Admit Cards can be Downloaded from 05-01-2012 17:00 hrs onwards by clicking ‘Application Status’

Click here to Download LAST 10 YEARS GATE QUESTION PAPERS ECE, CSE, IT, EEE, MECH etc.

GATE-2012 (Graduate Aptitude Test in Engineering) Notification & Important Dates.

Graduate Aptitude Test in Engineering (GATE) is an all India examination administered and conducted jointly by the Indian Institute of Science and seven Indian Institutes of Technology on behalf of the National Coordination Board – GATE, Department of Higher Education, Ministry of Human Resource Development (MHRD), Government of India.

The GATE committee, which comprises of representatives from the administering institutes, is the sole authority for regulating the examination and declaring the results.

GATE is conducted through the constitution of eight zones. The zones and the corresponding administrative institutes are:

Zone-1: Indian Institute of Science Bengaluru
Zone-2: Indian Institute of Technology Bombay
Zone-3: Indian Institute of Technology Delhi
Zone-4: Indian Institute of Technology Guwahati
Zone-5: Indian Institute of Technology Kanpur
Zone-6: Indian Institute of Technology Kharagpur
Zone-7: Indian Institute of Technology Madras
Zone-8: Indian Institute of Technology Roorkee

The overall coordination and responsibility of conducting GATE 2012 lies with Indian Institute of Technology Delhi, designated as the Organising Institute for GATE 2012 .

Admission to postgraduate programmes with MHRD and some other Government scholarships/assistantships in engineering colleges/institutes is open to those who qualify in GATE examination. GATE qualified candidates with Bachelor’s degree in Engineering/Technology/Architecture or Master’s degree in any branch of Science/Mathematics/Statistics/Computer Applications are eligible for admission to Master’s degree programmes in Engineering/Technology/Architecture as well as for Doctoral programmes in relevant branches of Science with MHRD or other government scholarships/assistantships. To avail the scholarship, the candidate must secure admission to such a postgraduate programme, as per the prevailing procedure of the admitting institution. However, candidates with Master’s degree in Engineering/Technology/Architecture may seek admission to relevant Doctoral programmes with scholarship/assistantship without appearing in the GATE examination.

GATE qualification is also a minimum requirement to apply for various fellowships awarded by many Government organizations.

Date of Online Examination: 29-01-2012 (Sunday)          Date of Offline Examination: 12-02-2012 (Sunday)

Eligibility for GATE Examination :

The following categories of candidates are eligible to appear for GATE 2012 :

• Bachelor’s degree holders in Engineering/Technology/ Architecture (4 years after 10+2) and those who are in the final year of such programmes.
• Master’s degree holders in any branch of Science/Mathematics/ Statistics/Computer Applications or equivalent and those who are in the final year of such programmes.
• Candidates in the second or higher year of the Four-year Integrated Master’s degree programme (Post-B.Sc.) in Engineering/Technology.
• Candidates in the fourth or higher year of Five-year Integrated Master’s degree programme or Dual Degree programme in Engineering/Technology.
• Candidates with qualifications obtained through examinations conducted by professional societies recognized by UPSC/AICTE (e.g. AMIE by Institute of Engineers (India); AMICE by Institute of Civil Engineers (India)) as equivalent to B.E./B.Tech. Those who have completed section A or equivalent of such professional courses are also eligible.

Commencement of Online Application Submission	Monday	12 September 2011 (00:00 Hrs)
Last date for Submission of Online Application (website closure)	Monday	17 October 2011 (23:00 Hrs)
Last date for the receipt of printed version of ONLINE Application at the respective zonal GATE Office	Monday	24 October 2011
Zonal GATE website display of final list of registered candidates, choices of test paper and examination city	Friday	09 December 2011
Availability of admit card on zonal GATE websites	Monday	02 January 2012
GATE 2012 Online Examination for Papers: AR, GG and TF	Sunday	29 January 2012 (09:00 Hrs to 12:00 Hrs)
GATE 2012 Online Examination Papers: AE, AG and MN	Sunday	29 January 2012 (14:00 Hrs to 17:00 Hrs)
GATE 2012 Offline Examination Papers: BT, CE, CH, CS, ME, PH and PI	Sunday	12 February 2012 (09:00 Hrs to 12:00 Hrs)
GATE 2012 Offline Examination Papers: CY, EC, EE, IN, MA, MT, XE and XL	Sunday	12 February 2012 (14:00 Hrs to 17:00 Hrs)
Announcement of Results	Thursday	15 March 2012 (10:00 Hrs)

What is New in GATE 2012?

Application Process:

In GATE 2012, candidates need to register and fill the application ONLINE only by accessing the zonal GATE websites of IISc and seven IITs. The application process is complete only when a print out of the filled ONLINE application with the candidate’s signature and a good quality photo affixed in the appropriate place is received by the respective GATE office along with necessary documents, if any, on or before 24 October 2011. Please note that sale of application forms through banks and GATE office counters has been discontinued.

Downloadable Admit Card:

Sending Admit cards by post has been discontinued from this year. Admit cards can only be downloaded from the zonal GATE websites from 2nd January 2012. Bring the admit card to the test center along with at least one original (not photocopied / scanned copy) and valid (not expired) photo identification.

ONLINE examination in two additional papers:

In GATE 2011, the papers with codes GG, TF, AE and MN had ONLINE examination. In GATE 2012, two additional papers, AR and AG, will also have ONLINE examination. The ONLINE examination will be conducted in two sessions on Sunday, January 29, 2012.

Forenoon session (09:00 hrs to 12:00 hrs): AR, GG and TF.

Afternoon session (14:00 hrs to 17:00 hrs): AE, AG and MN.

Numerical answer type questions in ONLINE papers:

In the ONLINE papers (AE, AG, AR, GG, MN and TF), the question paper will consist of questions of multiple choice type and questions of numerical answer type. For multiple choice type questions, each question will have four choices for the answer. For numerical answer type questions, each question will have a number as the answer. The number of numerical answer type questions may vary between 5 and 10 in each question paper.

Pre-final year students:

Pre-final year students are not eligible to write GATE 2012. For details, refer to eligibility for GATE examination.

GATE Examination Schedule :

GATE 2012 Examination will include both ONLINE and OFFLINE examinations as per the following schedule:

Type	Date	Time	Paper Codes
Online	29 January 2012 (Sunday)	09:00 Hrs to 12:00 Hrs	AR, GG and TF
		14:00 Hrs to 17:00 Hrs	AE, AG and MN
Offline	12 February 2012 (Sunday)	09:00 Hrs to 12:00 Hrs	BT, CE, CH, CS, ME, PH and PI
		14:00 Hrs to 17:00 Hrs	CY, EC, EE, IN, MA, MT, XE and XL

How to Apply?

Candidates have to apply only Online. The application fee and the steps in the application process are given below.

Category	Application Fee
General/OBC	Rs.1000/-
SC / ST /   PD	Rs.500/-

PD: Person with Disability

Application Process Step 1:Decide Payment Option Gateway Payment: Payment can be made using netbanking. Banking service charge is extra (maximum of Rs.30/-) Challan Payment: Payment by cash at ICICI, Indian Bank or State Bank of India branches. Bank service charge is extra (maximum of Rs.25/-) Step 2: Obtain SC / ST / PD Certificate (if applicable) Authorities empowered to issue Certificates Step 3: Apply Online Candidates must follow the instructions provided while applying online. At the end of this process, a PDF file will be generated with the following pages: Page-1: Instructions Page-2: GATE 2012 Application – GATE Copy Page-3: GATE 2012 Application – Candidate’s Copy Page-4: Address Slip of respective zonal GATE office Page-5: Bank Challan (for Challan Payment option only) Take a print out of the entire file. Step 4: Cash Payment: (only for Challan Payment option) The bank challan (Page-5) will be printed in triplicate. Take it to any one of the branches of ICICI, Indian Bank or State Bank of India (as opted by the candidate) and pay the fees. Bank will retain a copy with them and will return two copies to you. In those two copies, retain the Candidate’s copy with you and attach the GATE Copy with the application. Step 5: Paste your recent photograph (3 cm X 4 cm) in the designated place of Page-2. Sign at the designated places of Page-2. Paste the Page-4 on top of a A4-size envelope. Step 6: Post/Submission Before posting your application form, make sure that, in addition to the other relevant attachments, you have attached either a copy of the degree certificate or a certificate from your college principal as indicated below: Candidates should submit a copy of the degree certificate or provisional certificate if they have passed their qualifying degree in 2011 or before. Candidates with the following eligibility conditions should submit a certificate signed by the Principal of the college, where the candidate is studying, clearly indicating the year of passing of the candidate in the qualifying degree. Students in the final year of Bachelor’s degree programme in Engineering/Technology/ Architecture (4 years after 10+2). Students in the final year of Master’s degree programmes in any branch of Science/Mathematics/ Statistics/Computer Applications or equivalent. Students in the second or higher year of the Four-year Integrated Master’s degree programme (Post-B.Sc.) in Engineering/Technology. Students in the fourth or higher year of Five-year Integrated Master’s degree programme or Dual Degree programme in Engineering/Technology. To download the format of the certificate to be sent by the candidates, Click Here. Duly filled-in Application with appropriate enclosures must be sent by Speed Post (preferably) or by Registered Post to The Chairman, GATE of the Zone, corresponding to the 1st Choice of Examination City to appear for the examination, so as to reach on or before Monday, 24th October, 2011 (OR) It can be handed over personally to Respective Zonal GATE Office.

Click the below links to Download GATE Information Brochure :

LINK 1

(OR)

LINK 2

(OR)

LINK 3

Download Syllabus for GATE-2012 Papers

General Aptitude (GA) component common in all papers
AE: Aerospace Engineering	XE Section A: Engineering Mathematics
AG: Agricultural Engineering	XE Section B: Fluid Mechanics
AR: Architecture and Planning	XE Section C: Materials Science
BT: Biotechnology	XE Section D: Solid Mechanics
CE: Civil Engineering	XE Section E: Thermodynamics
CH: Chemical Engineering	XE Section F: Polymer Science and Engineering
CS: Computer Science and Information Technology	XE Section G: Food Technology
CY: Chemistry
EC: Electronics and Communication Engineering	XL Section H: Chemistry
EE: Electrical Engineering	XL Section I: Biochemistry
GG: Geology and Geophysics	XL Section J: Botany
IN: Instrumentation Engineering	XL Section K: Microbiology
MA: Mathematics	XL Section L: Zoology
ME: Mechanical Engineering	XL Section M: Food Technology
MN: Mining Engineering
MT: Metallurgical Engineering
PH: Physics
PI: Production and Industrial Engineering
TF: Textile Engineering and Fibre Science

Click here to Download LAST 10 YEARS GATE QUESTION PAPERS ECE, CSE, IT, EEE, MECH etc.

Click here to know more info about GATE-2012

Admit Cards can be Downloaded from 05-01-2012 17:00 hrs onwards by clicking  ‘Application Status’

JNTU-KAKINADA : Revised Course Structure and Syllabus-B.Tech (CSE and IT)-II YEAR-I Semester (R10 Students).

II B.TECH. – I SEMESTER (COMMON FOR COMPUTER SCIENCE ENGINEERING AND INFORMATION TECHNOLOGY)

REVISED COURSE STRUCTURE AND SYLLABUS – 2010-11 BATCH

II Year – I Semester

I SEMESTER		P	C
S.No.	Subject	P	C
1	Managerial Economics and Financial Analysis	4+1*	4
2	Probability & Statistics	4+1*	4
3	Mathematical Foundations of Computer  Science and Engineering	4+1*	4
4	Digital Logic Design	4+1*	4
5	Electronic Devices and Circuits	4+1*	4
6	Data Structures	4+1*	4
7	Electronic Devices and Circuits Lab	3	2
8	Data Structures Lab	3	2
9	Professional Communicational skills	2	1
Total Credits			29

*Tutorial

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY KAKINADA

B.TECH. (COMPUTER SCIENCE AND ENGINEERING)

II Year B.Tech. – I Semester

DIGITAL LOGIC DESIGN

Unit  I : Number Systems

Binary, Octal, Decimal, Hexadecimal Number Systems. Conversion of Numbers From One Radix To Another Radix , r’s Complement and (r-1)’s Complement Subtraction of Unsigned Numbers, Problems, Signed Binary Numbers, Weighted and Non weighted codes

Unit II:Logic Gates And Boolean Algebra

Basic Gates NOT, AND, OR, Boolean Theorms,Complement And Dual of Logical Expressions, Universal Gates, Ex-Or and Ex-Nor Gates, SOP,POS, Minimizations of Logic Functions Using Boolean Theorems, Two level Realization of Logic Functions Using Universal Gates.  Verilog programming for the minimized logic functions.

Unit III: Gate- Level Minimization

Karnaugh Map Method(K-Map): Minimization of Boolean Functions maximum upto  Four Variables , POS And SOP, Simplifications With Don’t Care Conditions Using K-Map.

Unit IV: Combinational Arithmetic Logic Circuits

Design of Half Adder, Full Adder, Half Subtractor ,  Full Subtractor, Ripple Adders and Subtractors, Ripple Adder/Subtractor Using Ones and Twos Complement Method. Serial Adder , Carry Look Ahead Adder.

Unit V: Combinational Logic Circuits

Design of Decoders, Encoders, Multiplexers, Demultiplexers, Higher Order Demultiplexers and Multiplexers, Realization of Boolean Functions Using Decoders and Multiplexers, Priority Encoder, Code Converters, Magnitude Comparator.

Unit VI:  Introduction to Programmable Logic Devices (PLOs)

PLA, PAL, PROM. Realization of Switching Functions Using PROM, PAL and PLA. Comparison of PLA, PAL and PROM..

Unit VII: Introduction to Sequential Logic Circuits

Classification of Sequential Circuits, Basic Sequential Logic Circuits: Latch and Flip-Flop, RS- Latch Using NAND and NOR Gates, Truth Tables. RS,JK,T and D Flip Flops , Truth and Excitation Tables, Conversion of Flip Flops. Flip Flops With Asynchronous Inputs (Preset and Clear).

Unit VIII: Registers and Counters

Design of Registers, Buffer Register, Control Buffer Registers, Bidirectional Shift Registers, Universal Shift Register, Design of Ripple Counters, Synchronous Counters and Variable Modulus Counters, Ring Counter, Johnson Counter.

TEXT BOOKS :

1. Digital Design ,4/e, M.Morris Mano, Michael D  Ciletti, PEA

2. Fundamentals of Logic Design, 5/e, Roth, Cengage

REFERENCE  BOOKS :

1. Switching and Finite Automata Theory,3/e,Kohavi, Jha, Cambridge.

2. Digital Logic Design, Leach, Malvino, Saha,TMH

3.Modern Digital Electronics, R.P. Jain, TMH

B.TECH. (COMPUTER SCIENCE AND ENGINEERING)

II Year B.Tech. – I Semester

ELECTRONIC DEVICES AND CIRCUITS

Unit-I

Electron Ballistics and Applications: Force on Charged Particles in Electric field, Constant Electric Field, Potential, Relationship between Field Intensity and Potential, Two Dimensional Motion, Electrostatic Deflection in Cathode ray Tube, CRO, Force in Magnetic Field, Motion in Magnetic Field, Magnetic Deflection in CRT, Magnetic Focusing, Parallel Electric and Magnetic fields and Perpendicular Electric and Magnetic Fields.

Unit- II

Review of Semi Conductor Physics : Insulators, Semi conductors, and Metals classification using Energy Band Diagrams, Mobility and Conductivity, Electrons and holes in Intrinsic Semi conductors, Extrinsic Semi Conductor, (P and N Type semiconductor) Hall effect, Generation and Recombination of Charges, Diffusion, Continuity Equation, Injected Minority Carriers, Law of Junction, Fermi Dirac Function, Fermi level in Intrinsic and Extrinsic Semiconductor

Unit- III

Junction Diode Characteristics  : Open circuited P N Junction, Forward and Reverse Bias, Current components in PN Diode, Diode Equation,Volt-Amper Characteristic, Temperature Dependence on V – I characteristic, Step Graded Junction, Diffusion Capacitance and Diode Resistance (Static and Dynamic), Energy Band Diagram of PN Diode,

Special Diodes: Avalanche and Zener Break Down, Zener Characterisitics,  Tunnel Diode, Characteristics with the help of Energy Band Diagrams, Varactor Diode, LED, PIN Diode,  Photo Diode

Unit IV

Rectifiers and Filters: Half wave rectifier, ripple factor, full wave rectifier(with and without transformer), Harmonic components in a rectifier circuit, Inductor filter, Capacitor filter, L- section filter, P- section filter, Multiple L- section and Multiple  P section filter, and comparison of various filter circuits  in  terms of ripple factors, Simple circuit of a regulator using zener diode, Series and Shunt voltage regulators

Unit- V

Transistors :

Junction transistor, Transistor current components, Transistor as an amplifier, Characteristics of Transistor in Common Base and  Common Emitter Configurations, Analytical expressions for Transistor Characteristics, Punch Through/  Reach Through, Photo Transistor, Typical transistor junction voltage values.

Unit VI

Field Effect Transistors:

JFET characteristics (Qualitative and Quantitative discussion), Small signal model of JFET, MOSFET characteristics (Enhancement and depletion mode), Symbols of MOSFET, Introduction to SCR and UJT and their characteristics,

UNIT-VII

Transistor Biasing and Thermal Stabilization : Transistor Biasing and Thermal Stabilization: Operating point, Basic Stability, Collector to Base Bias, Self Bias Amplifiers, Stabilization against variations in V_BE,, and ? for the self bias circuit, Stabilization factors, (S, S^‘, S^‘’), Bias Compensation,  Thermistor and Sensitor compensation,   Compensation against variation in V_BE, I_co,,  Thermal runaway, Thermal stability

UNIT- VIII

Small signal low frequency Transistor models: Two port devices and the Hybrid model, Transistor Hybrid model, Determination of h-parameters from characteristics, Measurement of h-parameters, Conversion formulas for the parameters of three transistor configurations, Analysis of a Transistor Amplifier circuit using h- parameters, Comparison of Transistor Amplifier configurations

Text Books

1.  Electronic Devices and Circuits – J. Millman,  C.C. Halkias,  Tata Mc-Graw Hill

Reference

1.  Electronic Devices and Circuits – K Satya Prasad,  VGS Book Links

2.  Integrated Electronics – Jacob Millman,  Chritos C. Halkies,, Tata Mc-Graw Hill, 2009

3. Electronic Devices and Circuits – Salivahanan, Kumar, Vallavaraj, TATA McGraw Hill, Second Edition

4. Electronic Devices and Circuits – R.L. Boylestad and Louis Nashelsky, Pearson/Prentice Hall,9thEdition,2006

5. Electronic Devices and Circuits -BV Rao, KBR Murty, K Raja Rajeswari, PCR Pantulu, Pearson, 2^nd edition

***

B.TECH. (COMPUTER SCIENCE AND ENGINEERING)

II Year B.Tech. – I Semester

DATA STRUCTURES

UNIT I: Recursion and Linear Search:

Preliminaries of algorithm,  Algorithm analysis and complexity.

Recursion: Definition, Design Methodology and Implementation of recursive algorithms, Linear and binary recursion, recursive algorithms for factorial function, GCD computation, Fibonacci sequence, Towers of Hanoi, Tail recursion

List Searches using Linear Search, Binary Search, Fibonacci Search,

UNIT II: Sorting Techniques:

Basic concepts, Sorting by : insertion (Insertion sort), selection (heap sort), exchange (bubble sort, quick sort), distribution (radix sort ) and merging  (merge sort )  Algorithms.

UNIT III: Stacks and Queues:

Basic Stack Operations, Representation of a Stack using Arrays, Stack Applications: Reversing list,   Factorial Calculation, In-fix- to postfix Transformation, Evaluating Arithmetic Expressions.

Queues: Basic Queues Operations, Representation  of a  Queue using array, Implementation of Queue Operations using Stack,  Applications of Queues-Round robin Algorithm, Enqueue,  Dequeue, Circular Queues,   Priority Queues.

UNIT IV:  Linked Lists:

Introduction, single linked list, representation of a linked list in memory, Operations on a single linked list, merging two single linked lists into one list, Reversing a   single  linked list, applications of single linked list to represent polynomial expressions and sparse matrix manipulation, Advantages and disadvantages of single  linked list, Circular linked list,  Double linked list

UNIT V: Trees:

Basic tree concepts, Binary Trees: Properties, Representation of Binary Trees using arrays and linked lists, operations on a Binary tree , Binary Tree Traversals (recursive), Creation of binary tree from in-order and pre(post)order traversals,

UNIT VI: Advanced concepts of Trees:

Tree Travels using stack (non recursive), Threaded Binary Trees. Binary search tree, Basic concepts, BST operations: insertion, deletion,

Balanced binary trees – need, basics and applications in computer science (No operations )

UNIT VII: Graphs:

Basic concepts, Representations of Graphs: using Linked list and adjacency matrix, Graph algorithms

Graph Traversals (BFS & DFS), applications: Dijkstra’s shortest path, Transitive closure, Minimum Spanning Tree using     Prim’s Algorithm, warshall’s Algorithm.

Unit VIII: Sets:

Definition, Representation of Sets using Linked list, operations of sets using linked lists, application of sets- Information storage using bit strings

Abstract Data Type Introduction to abstraction, Model for an Abstract Data Type, ADT Operations, ADT Data Structure, ADT Implementation of stack and queue .

TEXT BOOKS:

1.      Data Structures, 2/e, Richard F, Gilberg , Forouzan, Cengage

2.      Data Structures and Algorithms, 2008,G.A.V.Pai, TMH

REFERENCE  BOOKS:

1.      Data Structure with C, Seymour Lipschutz, TMH

2.      Classic Data Structures, 2/e, Debasis ,Samanta,PHI,2009

3.      Fundamentals of Data Structure in C, 2/e, Horowitz,Sahni, Anderson Freed,University Prees

B.TECH. (COMPUTER SCIENCE AND ENGINEERING)

II Year B.Tech. – I Semester

ELECTRONIC DEVICES AND CIRCUITS LAB

PART A : (Only for viva voce Examination)

ELECTRONIC WORKSHOP PRACTICE ( in 6 lab sessions) :

1. Identification, Specifications, Testing of R, L, C Components (Colour Codes), Potentiometers, Switches (SPDT, DPDT, and DIP), Coils, Gang Condensers, Relays, Bread Boards.

2. Identification, Specifications and Testing of Active Devices, Diodes, BJTs, Lowpower JFETs, MOSFETs, Power Transistors, LEDs, LCDs, Optoelectronic Devices, SCR, UJT, DIACs, TRIACs, Linear and Digital ICs.

3. Soldering practice – Simple Circuits using active and passive components.

4. Single layer and Multi layer PCBs (Identification and Utility).

5. Study and operation of

• Multimeters (Analog and Digital)

• Function Generator

• Regulated Power Supplies

1. Study and Operation of CRO.

PART B : (For Laboratory examination – Minimum of 10 experiments)

1.  Frequency measurment using Lissajous Figures

2. PN Junction diode characteristics   A. Forward bias  B. Reverse bias.( cut-in voltage & Resistance calculations)

3. Zener diode characteristics and Zener as a regulator

4. Transistor CB characteristics (Input and Output) & h Parameter calculations

5. Transistor CE characteristics (Input and Output) & h Parameter calculations

6. Rectifier without filters (Full wave & Half wave)

7. Rectifier with filters (Full wave & Half wave)

8. FET characteristics

9. SCR Charecteristics

10. UJT Charectristics

11. CE Amplifier

12. CC Amplifier (Emitter Follower).

PART C:

Equipment required for Laboratories:

1. Regulated Power supplies (RPS)                        -           0-30v
2. CROs                                                              -           0-20M Hz.
3. Function Generators                                         -           0-1 M Hz.
4. Multimeters
5. Decade Resitance Boxes/Rheostats
6. Decade Capacitance Boxes
7. Micro Ammeters (Analog or Digital)                 -           0-20 µA, 0-50µA, 0-100µA, 0-                                                                                              200µA
8. Voltmeters (Analog or Digital)                         -           0-50V, 0-100V, 0-250V
9. Electronic Components                                   -          Resistors, Capacitors, BJTs, LCDs,                                                                                        SCRs,  UJTs, FETs, LEDs,

MOSFETs,diodes,transistors

***

Click on the below link to Download the Official Notification :

JNTU-KKD : Revised Course Structure and Syllabus-B.Tech (CSE and IT)-II YEAR-I Semester (R10 Students).