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18CS33
Analog and Digital Electronics
Time: 3 hrs. Max. Marks: 100
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Note: Answer any FIVE full questions, choosing ONE full question from eachModule-1.
Explain the construction, working and characteristics of photo.. diode.
With hysteresis characteristics explain the working of Schmitt :trigger circuit (
module.
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(06 Marks)Inverting).
(06 Marks)
bias circuit.
(08 Marks)
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With a neat circuit diagram and mathematical analysis explain voltage dividerOR
2 a. Explain the working of R-2R ladder D to A converter.
b. EXplain successive approximation A to D converter.
c. Show how IC-555 timer can be used as an astable multivibrator.
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(06 Marks)(06 Ma rks)
(08 Marks)
Module-2
3 a. Find the minimum SOP and minimum PUS expressions for the following function using
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K-map. f(A, B, C, D) = En
, (1, 3, 4, 11) + Ed (2, 7, 8, 12, 14, 15). (06 Marks)
b. What are the disadvantages of K-map method? How they are overcome in Quine Mccluskey
method. Simplify following function using Q-M method
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f(A, B, C, D) = Ern
(0, 1, 2, 5, 6, 7, 8, 9, 10, 14), (08 Marks)
C.
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What is Map-Entered Variable method? Using MEV method simplify following function:f(A, B, C, D) = E
n
, (2, 3, 4, 5, 13, 15) + dc(8, 9 10, 11). (06 Marks)
OR
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4 a. With the help of flow chart explain how to determine 'Minimum sum of products usingKarnaugh map. (06 Marks)
b. Using Q-M method simplify the following function
F(A, B, C, D) = E
m
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(2, 3, 7, 9,I1, 13)+ (l,, 10, 1:
5). (08 Marks)
C.
With example explain Petrik's method. (06 Marks)
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Module-35 a. What are hazards in digital circuits? Explain different types of hazards. (06 Marks)
b: Implement full subtractor using 3 to 8 decoder and NAND gates. (06 Marks)
C. Differentiate between PAL and PLA. Realize following functions using PLA. Give PLA
table and internal connection diagram for the PLA (Use as many common terms as possible)
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Fi
(1, b, c, E,?(1, 2, 4, 5, 6,.8,10, 12, 14)
F
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(a, b, c, d) = E, (2, 4, 6, 8, 10, 11, 12, 14, 15)(08 Marks)
OR
6 a. What is Multiplexer? Implement following function using 8:1 MUX
f(A, B, C, D) E
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m(1, 2, 5, 6, 9, 12)
(08 Marks)
b.
Design Hexadecimal (Binary) to ASCII Code Converter using suitable ROM. Give the
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connection diagram of ROM.(06 Marks)
c. Explain Simulation and testing of digital circuits.
(06 Marks)
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1_ _aiii.2020
18CS33
Analog and Digital Electronics
--- Content provided by FirstRanker.com ---
Time: 3 hrs. Max. Marks: 100Note: Answer any FIVE full questions, choosing ONE full question from each
Module-1.
Explain the construction, working and characteristics of photo.. diode.
With hysteresis characteristics explain the working of Schmitt :trigger circuit (
--- Content provided by FirstRanker.com ---
module.(06 Marks)
Inverting).
(06 Marks)
bias circuit.
--- Content provided by FirstRanker.com ---
(08 Marks)With a neat circuit diagram and mathematical analysis explain voltage divider
OR
2 a. Explain the working of R-2R ladder D to A converter.
b. EXplain successive approximation A to D converter.
--- Content provided by FirstRanker.com ---
c. Show how IC-555 timer can be used as an astable multivibrator.(06 Marks)
(06 Ma rks)
(08 Marks)
Module-2
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3 a. Find the minimum SOP and minimum PUS expressions for the following function usingK-map. f(A, B, C, D) = E
n
, (1, 3, 4, 11) + Ed (2, 7, 8, 12, 14, 15). (06 Marks)
b. What are the disadvantages of K-map method? How they are overcome in Quine Mccluskey
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method. Simplify following function using Q-M methodf(A, B, C, D) = E
rn
(0, 1, 2, 5, 6, 7, 8, 9, 10, 14), (08 Marks)
C.
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What is Map-Entered Variable method? Using MEV method simplify following function:
f(A, B, C, D) = E
n
, (2, 3, 4, 5, 13, 15) + dc(8, 9 10, 11). (06 Marks)
--- Content provided by FirstRanker.com ---
OR4 a. With the help of flow chart explain how to determine 'Minimum sum of products using
Karnaugh map. (06 Marks)
b. Using Q-M method simplify the following function
F(A, B, C, D) = E
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m(2, 3, 7, 9,I1, 13)+ (l,, 10, 1
:
5). (08 Marks)
C.
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With example explain Petrik's method. (06 Marks)Module-3
5 a. What are hazards in digital circuits? Explain different types of hazards. (06 Marks)
b: Implement full subtractor using 3 to 8 decoder and NAND gates. (06 Marks)
C. Differentiate between PAL and PLA. Realize following functions using PLA. Give PLA
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table and internal connection diagram for the PLA (Use as many common terms as possible)F
i
(1, b, c, E,?(1, 2, 4, 5, 6,.8,10, 12, 14)
F
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2(a, b, c, d) = E, (2, 4, 6, 8, 10, 11, 12, 14, 15)
(08 Marks)
OR
6 a. What is Multiplexer? Implement following function using 8:1 MUX
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f(A, B, C, D) Em
(1, 2, 5, 6, 9, 12)
(08 Marks)
b.
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Design Hexadecimal (Binary) to ASCII Code Converter using suitable ROM. Give theconnection diagram of ROM.
(06 Marks)
c. Explain Simulation and testing of digital circuits.
(06 Marks)
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full adder as component. (08 Marks)
b. Explain the working of SR latch using NOR gates. Show how SR latch can be used for
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switch debouncing. (07 Marks)c. Differentiate between Latch and Flip Flop. Show how SR flipflop can be converted to D flip
flop. (05 Marks)
OR
8 a. Derive the characteristics equations for D, T, SR and JK flipflops. (08 Marks)
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b. Draw the logic diagram of master slave JK flipflop using NAND gates and explain theworking with suitable timing diagram. (07 Marks)
c. With example explain the syntax of conditional signal assignment statement in VHDL.
(05 Marks)
Module-5
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9 a. What is shift register? Explain the working of 8 bit SISO shift register using SR flip flop.(06 Marks`
b.
With the help of state graph, state and transition tables and timing diagram explair*
sequential parity checker. (06 Marks)
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C.Design a random counter using T flip flops whose transition graph is shown in Fig.Q.9(c).
(08 Marks)
Fig.Q.9(c)
OR
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10 a. What is register? Explain how 4 bit register with data, load, clear and clock input isconstructed using D flip flops. (06 Marks)
b. With a block diagram explain the working of n-bit parallel adder with accumulator.
(06 Marks)
C.
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Differentiate between Moore and Melay machines. Analyze following Moore sequentialcircuit for an input sequence of X = 01101 and draw the timing diagram. (08 Marks)
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