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Download ARPIT 2020 A Practical Refresher In Computer Engineering Creation Question Paper

Download Annual Refresher Programme in Teaching (ARPIT) 2020 A Practical Refresher In Computer Engineering Creation Previous Question Paper || Annual Refresher Programme in Teaching (ARPIT) Last 10 Years Question Paper

This post was last modified on 19 January 2021

Tags:ARPIT2020Computer EngineeringQuestion PaperPrevious YearfrdA190121A2111867downloadpractical refreshercreation
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ARPIT Last 10 Years 2011-2021 Previous Question Papers


Question Paper Name: A Practical Refresher in Computer Engineering 16th February 2020 Shift 1

Subject Name: A Practical Refresher in Computer Engineering

Creation Date: 2020-02-16 12:58:19

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Duration: 180

Total Marks: 140

Display Marks: Yes

A Practical Refresher in Computer Engineering

Group Number : 1

Group Id : 28860721

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Group Maximum Duration : 0

Group Minimum Duration : 120

Show Attended Group? : No

Edit Attended Group? : No

Break time: 0

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Group Marks: 140

Is this Group for Examiner?: No

A Practical Refresher in Computer Engineering

Section Id : 2886

Section Number : 4

Section type : Online

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Mandatory or Optional: Mandatory

Number of Questions: 70

Number of Questions to be attempted: 70

Section Marks: 140

Sub-Section Number: 1

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Sub-Section Id: 28860724

Question Shuffling Allowed : Yes

Question Number: 1 Question Id : 2886071886 Question Type : MCQ Option Shuffling : No

Correct Marks: 2 Wrong Marks : 1

The von Neumann architecture of a computer talks about: (choose the BEST option).

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  1. higher level algorithms
  2. the stored program concept
  3. automata in hardware
  4. functional programming

Options:

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2886077534. 1

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2886077536. 3

2886077537. 4

Question Number: 2 Question Id : 2886071887 Question Type : MCQ Option Shuffling: No

Correct Marks : 2 Wrong Marks : 1

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Which ONE of the following is NOT an abstract component of a von Neumann computer?

  1. Control Path
  2. Data Path
  3. Management Path
  4. Memory

    5. --- Content provided by FirstRanker.com ---

Options:

2886077538. 1

2886077539. 2

2886077540. 3

2886077541. 4

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Question Number : 3 Question Id : 2886071888 Question Type : MCQ Option Shuffling: No

Correct Marks: 2 Wrong Marks : 1

In MIPS32, the '32' indicates:

  1. The number of instructions possible
  2. The width in bits of the memory address

    3. --- Content provided by‍ FirstRanker.com ---

  3. The number of R-type instructions
  4. The number of pipeline stages

Options:

2886077542. 1

2886077543. 2

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2886077544. 3

2886077545. 4

Question Number : 4 Question Id : 2886071889 Question Type : MCQ Option Shuffling: No

Correct Marks: 2 Wrong Marks : 1

hat MIPS32 uses 2's complement notation for the immediate operand, which ONE of the following is NOT a valid section?

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  1. Iw
  2. sw
  3. sub
  4. subi

Options:

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2886077546. 1

2886077547. 2

2886077548. 3

2886077549. 4

Question Number: 5 Question Id : 2886071890 Question Type : MCQ Option Shuffling: No

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Correct Marks : 2 Wrong Marks : 1

Which ONE of the following MIPS instructions would you use IDEALLY to multiply the value of a register by 4 ?

  1. mul
  2. muli
  3. sll

    4. --- Content provided by‍ FirstRanker.com ---

  4. srl

Options:

2886077550. 1

2886077551. 2

2886077552. 3

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2886077553. 4

Question Number: 6 Question Id : 2886071891 Question Type : MCQ Option Shuffling: No

Correct Marks: 2 Wrong Marks : 1

In the MIPS32 instruction set, branch based on if-less-than comparison _______

  1. is not supported at all

    2. --- Content provided by FirstRanker.com ---

  2. is supported in a single instruction
  3. is supported as a pair of instructions
  4. is possible only if one of the values is zero

Options:

2886077554. 1

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2886077555. 2

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Question Number : 7 Question Id : 2886071892 Question Type : MCQ Option Shuffling: No

Correct Marks: 2 Wrong Marks : 1

In MIPS, callee-saved registers are also called _______

  1. preserved

    2. --- Content provided by⁠ FirstRanker.com ---

  2. unpreserved
  3. intermediate
  4. shadow

Options:

2886077558. 1

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2886077559. 2

2886077560. 3

2886077561. 4

Question Number: 8 Question Id : 2886071893 Question Type : MCQ Option Shuffling : No

Correct Marks: 2 Wrong Marks : 1

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In MIPS, callee-saved registers are saved onto _______

  1. swap memory
  2. the process stack
  3. dynamic heap memory
  4. static global memory

    5. --- Content provided by‍ FirstRanker.com ---

Options:

2886077562. 1

2886077563. 2

2886077564. 3

2886077565. 4

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Question Number : 9 Question Id : 2886071894 Question Type : MCQ Option Shuffling: No

Correct Marks : 2 Wrong Marks : 1

ONE of the following integer notations has a unique representation for the number 0?

  1. sign-magnitude
  2. 1's complement

    3. --- Content provided by⁠ FirstRanker.com ---

  3. 2's complement
  4. None of the other options

Options:

2886077566. 1

2886077567. 2

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2886077568. 3

2886077569. 4

Question Number : 10 Question Id : 2886071895 Question Type : MCQ Option Shuffling: No

Correct Marks : 2 Wrong Marks : 1

In a MIPS program's memory, the global data is placed at the bottommost portion (lowest address starting from 0) of memory: _______ (choose the BEST option below).

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  1. only when the program is statically linked
  2. when the program has no dynamically allocated data
  3. never
  4. when the program has no function calls

Options:

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2886077570. 1

2886077571. 2

2886077572. 3

2886077573. 4

Question Number : 11 Question Id : 2886071896 Question Type : MCQ Option Shuffling : No

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Correct Marks: 2 Wrong Marks : 1

Which ONE of the following is true about the $at (assembler temporary) register in MIPS32 ?

  1. It is preserved, and it is temporarily stored in the heap
  2. It is preserved, and it is temporarily stored in the stack frame
  3. It is preserved, but it is not stored in the stack

    4. --- Content provided by​ FirstRanker.com ---

  4. It is caller-saved

Options:

2886077574. 1

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2886077576. 3

2886077577. 4

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Question Number : 12 Question Id : 2886071897 Question Type : MCQ Option Shuffling: No

Correct Marks: 2 Wrong Marks : 1

Which ONE of the following is true about the $ra (return address) register in MIPS32 ?

  1. It is preserved, and it is temporarily stored in the heap
  2. It is preserved, and it is temporarily stored in the stack frame

    3. --- Content provided by​ FirstRanker.com ---

  3. It is unpreserved
  4. It always has the value of 0xFFFFFFFC

Options:

2886077578. 1

2886077579. 2

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2886077580. 3

2886077581. 4

Question Number : 13 Question Id : 2886071898 Question Type : MCQ Option Shuffling: No

Correct Marks: 2 Wrong Marks : 1

In the context of computer performance quantification, SPEC is _______

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  1. a particular computer architecture with a rich instruction set
  2. a specification language for formal performance bounds
  3. a compiler with many optimization techniques
  4. a consortium of computer industries

Options:

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2886077582. 1

2886077583. 2

2886077584. 3

2886077585. 4

Question Number : 14 Question Id : 2886071899 Question Type : MCQ Option Shuffling : No

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Correct Marks: 2 Wrong Marks : 1

f the components of the computer performance equation does the choice of HLL (Higher Level Language) affect? Choose the BEST option below.

  1. Only the number of instructions
  2. Only the cycle time
  3. Both the number of instructions and the cycle time

    4. --- Content provided by⁠ FirstRanker.com ---

  4. Neither the number of instructions nor the cycle time

Options:

2886077586. 1

2886077587. 2

2886077588. 3

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2886077589. 4

Question Number : 15 Question Id : 2886071900 Question Type : MCQ Option Shuffling : No

Correct Marks: 2 Wrong Marks : 1

Which of the components of the computer performance equation does the instruction set architecture affect ? Choose the BEST option below.

  1. Only the number of instructions

    2. --- Content provided by⁠ FirstRanker.com ---

  2. Only the CPI
  3. Both the number of instructions and the CPI
  4. Neither the number of instructions nor the CPI

Options:

2886077590. 1

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2886077591. 2

2886077592. 3

2886077593. 4

Question Number : 16 Question Id : 2886071901 Question Type : MCQ Option Shuffling : No

Correct Marks: 2 Wrong Marks : 1

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Which ONE of the following is a valid return statement from an exception handler in a MIPS32 machine?

  1. jalr $ra
  2. jr $ra
  3. jr $k0
  4. jalr $at

    5. --- Content provided by​ FirstRanker.com ---

Options:

2886077594. 1

2886077595. 2

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Question Number : 17 Question Id : 2886071902 Question Type : MCQ Option Shuffling : No

Correct Marks: 2 Wrong Marks : 1

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Which ONE of the following limits the achievable performance improvement in a computer?

  1. Huddle space constraint
  2. Magnolias effect
  3. Amdahl's law
  4. Little's theorem

    5. --- Content provided by‌ FirstRanker.com ---

Options:

2886077598. 1

2886077599. 2

2886077600. 3

2886077601. 4

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Question Number : 18 Question Id : 2886071903 Question Type : MCQ Option Shuffling : No

Correct Marks: 2 Wrong Marks : 1

A program's CPI (Cycles Per Instruction) will most likely NOT be affected by the use of: (choose the BEST option)

  1. integer versus floating point arithmetic
  2. signed versus unsigned integers for small positive integer variables

    3. --- Content provided by FirstRanker.com ---

  3. optimization techniques employed by the compiler
  4. memory versus compute intensive algorithm

Options:

2886077602. 1

2886077603. 2

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2886077604. 3

2886077605. 4

Question Number : 19 Question Id : 2886071904 Question Type : MCQ Option Shuffling : No

Correct Marks: 2 Wrong Marks : 1

IPS32 5-stage pipeline, a sw followed by a lw causes a data hazard stall on a memory location (not a register)

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  1. always
  2. never
  3. when the Iw loads the base register of sw
  4. when the sw stores the base register of Iw

Options:

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2886077606. 1

2886077607. 2

2886077608. 3

2886077609. 4

Question Number : 20 Question Id : 2886071905 Question Type : MCQ Option Shuffling: No

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Correct Marks : 2 Wrong Marks : 1

In the MIPS32 5-stage pipeline, a Iw followed by another Iw causes a data hazard stall

  1. always
  2. never
  3. when the first Iw loads the base register of the second Iw

    4. --- Content provided by⁠ FirstRanker.com ---

  4. when the second lw loads the base register of the first Iw

Options:

2886077610. 1

2886077611. 2

2886077612. 3

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2886077613. 4

Question Number : 21 Question Id : 2886071906 Question Type : MCQ Option Shuffling : No

Correct Marks : 2 Wrong Marks : 1

In the MIPS32 5-stage pipeline, a sw followed by another sw causes a data hazard stall

  1. always

    2. --- Content provided by‌ FirstRanker.com ---

  2. never
  3. when the first sw stores the base register of the second sw
  4. when the second sw stores the base register of the first sw

Options:

2886077614. 1

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2886077615. 2

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Question Number : 22 Question Id : 2886071907 Question Type : MCQ Option Shuffling : No

Correct Marks: 2 Wrong Marks : 1

Which ONE of the following is true about structural hazards in a pipelined processor?

  1. they will result in performance degradation

    2. --- Content provided by‌ FirstRanker.com ---

  2. they will result in OS deadlocks
  3. they can be handled using data forwarding
  4. they can be handled using branch prediction

Options:

2886077618. 1

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2886077619. 2

2886077620. 3

2886077621. 4

Question Number : 23 Question Id : 2886071908 Question Type : MCQ Option Shuffling : No

Correct Marks: 2 Wrong Marks : 1

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In the MIPS32 5-stage pipeline implementation, the register file is written in the first half and read in the second half of a cycle. Why? (choose the BEST option below).

  1. This avoids expensive structural hazards in the register file for each instruction
  2. This reduces instances of control hazard stalls
  3. This reduces chances of pipeline exceptions
  4. This leads to lesser cache misses

    5. --- Content provided by⁠ FirstRanker.com ---

Options:

2886077622. 1

2886077623. 2

2886077624. 3

2886077625. 4

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Question Number : 24 Question Id : 2886071909 Question Type : MCQ Option Shuffling : No

Correct Marks : 2 Wrong Marks : 1

ONE of the following is an implication of control hazards in the MIPS32 5-stage pipeline?

  1. branch instructions take 6 cycles to complete instead of 3
  2. there are extra stalls in the pipeline after each branch instruction

    3. --- Content provided by⁠ FirstRanker.com ---

  3. structural hazards in branches face twice as many stalls compared to other instructions
  4. data forwarding becomes ineffective

Options:

2886077626. 1

2886077627. 2

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2886077628. 3

2886077629. 4

Question Number : 25 Question Id : 2886071910 Question Type : MCQ Option Shuffling: No

Correct Marks : 2 Wrong Marks : 1

The technique of loop unrolling can lead to lesser pipeline stalls. Which entity is responsible for such unrolling?

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  1. Operating System
  2. Dynamic Linker
  3. Compiler
  4. Terminal Shell

Options:

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2886077630. 1

2886077631. 2

2886077632. 3

2886077633. 4

Question Number : 26 Question Id : 2886071911 Question Type : MCQ Option Shuffling : No

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Correct Marks: 2 Wrong Marks : 1

Which ONE of the following is a compiler's role, in reducing branch penalty in the pipeline?

  1. replacing conditional branches with unconditional branches
  2. replacing unconditional branches with conditional branches
  3. scheduling useful instructions in the branch delay slot

    4. --- Content provided by⁠ FirstRanker.com ---

  4. making branch instructions always use the fp (frame pointer) register

Options:

2886077634. 1

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Question Number : 27 Question Id : 2886071912 Question Type : MCQ Option Shuffling: No

Correct Marks : 2 Wrong Marks : 1

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In the MIPS32 5-stage pipeline, what is the ideal CPI (Cycles Per Instruction), in the absence of hazards and stalls?

  1. 1/5
  2. 1
  3. 3
  4. 5

    5. --- Content provided by FirstRanker.com ---

Options:

2886077638. 1

2886077639. 2

2886077640. 3

2886077641. 4

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Question Number: 28 Question Id : 2886071913 Question Type: MCQ Option Shuffling: No

Correct Marks: 2 Wrong Marks : 1

Which ONE of the following techniques is for the purpose of reducing control hazards, and requires the role of the operating system?

  1. branch prediction
  2. early branch completion

    3. --- Content provided by‍ FirstRanker.com ---

  3. branch target buffer
  4. none of the other options

Options:

2886077642. 1

2886077643. 2

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2886077644. 3

2886077645. 4

Question Number : 29 Question Id : 2886071914 Question Type : MCQ Option Shuffling: No

Correct Marks: 2 Wrong Marks : 1

IPS32 5-istage pipeline, an add instruction is followed by a jump instruction. Unconditional branches take 2 cycle stalls to deal with control hazards. How many cycles of stall are required and when?

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  1. 1 cycle, between the add and jump
  2. 1 cycle, after the jump
  3. 2 cycles, between the add and jump
  4. 2 cycles, after the jump

Options:

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2886077646. 1

2886077647. 2

2886077648. 3

2886077649. 4

Question Number : 30 Question Id : 2886071915 Question Type : MCQ Option Shuffling : No

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Correct Marks: 2 Wrong Marks : 1

Which ONE of the following is true about 2-stage branch completion in the MIPS32 5-stage pipeline?

  1. this is possible only for unconditional branches
  2. this potentially introduces additional data hazards
  3. this requires the compiler to arrange branch instructions to be within 4 instructions of one another

    4. --- Content provided by‍ FirstRanker.com ---

  4. this requires the branch offset to be less than 256 in absolute value

Options:

2886077650. 1

2886077651. 2

2886077652. 3

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2886077653. 4

Question Number : 31 Question Id : 2886071916 Question Type : MCQ Option Shuffling : No

Correct Marks : 2 Wrong Marks : 1

In MIP32, a branch delay slot can ALWAYS be safely filled with an instruction from _______

  1. before the branch

    2. --- Content provided by​ FirstRanker.com ---

  2. the branch fall through
  3. the branch target
  4. none of the other options

Options:

2886077654. 1

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www.FirstRanker.com

2886077656. 3

2886077657. 4

Question Number : 32 Question Id : 2886071917 Question Type : MCQ Option Shuffling: No

Correct Marks : 2 Wrong Marks : 1

In MIP32, a branch delay slot can NEVER be filled with a _______ instruction.

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  1. nop
  2. load word
  3. store word
  4. jump

Options:

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2886077658. 1

2886077659. 2

2886077660. 3

2886077661. 4

Question Number : 33 Question Id : 2886071918 Question Type: MCQ Option Shuffling: No

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Correct Marks : 2 Wrong Marks : 1

Which ONE of the following is true about 2-stage branch completion in the MIPS32 5-stage pipeline, compared to 3-stage branch completion?

  1. extra delay slots are required
  2. extra data forwarding paths are required
  3. extra instruction formats are required

    4. --- Content provided by​ FirstRanker.com ---

  4. extra CPU cores are required

Options:

2886077662. 1

2886077663. 2

2886077664. 3

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2886077665. 4

Question Number : 34 Question Id : 2886071919 Question Type : MCQ Option Shuffling: No

Correct Marks : 2 Wrong Marks : 1

ONE of the following is true about a STALL introduced due to a a data hazard, specifically followed by a dependence?

  1. The STALL introduces a nop between the Iw and the add in the pipeline

    2. --- Content provided by‌ FirstRanker.com ---

  2. The STALL introduces a nop before the Iw in the pipeline
  3. The STALL introduces a nop after the add in the pipeline
  4. The STALL introduces two nops: one before and one after the add in the pipeline

Options:

2886077666. 1

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2886077667. 2

2886077668. 3

2886077669. 4

Question Number : 35 Question Id : 2886071920 Question Type : MCQ Option Shuffling : No


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This download link is referred from the post: ARPIT Last 10 Years 2011-2021 Previous Question Papers

This post was last modified on 19 January 2021