Download JNTUK M-Tech 2020 R19 CSE Parallel Computer Architecture Model Question Paper

Download JNTUK (Jawaharlal Nehru Technological University Kakinada (JNTU kakinada)) M.Tech (ME is Master of Engineering) 2020 R19 CSE Parallel Computer Architecture Model Previous Question Paper

20

[M19CST1112]

I M.Tech I Semester (R19) Regular Examinations
PARALLEL COMPUTER ARCHITECTURE
(Computer Science & Engineering)
MODEL QUESTION PAPER
TIME: 3 Hrs. Max. Marks: 75 M
Answer ONE Question from EACH UNIT
All questions carry equal marks
*****

CO KL M
UNIT - I
1. a). Explain abt trends in Integrated Circuits 1 2 7
b). Write abt basic and Intermediate concepts of Pipelining 1 1 8
OR
2. a). Explain abt Quantative Principles f Computer Design 1 2 8
b). Discuss abt Pipeline Hazards 1 2 7
UNIT - II
3. a). Write abt basic compiler techniques for exposing ILP 2 3 8
b). What are the limitations on ILP realizable processors 2 2 7
OR
4. a). With suitable example explain dynamic scheduling algorithm 2 3 7
b). Explain exploiting using dynamic scheduling 2 3 8
UNIT-III
5. a). Explain Vector architecture in detail. 2 3 7
b). Write abt infrastructure and costs of warehse scale computers 2 2 8
OR
6. a). Explain abt the performance of shared memory processors 2 3 7
b). Give the architecture of warehse scale computers 2 2 8
UNIT - IV
7. a). What are basic cache performance techniques . Explain. 2 3 8
b). Write abt virtual memory 2 3 7
OR
8. a). Writhe abt any six advanced optimization techniques of cache performance 2 2 8
b). Explain the design of memory hierarchies 2 2 7
UNIT - V
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20

[M19CST1112]

I M.Tech I Semester (R19) Regular Examinations
PARALLEL COMPUTER ARCHITECTURE
(Computer Science & Engineering)
MODEL QUESTION PAPER
TIME: 3 Hrs. Max. Marks: 75 M
Answer ONE Question from EACH UNIT
All questions carry equal marks
*****

CO KL M
UNIT - I
1. a). Explain abt trends in Integrated Circuits 1 2 7
b). Write abt basic and Intermediate concepts of Pipelining 1 1 8
OR
2. a). Explain abt Quantative Principles f Computer Design 1 2 8
b). Discuss abt Pipeline Hazards 1 2 7
UNIT - II
3. a). Write abt basic compiler techniques for exposing ILP 2 3 8
b). What are the limitations on ILP realizable processors 2 2 7
OR
4. a). With suitable example explain dynamic scheduling algorithm 2 3 7
b). Explain exploiting using dynamic scheduling 2 3 8
UNIT-III
5. a). Explain Vector architecture in detail. 2 3 7
b). Write abt infrastructure and costs of warehse scale computers 2 2 8
OR
6. a). Explain abt the performance of shared memory processors 2 3 7
b). Give the architecture of warehse scale computers 2 2 8
UNIT - IV
7. a). What are basic cache performance techniques . Explain. 2 3 8
b). Write abt virtual memory 2 3 7
OR
8. a). Writhe abt any six advanced optimization techniques of cache performance 2 2 8
b). Explain the design of memory hierarchies 2 2 7
UNIT - V
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9. a). With suitable examples define real faults and failures 2 3 7
b). Write abt SIMICS and INTEL software development tools 2 2 8
OR
10. a). Give the design and evaluation of an I/O system 2 2 7
b). Write abt I/0 performance and reliability measures 2 2 8
























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