Download AKTU B-Tech 3rd Sem 2018-2019 Digital Logic Design Question Paper

Printed Pages: 02

Paper Id: 130301

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Subject Code: REC301

Time: 3 Hours

B TECH

(SEM-111) THEORY EXAMINATION, 2018-19

DIGITAL LOGIC DESIGN

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Max. Marks: 70

Note: Be precise in your answer. In case of numerical problem assume data wherever not provided.

SECTION-A

1. Attempt all of the following questions: (2×7=14)
   1. What is modulus of a counter?
   2. How many flip flops are required to design Mod-5 Ring counter and Mod-5 Johnson counter?

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   3. Determine the value of base x, if: (193)x = (623)8
   4. Write the advantage of Gray code over the straight binary number sequence.
   5. What do you mean by fan-out and fan-in?
   6. Define cyclic codes.
   7. What is race around condition?

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SECTION-B

2. Attempt any three of the following questions: (7×3=21)
   1. Minimize the following Boolean function using K-map. F(A, B, C, D) = S (3,4,5,7,9,13, 14,15)
   2. Minimize the following using Quine- McCluskey method: F(A, B, C, D) = ? (0,1, 9,15, 24, 29, 30) + Sd (8, 11, 31)
   3. Write short notes on priority encoder.

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   4. Implement the following Boolean function: F (?. ?. C. D) = ? (0, 1, 3, 4, 7, 8, 9, 11, 14, 15) using
      1. 4:1 MUX
      2. 2:1 MUX
   5. Design Binary code to Gray code converter.

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SECTION-C

3. Attempt any one of the following questions: (7×1 = 7)
   1. 1. Draw a BCD adder circuit and explain its working.
      2. Convert the SR Flip Flop to JK Flip Flop.
   2. What do you mean by shift register? What is the need of shift register? Draw and explain bidirectional shift register.

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4. Attempt any one of following questions: (7×1 = 7)
   1. 1. Design a modulo-4 UP/DOWN counter using JK flip flop.
      2. Design a ripple decade counter using JK flip flop.
   2. 1. What is critical race and non- critical race? How can they be avoided?

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      2. Describe the hazards in digital circuits. How are these removed? Design a hazards free circuit of the following Boolean function: F (A, B, C) = ?m (1, 2, 3, 5)
5. Attempt any one of following questions: (7×1=7)
   1. 1. Describe the circuit and performance of CMOS inverter and state the characteristics of CMOS.
      2. Differentiate between PLA and PAL. Realize the full adder circuit using PAL.

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   2. 1. Discuss the concept of field programmable gate array (FPGA). Discuss the various structures of FPGA.
      2. Tabulate the truth table for 8×4 ROM that implements the Boolean function:
         ?(x, y, z) = ? (1, 2, 4, 6)
         ? (x, y, z) = ? (0, 1, 6, 7)
         

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         C(x, y, z) = ? (2,6)
         D(x, y, z) = ? (1, 2, 3, 5, 7)
6. Attempt any one of following questions: (7×1=7)
   1. An asynchronous sequential logic circuit is described by the following excitation and output function
      

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      y = X1X2 + (X1 + X2) Y
      Z=y
      1. Draw the logic diagram of the circuit.
      2. Derive the transition table and output map
      3. Describe the behavior of the circuit.

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   2. 1. The code 101101010 is received, correct any errors. There are four parity bits and odd parity is used.
      2. Draw a full subtractor circuit using NAND gate.
7. Attempt any one of following questions: (7×1=7)
   1. Drive the state table and state diagram for the Sequential circuit shown in fig, below:
      

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      (Diagram Description: A circuit diagram with components DA, QA, CP, and IS. Details are difficult to discern from the image.)
   2. Draw the reduced state table and reduced state diagram for the state table given
      (State table description: A state table with states a, b, c, d, e, f and inputs 0, 1. Details are difficult to discern from the image.)

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