Download AKTU B-Tech 5th Sem 2017-2018 NCS505 Computer Architecture Question Paper

Download AKTU (Dr. A.P.J. Abdul Kalam Technical University (AKTU), formerly Uttar Pradesh Technical University (UPTU) B-Tech 5th Semester (Fifth Semester) 2017-2018 NCS505 Computer Architecture Question Paper

Printed pages: 02 Sub Code: NCS 505
PaperID I?ll? Roll W No.
Time:
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B.TECH
(SEM V) THEORY EXAMINATION 2017-18
COMPUTER ARCHITECTURE
3 Hours Total Marks: 100
1. Attempt all Sections. If any missing data is required, then choose suitably.
SECTION A
Attempt all questions in brief. 2 x10 = 20
What is meant by synchronous and asynchronous communication?
Describe magnetic disk?
What is instruction cycle?
Discuss ?oating point number representation.
Explain concept of memory transfer.
What are various types of registers?
Define bus arbitration. What the different types are of bus arbitration do you know?
. What is auxiliary memory? Explain.
What is vertical microprogramming?
How may 128X8RAM chips are needed to provide memory capacity of 2048 bytes?
SECTION B
Attempt any three of the following: 10 x 3 = 30
Explain General Register Organization with the help of suitable diagram.
. What is interrupt? What are the different types of interrupts?
Describe the following organizations of cache memory:
(i). Associative mapping
(ii). Direct Mapping
(iii). Set associative mapping
. A digital computer has a memory unit of 64K X 16 and a cache memory of 1K words.
The cache uses direct mapping with block size of four words.
(i). How many bits are there in tag, index, block and word fiels 0f the address format?
(ii). How many bits are there in each word of cache, and how they are devided into
functions? Include a valid bit.
(iii). How many blocks can the cache accommodate?
Discuss stack organization. Explain the following in details.
(i) Register stack
(ii) Memory stack

SECTION C
Attempt any one part of the following: 10 x 1 = 10
(a) Discuss Booth?s algorithm. Multiply (-7) and (3) using Booth?s algorithm.
(b) Consider a two level memory hierarchy of the form (M1, M2) where M1 is connected directly
to the CPU. Determine the average cost per bit C and average access time ta for the data
given below:
Level(i) Capacity(Si) Cost(Ci) Access time (tai) Hit Ratio(H)
M1 (Cache) 1024 0.1000 10?8 .9000
M2 (Main) 216 0.0100 10*6 -
Attempt any one part of the following: 10 x 1 = 10
(a) Discuss control word with suitable example.
(b) Describe I/O interface.
Attempt any one part of the following: 10 x 1 = 10
(a) What is DMA in computer architecture?
(b) Draw and explain 2D and 2-1/2D RAM chip
Attempt any one part of the following: 10 x 1 = 10
(a) What is Virtual Memory? Why is it necessary to implement Virtual memory?
What is use of page replacement algorithm?
(b) What is difference between 1/0 mapped input/output and memory mapped 1/0?
What are the advantages and disadvantages of each?
Attempt any one part of the following: 10 x 1 = 10
(a) Write a program to evaluate arithmetic expression
X=(A?B)*(((C-D)/F)/G)
Using a general register computer with three, two, one & zero address
instructions.
(b) Describe the following control units
(i). Hardwired control unit
(ii).Micr0pra1nmed control unit