Download JNTUA M.Tech 1st Sem 2016 Feb Reg-Supple 9D06101 Digital System Design Question Paper

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Code: 9D06101

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M.Tech I Semester Regular & Supplementary Examinations February 2016

DIGITAL SYSTEM DESIGN

(Common to DSCE, DECS, ECE, VLSIES, ESVLSI, VLSIESD & MNE)

(For students admitted in 2011, 2012, 2013, 2014 & 2015 only)

Time: 3 hours

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Max Marks: 60

Answer any FIVE questions

All questions carry equal marks

1. (a) Discuss the primary constructs that are used in VHDL.
   (b) Design a 4 X 3 ROM to perform:
   

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   F₁ = ∑(0, 1, 2, 3, 7)
   F₂ = ∑(1, 2, 3, 5, 7)
   F₃ = ∑(0, 2, 4, 6)
2. (a) Draw the symbols used in ASM chart and explain.
   (b) Describe important features of FPGA.

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3. Construct the test set of output function of the circuit F(X₁, X₂, X₃) = X₁X₃ + (X₂ + X₃). Using path sensitizing method.
4. (a) With a neat circuit diagram, describe the working a signature analyzer.
   (b) Write short notes on testing for bridging faults.
5. (a) Explain about fault detection and location in sequential circuits.
   (b) Discuss about synchronizing experiments of fault diagnosis in sequential circuits.

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6. (a) Explain the various types of cross point fault that occur in PLA's.
   (b) Explain PLA folding.
7. (a) Explain how test generation can be achieved in testing a PLA.
   (b) Discuss briefly about testable PLA design.
8. Explain the fundamental mode model for asynchronous sequential machine design.

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