Download JNTUA M.Tech 1st Sem 2018 Aug-Sept 9D06103 Advanced Computer Architecture Question Paper

Download JNTUA (JNTU Anantapur) M.Tech ( Master of Technology) 1st Semester 2018 Aug-Sept 9D06103 Advanced Computer Architecture Previous Question Paper

Code: 9D06103

M.Tech I Semester Supplementary Examinations August/September 2018
ADVANCED COMPUTER ARCHITECTURE
(Common to DSCE, DECS & ES)
(For students admitted in 2013, 2014, 2015 & 2016 only)

Time: 3 hours Max. Marks: 60
Answer any FIVE questions
All questions carry equal marks
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1 (a) What is the impact of time, volume, commodification and packaging in determining cost of
a computer? Explain.
(b) Describe five levels of programs used to evaluate machines.

2 (a) Discuss with examples, the three popular choices for encoding the instruction set.
(b) With the help of diagrams, explain the operand locations for four instruction set
architecture classes.

3 (a) Explain in detail the dynamic scheduling using Tomasulo?s approach.
(b) With the help of flow chart, explain the steps involved in handling an instruction with a
branch-target buffer.

4 (a) Examine the use of compiler technology to improve the performance of pipelines.
(b) What are the four methods that have been investigated for supporting more ambitious
speculation without introducing erroneous exception behavior?

5 (a) Illustrate a multi-level memory hierarchy, including typical sizes and speeds of access.
(b) Suppose that in 1000 memory references there are 40 misses in the first level cache and
20 musses in the second-level cache. What are the various miss rates? Assume the miss
penalty from L2 cache to memory is 100 clock cycles, the hit time of L2 cache is 10 clock
cycles, the hit time of L1 is 1 clock cycles, and there are 1.5 memory references per
instruction. What is the average memory access time and average stall cycles per
instruction? Ignore the impact of writes.

6 (a) Discuss the basic hardware primitives required to implement synchronization in a
multiprocessor.
(b) Draw and explain the finite-state transition diagram for a single cache block using a write-
invalidation protocol and a write-back cache.

7 Describe in detail the following most commonly used storage devices:
(i) Magnetic disks (ii) Magnetic tapes (iii) Flash memory.

8 (a) List and explain the components used to construct the cluster.
(b) Discuss briefly the three interconnection network media.

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