Download JNTUK B-Tech 2020 R19 IT 1202 Digital Logic Design Model Question Paper

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[B19 CS 1202]
I B. Tech II Semester (R19) Regular Examinations
DIGITAL LOGIC DESIGN
(Common to CSE & IT)
MODEL QUESTION PAPER

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TIME: 3 Hrs. Max. Marks: 75 M
Answer ONE Question from EACH UNIT
All questions carry equal marks

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skskeokskok
CO|KL | M

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UNIT -1
1. a). i. Convert (1032.2)4 to decimal. Cl| K2 8
ii. Perform the subtraction using 2’s complement 100-110000
b). Reduce the Boolean Functions to minimum number of literals Cl| K2 7
(1) ABC+AIB 1C+A1BC+ABCI1 +A1B 1C 1 to five literals

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(ii) (A+C+D)(A+C+D1 )(A+C1 +D)(A+B1 ) to fr literals
OR
2. a). Convert the function to another canonical form. F(x,y,z)=n(0,3,6,7) Cl | K2 8
b). Implement the Boolean function F=xy+x1yl+ylz with Cl| K2 7
(1) AND ,OR and NOT gates

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(i1) OR,NOT gates
(ii1)) AND, NOT gates
UNIT -1I
3. a). Simplify the Boolean Function using K-Map. C2| K3 8
F(A,B,C,D)=ACE+A'CD'E+A'C'DE

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D(A,B,C,D)=DE'+A'D'E+AD'E'
b). Design and explain Binary Adder/ Subtractor. C2 | K3 7
OR
4. a). Simplify the Boolean Function to-product of sums. F(A,B,C,D)=n(0,1,2,3,4,10,11) | C2 | K2 8
b). Design and explain Decimal Adder. C2 | K2 7

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UNIT - 111
5. a). Design and explain abt JK Flip flop. C3 | K3 8
b). Explain abt State Reduction and Assignment with example. C3 | K3 7
OR
6. Explain abt design procedure of sequential circuits with an example C3| K4 | 15

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UNIT -1V
7. a). Design and explain abt Shift Register. C4 | K3 8
b). Design and explain abt BCD Ripple cnter . C4 | K3 7
OR
8. a). Design and explain abt Universal Shift Register. C4 | K3 8

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b). Design and explain abt Synchrons Binary cnter. C4 | K3 7
UNIT -V
9. a). Explain abt Memory decoding of RAM. C5 | K3 8
b). Explain abt ROM Variants C5| K3 | 7
OR

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10. a). Explain PLA and PAL C5| K3 | 8
b). Explain abt Hamming code with an example C5| K3 7

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