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Download AKTU B-Tech 6th Sem 2017-2018 NEN 603 Integrated Circuits Question Paper

Download AKTU (Dr. A.P.J. Abdul Kalam Technical University (AKTU), formerly Uttar Pradesh Technical University (UPTU) B-Tech 6th Semester (Sixth Semester) 2017-2018 NEN 603 Integrated Circuits Question Paper

This post was last modified on 29 January 2020

AKTU B-Tech Last 10 Years 2010-2020 Previous Question Papers || Dr. A.P.J. Abdul Kalam Technical University


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Printed pages: 03

Paper Id: 121603

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Sub Code: NEN 603

Roll No:

B TECH

(SEM-VI) THEORY EXAMINATION 2017-18

INTEGRATED CIRCUITS

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Time: 3 Hours Max. Marks: 100

Note: Be precise in your answer. In case of numerical problem assume suitable data wherever not provided.

SECTION A

1. Attempt all parts of the following questions: 2×10=20

  1. (a) Why CMOS NAND is preferred over CMOS NOR?
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  3. (b) What is Capture range in PLL?
  4. (c) What do you understand by hysteresis voltage?
  5. (d) Define current mirror circuit and current steering process.
  6. (e) The basic step of an 8-bit DAC is 40mV. If 00000000 represents 0V, what is represented by the input 11010111?
  7. (f) Draw and explain the generalized impedance converter circuit.
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  9. (g) What is the role of coupling capacitor (Cc) in IC 741 internal circuit?
  10. (h) List the advantages of Wildar current source.
  11. (i) Sketch properly labeled Master Slave D flip flop Circuit.
  12. (j) Design a multiple feedback Narrow Band Pass filter with f=1 KHz, Q=3 and A=10.

SECTION B

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2. Attempt any three parts of the following questions: 3×10=30

  1. (a) Derive the expression of voltage gain in KHN Biquad Filter. Draw the KHN Biquad filter and drive transfer function of the BPF and LPF from that.
  2. (b) Draw and explain the block diagram of IC 555. Design a 555 timer as astable multivibrator giving its block diagram which provides an output signal frequency of 2 KHz and 75 % duty cycle.
  3. (c) Design a wideband pass filter with lower cutoff frequency fL=200 Hz, higher cutoff frequency fH=1 kHz and a passband gain=4?
  4. (d) Find the truth table and CMOS realization of the following gates:
    1. (i) AND-OR-INVERT (AOI), F = AB + CD
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    3. (ii) OR-AND-INVERT (OAI) F = (A + B)(C + D)
  5. (e) Explain the working of PLL with suitable block diagram. Write down the different applications of PLL.

SECTION C

3. Attempt any one part of the following: (10 X 1 = 10)

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  1. (a) Define the slew rate. Also derive the relationship between fT and slew rate for IC 741.
  2. (b) What is a DAC? Explain the weighted resistor DAC with suitable diagram.

4. Attempt any one part of the following: (10 X 1 = 10)

  1. (a) What is log amplifier and what are its applications? Draw and explain its operation.
  2. (b) A combinational circuit has 3 inputs A, B, C and output F is true for following input combinations:
    • A is False, B is True
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    • A is False, C is True
    • A, B, C are False
    • A, B, C are True
    Write truth table and draw CMOS logic circuit for expression obtained for F using NAND gates only. (Use convention False=0 and True=1)

5. Attempt any one part of the following: (10 X 1 = 10)

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  1. (a) Draw the circuit of full wave precision rectifier and find expression for output voltage for positive half cycle of input sinusoidal waveform.
  2. (b) Draw and explain a GILBERT analog multiplier.

6. Attempt any one part of the following: (10 X 1 = 10)

  1. (a) Give CMOS implementation of a clocked SR flip-flop and explain its working.
  2. (b) Draw the circuit diagram for monostable multivibrator with operational amplifier. Explain its operation. Derive the expression for its time period.
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7. Attempt any one part of the following: (10 X 1 = 10)

  1. (a) Draw the output of the following circuit and explain its working.

Figure 1

  1. (b) Design and implement an inverting Schmitt trigger for use as a zero crossing detector with saturation voltages of ± 15V, having hysteresis transition of ± 25mV.

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