Download VTU BE 2020 Jan ECE Question Paper 17 Scheme 5th Sem 17EC53 Verilog HDL

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Fifth Semester B.E. Degree Examination, Dec.2
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Verilog HDL
17EC53
Time: 3 hrs. Max. Marks: 100
Note: Answer FIVE full questions, choosing ONE full question from each module.
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Module-1
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1 a. Explain typical design flow for designing VLSI IC circuit using the flow chart. (08 Marks)
b. Write the verilog code for 4-bit ripple carry counter. (07 Marks)
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4)
to c. What are the advantages of HDLs compared to traditional schematic based design?(05 Marks)
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c -
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2 a. Explain top-down design methodology with example.
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b. What are the two styles of stimulus application? Explain each method in brief (07 Marks)

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c. Mention the features of verilog HDL.
(05 Marks)
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Module-2

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3 a. Explain the following verilog data types with an examples,

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' (i) Nets
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(ii) Registers
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(iii) Integers
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(iv) Parameters
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(v) Arrays (10 Marks)
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... b. Write the verilog description of SR-latch. Also write stimulus code.
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(06 Marks)
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c. How to write comments in verilog HDL, explain with examples. (04 Marks)
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4 a. With neat block diagram, explain the components of verilog module. (08 Marks)
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. b. Explain $display, Smonitor, $finish and $stop system tasks with examples. (08 Marks)
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c. Declare the following variables in verilog:
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( i) An 8-bit vector net called a_in.
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(ii) An integer called count.
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(iv) A parameter cache_size equal to 512. (04 Marks)
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c.,
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c Module-3
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5 a. Write a verilog data flow description for 4-bit full adder with carry lookahead logic.
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(08 Marks)
o b. What are rise, fall and turn-off delays? How they are specified in verilog?
z
(06 Marks)
c. What would be the output of the following a = 4'1)0111, b = 4'b1001

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(i) &b (ii) a <2 (iii) {a, bl (iv) { 2{b}} (v) a
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(vi) a I b (06 Marks)
1 of 2
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Fifth Semester B.E. Degree Examination, Dec.2
-
01414aff.2020
Verilog HDL
17EC53

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Time: 3 hrs. Max. Marks: 100
Note: Answer FIVE full questions, choosing ONE full question from each module.
74
. "'
Module-1

--- Content provided by​ FirstRanker.com ---

c
.
;
?
1 a. Explain typical design flow for designing VLSI IC circuit using the flow chart. (08 Marks)

--- Content provided by‌ FirstRanker.com ---

b. Write the verilog code for 4-bit ripple carry counter. (07 Marks)
,..
. ?
4)
to c. What are the advantages of HDLs compared to traditional schematic based design?(05 Marks)

--- Content provided by‌ FirstRanker.com ---

c5. =
? ?5
, --
c -
,--, OR

--- Content provided by FirstRanker.com ---

2 a. Explain top-down design methodology with example.
E -
?
'4
gy (08 Marks)

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= ?
? ?t-
b. What are the two styles of stimulus application? Explain each method in brief (07 Marks)
c. Mention the features of verilog HDL.
(05 Marks)

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,
?
F
= .:. -!
O

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c.
:..
Module-2
. .
''

--- Content provided by‍ FirstRanker.com ---

,,,
=
3 a. Explain the following verilog data types with an examples,
0
' (i) Nets

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i-

?
-
u 0

--- Content provided by FirstRanker.com ---

(ii) Registers
Tt
.
8
?

--- Content provided by⁠ FirstRanker.com ---

(iii) Integers
? "CI
eA c
(iv) Parameters
et et

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-a .5
(v) Arrays (10 Marks)
;'.
... b. Write the verilog description of SR-latch. Also write stimulus code.
-0 ct

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(06 Marks)
? _.?
4)
>, >
c. How to write comments in verilog HDL, explain with examples. (04 Marks)

--- Content provided by​ FirstRanker.com ---

r-
-
0
? a.,
C. 0.

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OR
?_,
0 ^
4 a. With neat block diagram, explain the components of verilog module. (08 Marks)
o cti

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. b. Explain $display, Smonitor, $finish and $stop system tasks with examples. (08 Marks)
3 o
c. Declare the following variables in verilog:
0

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( i) An 8-bit vector net called a_in.
_,. -
0

?.,--

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(ii) An integer called count.
to
O to (iii) A memory MEM containing 256 words of 64 bits each.
.0: c
0.. 8

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(iv) A parameter cache_size equal to 512. (04 Marks)
P >
O v.,
c.,
o

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>,
=
<
c Module-3
._, r.;

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5 a. Write a verilog data flow description for 4-bit full adder with carry lookahead logic.
?
4)
(08 Marks)
o b. What are rise, fall and turn-off delays? How they are specified in verilog?

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z
(06 Marks)
c. What would be the output of the following a = 4'1)0111, b = 4'b1001
,T
E

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0
a
<<<2
0..
(i) &b (ii) a <2 (iii) {a, bl (iv) { 2{b}} (v) a

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A
b
?
(vi) a I b (06 Marks)
1 of 2

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17EC5:.
OR
6 a. Write the verilog code for 4-to-1 multiplexer using,
(i) Conditional operator (ii) Logic equation. (06 Marks)
b. Discuss And, Or and Not gates with respect to logic symbols, gate instantiation and truth

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tables. (08 Marks)
c. Explain assignment delay, implicit assignment delay and net declaration delay for
continuous assignment statements. (06 Marks)
Module-4
7 a. Explain the blocking assignment statements and non blocking assignment statements with

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relevant examples. (08 Marks)
b. Write a verilog behavioural description of 8 : 1 multiplexer using case statement. (06 Marks)
c. Explain Event based timing control with example. (06 Marks)
OR
8 a. Discuss sequential and parallel blocks with examples. (08 Marks)"

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b. Write the verilog behavioural description of 4-bit binary counter. (06 Marks)
c. Illustrate the use of while loop and repeat loop with suitable examples. (06 Marks)
Module-5
9 a. Explain synthesis process with neat block diagram. (08 Marks)
b. Write the structural description of 4-bit equality comparator. (06 Marks)

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c. Explain the following with general syntax and examples (i) Entity (ii) Architecture.
(06 Marks)
OR
10 a. Discuss the capabilities of VHDL. (06 Marks)
b. Write the VHDL code for two 4-bit comparator using data flow description and when-else

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statement. (08 Marks)
c. Explain the declaration of constants, variables and signals in VHDL with examples.
(06 Marks)
2 of 2
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