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GUJARAT TECHNOLOGICAL UNIVERSITY
BE - SEMESTER- IV EXAMINATION — SUMMER 2020
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Subject Code: 2140707 Date: 28/10/2020
Subject Name: COMPUTER ORGANIZATION
Time: 10:30 AM TO 01:00 PM Total Marks: 70
Instructions:
- Attempt all questions.
- Make suitable assumptions wherever necessary.
- Figures to the right indicate full marks.
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MARKS
Q.1 (a) Enlist the major components of CPU and explain each in brief. 03
(b) Briefly discuss 4-bit binary adder. 04
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(c) Draw and explain flowchart for instruction cycle. 07
Q.2 (a) Discuss three-state bus buffers in brief. 03
(b) Write the name of basic computer registers with their functionalities. 04
(c) Enlist various addressing modes and explain the same in brief with proper example(s). 07
OR
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(c) Write a note on arithmetic pipeline. 07
Q.3 (a) Draw a space-time diagram for a six-segment pipeline to process seven tasks. 03
(b) Write microoperations needed to execute the following instructions: 04
- ADD
- LDA
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(c) Write three address and one address instructions program for the following arithmetic expression. 07
Z=(A+B)*(C-D/E)+F/G
OR
Q.3 (a) Explain any one pipeline conflicts. 03
(b) Draw the flowchart for first pass of assembler. 04
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(c) Explain Booth algorithm. Support your answer by taking small example. 07
Q.4 (a) What do you mean by pseudoinstruction? Give any three examples of pseudoinstructions. 03
(b) State differences between hardwired control organization and microprogrammed control organization. 04
(c) Write a brief note on peripheral devices. 07
OR
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Q.4 (a) Write assembly language program to add two numbers. 03
(b) Discuss microprogrammed control organization in brief with neat diagram. 04
(c) Explain associative memory in detail. 07
Q.5 (a) Write the difference(s) between arithmetic shift left and logical shift left instruction. Support your answer with small example. 03
(b) Show the step-by-step multiplication process using Booth algorithm when multiplicand is +23 and multiplier is +19. Assume 5-bit signed magnitude number format. (Write necessary assumptions if required) 04
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A=+7 and B=+3
(c) Discuss any two mapping procedures when considering the organization of cache memory. 07
OR
Q.5 (a) Write a brief note on memory hierarchy. 03
(b) Explain Input-Output Processor in brief. 04
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(c) Elaborate cache coherence problem. 07
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