Download GTU B.Tech 2020 Winter 5th Sem 3151105 Vlsi Design Question Paper

Download GTU (Gujarat Technological University Ahmedabad) B.Tech/BE (Bachelor of Technology/ Bachelor of Engineering) 2020 Winter 5th Sem 3151105 Vlsi Design Previous Question Paper

Seat No.: ________
Enrolment No.___________
GUJARAT TECHNOLOGICAL UNIVERSITY
BE- SEMESTER?V (NEW) EXAMINATION ? WINTER 2020
Subject Code:3151105 Date:03/02/2021
Subject Name:VLSI Design
Time:10:30 AM TO 12:30 PM Total Marks: 56
Instructions:
1. Attempt any FOUR questions out of EIGHT questions.

2. Make suitable assumptions wherever necessary.

3. Figures to the right indicate full marks.



MARKS
Q.1 (a) Draw CMOS inverter circuit and cross section view of
03
nMOSFET.

(b) Draw voltage transfer characteristics of inverter and define
04
VIL, VIH, VOL, VOH, NML and NMH.

(c) Derive threshold voltage equation and explain what is
07
substrate bias effect.


Q.2 (a) Realize following Boolean logic equation using CMOS
03
inverter. Z= (AB+C(D+E))'

(b) Compare Static and Dynamic logic circuit.
04

(c) Derive
drain
current
using
gradual
channel
07
approximation.
Q.3 (a) Draw VTC of CMOS inverter and find operating region
03
of NMOS and PMOS at different input voltage ranges
from 0 to Vdd.

(b) Derive Critical voltages VIL and VIH of CMOS inverter
04

(c) Consider a CMOS inverter with the following
07
parameters: VTon = 0.6 V, VTop = - 0.7 V ,Kn' = 50
uA/V2, Kp' = 16 uA/V2, (W/L)n = 4, (W/L)p = 5
Calculate the noise margins of this circuit. The power
supply voltage is VDD = 3.3 V.




Q.4 (a) Draw resistive load inverter circuit and its VTC curve.
03

(b) Derive critical voltages VOH, VOL, VIL and VIH of
04
resistive load inverter.

(c) Design resistive load inverter with following parameters:
07
VTon = 0.8 V, Kn' = 20 uA/V2, (W/L)n = 2, RL= 200
kohm and Vdd=5V. Calculate the noise margins of this
circuit.
Q.5 (a) Draw transistor level circuit diagram of NOR based SR
03
latch using CMOS.

(b) Derive switching power dissipation equation of CMOS
04
inverter with idea step input.

(c) Justify importance of transmission gate. Realize
07
following functions using TG.
i) F=AB+A'C'+AB'C and
ii) F=AB' + A'B



Q.6 (a) What is need of domino CMOS logic circuit and draw
03
it's circuit diagram.
1

---

(b) Explain Ring oscillator
04

(c) Draw i/p and o/p waveform during high to low transition
07
of o/p for CMOS inverter and derive expression for PHL.
using differential equation method.
Q.7 (a) Draw CMOS implementation of D latch with two
03
inverters and two CMOS TG gates.

(b) Compare CPLD and FPGA.
04

(c) Draw and Explain different clock generator and
07
distributor circuits



Q.8 (a) Compare FinFET and Planner MOSFET
03
(b) Compare constant voltage and constant filed scaling.
04
(c) What is need of Design of Testability (DFT) in VLSI IC
07
design and explain Built in Self Test (BIST) techniques
of DFT.
*************
2

---