Download GTU B.Tech 2020 Winter 6th Sem 2161101 Vlsi Technology And Design Question Paper

Download GTU (Gujarat Technological University Ahmedabad) B.Tech/BE (Bachelor of Technology/ Bachelor of Engineering) 2020 Winter 6th Sem 2161101 Vlsi Technology And Design Previous Question Paper

Seat No.: ________
Enrolment No.___________
GUJARAT TECHNOLOGICAL UNIVERSITY
BE- SEMESTER?VI (NEW) EXAMINATION ? WINTER 2020
Subject Code:2161101 Date:29/01/2021
Subject Name:VLSI Technology & Design
Time:02:00 PM TO 04:00 PM Total Marks: 56
Instructions:
1. Attempt any FOUR questions out of EIGHT questions.

2. Make suitable assumptions wherever necessary.

3. Figures to the right indicate full marks.


MARKS
Q.1 (a) Compare Semi-custom and Full custom VLSI design style
03

(b) Draw voltage transfer characteristics of inverter and define VIL, VIH, VOL,
04
VOH, NML and NMH.

(c) Explain the VLSI design flow.
07


Q.2 (a) Write advantages and disadvantages of dynamic logic circuit.
03

(b) Realize following Boolean logic equation using CMOS inverter.
04
Z= (AB+C(D+E))'

(c) Derive the drain current equation for MOSFET using Gradual
07
Channel Approximation (GCA).




Q.3 (a) Which are the four general criteria to measure design quality of a
03
fabricated integrated circuit (chip)?

(b) Draw resistive load inverter. Derive VIL and VIH critical voltage equation
04
of resistive load inverter.

(c) Design a resistive-load inverter with R = 1 k, such that VOL = 0.6 V.
07
The enhancement-type nMOS driver transistor has the following
parameters VDD = 5 .0 V VTO= 1. V nCox = 22.0 ?A/V2 (a) Determine
the required aspect ratio, W/L. (b) Determine VIL and VIH. (c) Determine
noise margins NML and NMH.




Q.4 (a) Write advantage and disadvantage of both the enhancement load inverter
03
configuration.

(b) Draw CMOS inverter with lead name of pMOS and nMOS. Derive VIL
04
critical Voltage equation of CMOS inverter.

(c) Consider a CMOS inverter circuit with the following parameters: VDD
07
=3.3V, VTON =0.6 V, VTOP= -0.7 V, kn = 200 ?A/V2, kp = 80 A/V2 , find
the NML.



Q.5 (a) What is the need of Scaling? Mention the merits and demerits of constant
03
voltage scaling.

(b) Draw tristate input circuit using Transmission Gate and CMOS inverter
04
and also write its truth table.

(c) Draw circuit for CMOS two input NOR gate. Derive VTH of the same.
07





Q.6 (a) Draw CMOS implementation of D latch with two inverters and two
03
CMOS TG gates.
1

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(b) Implement following Boolean logic equation using Transmission Gate
04
(TG).
Y = AB+ A'C'+AB'C

(c) What is the need for voltage bootstrapping? Explain dynamic voltage
07
bootstrapping circuit with necessary mathematical analysis.



Q.7 (a) Draw general structure of scan based design.
03

(b) Give comparison between FPGA and CPLD.
04

(c) Write a short note on CMOS Transmission gate.
07



Q.8 (a) Define and discuss Latch-up problem in CMOS inverter.
03
(b) Find a equivalent CMOS inverter circuit for simultaneous switching of
04
all inputs, assume that (W/L)p = 15 for all pMOS transistors and (W/L)n
= 10 for all nMOS transistors for the following Boolean equation
F =[(C+D+E) . (B+A)]'
(c) Discuss the on-chip clock generation and distribution.
07

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