Subject Code:2161101
GUJARAT TECHNOLOGICAL UNIVERSITY
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BE- SEMESTER-VI (NEW) EXAMINATION - WINTER 2020
Subject Name:VLSI Technology & Design
Time:02:00 PM TO 04:00 PM
Instructions:
- Attempt any FOUR questions out of EIGHT questions.
- Make suitable assumptions wherever necessary.
- Figures to the right indicate full marks.
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Q1 (a) Compare Semi-custom and Full custom VLSI design style MARKS 03
(b) Draw voltage transfer characteristics of inverter and define Vir, Vi, Vor, Von, NML and NMH. MARKS 04
(c) Explain the VLSI design flow. MARKS 07
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Q2 (a) Write advantages and disadvantages of dynamic logic circuit. MARKS 03
(b) Realize following Boolean logic equation using CMOS inverter. 7= (AB+C(D+E))’ MARKS 04
(c) Derive the drain current equation for MOSFET using Gradual Channel Approximation (GCA). MARKS 07
Q3 (a) Which are the four general criteria to measure design quality of a fabricated integrated circuit (chip)? MARKS 03
(b) Draw resistive load inverter. Derive Vi and Vil critical voltage equation of resistive load inverter. MARKS 04
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(c) Design a resistive-load inverter with R = 1 kO, such that VoL = 0.6 V. The enhancement-type nMOS driver transistor has the following parameters VDD =5 .0 V Vt= 1.V unCox = 22.0 µA/V² (a) Determine the required aspect ratio, W/L:(b) Determine V1 and V. (c) Determine noise margins NMl and NMh: MARKS 07
Q4 (a) Write advantage and disadvantage of both the enhancement load inverter configuration. MARKS 03
(b) Draw CMOS inverter with lead name of pMOS and nMOS. Derive Vi, critical Voltage equation of CMOS inverter. MARKS 04
(c) Consider a CMOS inverter circuit with the following parameters: VDD =3.3V, Vtp =0.6 V, Vtn=-0.7 V, kn = 200 µA/V², kp = 80 µA/ V², find the NMH. MARKS 07
Q5 (a) What is the need of Scaling? Mention the merits and demerits of constant voltage scaling. MARKS 03
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(b) Draw tristate input circuit using Transmission Gate and CMOS inverter and also write its truth table. MARKS 04
(c) Draw circuit for CMOS two input NOR gate. Derive Vth of the same. MARKS 07
Q6 (a) Draw CMOS implementation of D latch with two inverters and two CMOS TG gates. MARKS 03
(b) Y = AB+ A’C’+AB’C MARKS 04
(c) What is the need for voltage bootstrapping? Explain dynamic voltage bootstrapping circuit with necessary mathematical analysis. MARKS 07
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Q.7 (a) Draw general structure of scan based design. MARKS 03
(b) Give comparison between FPGA and CPLD. MARKS 04
(c) Write a short note on CMOS Transmission gate. MARKS 07
Q.8 (a) Define and discuss Latch-up problem in CMOS inverter. MARKS 03
(b) Find a equivalent CMOS inverter circuit for simultaneous switching of all inputs, assume that (W/L)p = 15 for all pMOS transistors and (W/L)n =10 for all nMOS transistors for the following Boolean equation F =[(C+D+E) . (B+A)]’ MARKS 04
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(c) Discuss the on-chip clock generation and distribution. MARKS 07
Date:29/01/2021
Total Marks: 56
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