PTU B.Tech ECE 6th Semester May 2019 71124 VLSI DESIGN Question Papers

Roll No.

Total No. of Pages : 02

Total No. of Questions : 09

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B.Tech.(ECE)/(ETE) (2011 Onwards) (Sem.-6)

VLSI DESIGN

Subject Code : BTEC-604

M.Code: 71124

Time: 3 Hrs.

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Max. Marks : 60

INSTRUCTION TO CANDIDATES :

1. SECTION-A is COMPULSORY consisting of TEN questions carrying TWO marks each.
2. SECTION-B contains FIVE questions carrying FIVE marks each and students have to attempt any FOUR questions.
3. SECTION-C contains THREE questions carrying TEN marks each and students have to attempt any TWO questions.

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SECTION-A

1. Answer briefly :

1. With one example each differentiate between STD_LOGIC and STD_ULOGIC.
2. Perform the following using sra and sll shift operators : (i) 10100101 (ii) 01011010
3. Explain subtype for any data type with an example.

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4. Define pull-up and pull-down ratios of NMOS.
5. Explain scalar data type in VHDL with an example.
6. Describe the significance of process statement.
7. What is propagation delay?
8. Differentiate between Arrays and Records in VHDL.

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9. Discuss the wiring capacitances.
10. What is meant by body effect?

SECTION-B

2. Explain various data objects in VHDL language each with two examples.
3. What is the significance of process statement in VHDL? Explain with an example.

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4. Write a VHDL code for full adder using behavioural modelling style.
5. Does the inverter with a lower VOL always have the shorter high-to-low switching time? Justify your answer.
6. Describe in detail twin tub CMOS process of fabrication.

SECTION-C

7. Design 8×1 MUX using two 4:1 MUX and one 2:1 MUX along with its diagram.

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8. Implement 8×1 multiplexer in VHDL using structural modelling style.
9. Consider a CMOS inverter circuit with the following parameters : VDD = 3.3V, V_TOn = 0.6V, V_TOp = -0.7V, k_n = 200µA/V², k_p = 80µA/V². Calculate the noise margins of the circuit. Notice that the CMOS inverter being considered here has k_r = 2.5 and V_TOn ? |V_TOp| hence it is not a symmetric inverter.

Discuss about the effects of scaling down the dimensions of MOS circuits and systems.

NOTE : Disclosure of Identity by writing Mobile No. or Making of passing request on any page of Answer Sheet will lead to UMC against the Student.

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