Download JNTUA B.Tech 4-2 R13 2018 April 13A04804 RF Integrated Circuits Question Paper

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Code: 13A04804

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B.Tech IV Year II Semester (R13) Regular & Supplementary Examinations April 2018

Time: 3 hours

RF INTEGRATED CIRCUITS

(Electronics and Communication Engineering)

Max. Marks: 70

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PART - A

(Compulsory Question)

Answer the following: (10 X 02 = 20 Marks)

1. (a) State the maximum power transfer theorem and its conditions.
2. (b) What are the conditions for resonance in series RLC networks?

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3. (c) Define gain and bandwidth.
4. (d) What is reflection coefficient?
5. (e) What is thermal noise?
6. (f) Define phase locked loop.
7. (g) What is power match and noise match.

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8. (h) Define phase detector.
9. (i) What is meant by integer-N synthesis?
10. (j) Define frequency synthesis.

PART - B

(Answer all five units, 5 X 10 = 50 Marks)

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UNIT - I

2. (a) Design and convert series to parallel RL & RC network transformations.
   (b) Explain about passive IC components interconnects in RF System.
   OR

3. (a) Compare Pi match and T-match of a network system.
   

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   (b) Discuss about the basic architecture of a RF system.

UNIT - II

4. Prove that a long channel MOS device transconductance depends only on the square root of bias current.

5. (a) Draw and explain about the tuned amplifier.
   (b) Explain about the high frequency amplifier design.
   

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   OR

UNIT - III

6. (a) Explain about intrinsic MOS noise parameters.
   (b) Explain about power match versus noise match.
   OR

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7. Design any two examples of multiplier based mixers.

UNIT - IV

8. (a) Discuss about class D, E, F amplifier in detail.
   (b) Explain about phase locked loops and phase detectors.
   OR

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9. Write short notes on:
   (a) Negative resistance oscillators.
   (b) Linearlized PLL models.

UNIT - V

10. (a) Explain about frequency synthesis in detail.
    

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    (b) Discuss about phase noise and fractional frequency in frequency synthesis.
    OR

11. Write short notes on:
    (a) GSM radio architecture.
    (b) CDMA radio architecture.

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