Total No. of Pages : 02
Total No. of Questions : 18
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B.Tech. (ECE) (2018 Batch) (Sem.-3)
DIGITAL SYSTEM DESIGN
Subject Code : BTEC-302-18
M.Code : 76445
Time : 3 Hrs. Max. Marks : 60
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INSTRUCTIONS TO CANDIDATES :
- SECTION-A is COMPULSORY consisting of TEN questions carrying TWO marks each.
- SECTION-B contains FIVE questions carrying FIVE marks each and students have to attempt any FOUR questions.
- SECTION-C contains THREE questions carrying TEN marks each and students have to attempt any TWO questions.
SECTION-A
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Write briefly :
- Define the term Entity.
- What is an Array?
- What is Combinational Circuits?
- List out the elements present in the ASM chart.
- Write down the features of EPGA.
- Write the Verilog code for half adder using gate level modelling.
- “PAL has reprogrammable AND array, whereas GAL has programmable AND array”. Comment.
- Define Speed Power Product. What is its significance?
- Define fan-in, fan-out.
- What is race around condition?
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SECTION-B
- Design and summarize the internal 3 sections of LS-TTL NAND gate and analyze the circuit with the help of function table.
- Design 1-bit comparator using 2-4 decoder giving three output G, E and L.
- Applying a 4-bit shift register, design a 4-bit twisted ring counter.
- Explain various data types available in VHDL.
- Implement a T-FF with active low asynchronous inputs and clock inputs in VHDL.
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SECTION-C
- Design a serial adder Moore type FSM.
- List out the steps to be consider for PLA folding algorithm.
- How a sequential circuit can be designed using FPGA?
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NOTE : Disclosure of Identity by writing Mobile No. or Making of passing request on any page of Answer Sheet will lead to UMC against the Student.
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This download link is referred from the post: PTU B.Tech Question Papers 2020 December (All Branches)