1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
?
--- Content provided by FirstRanker.com ---
DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
III SEMESTER - R 2017CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________Register No : _______________________________________
Section : _______________________________________
--- Content provided by FirstRanker.com ---
LABORATORY MANUAL
FirstRanker.com - FirstRanker's Choice
--- Content provided by FirstRanker.com ---
1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
?
--- Content provided by FirstRanker.com ---
DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
--- Content provided by FirstRanker.com ---
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
Name : _______________________________________
--- Content provided by FirstRanker.com ---
Register No : _______________________________________Section : _______________________________________
--- Content provided by FirstRanker.com ---
LABORATORY MANUAL
--- Content provided by FirstRanker.com ---
2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
training.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
--- Content provided by FirstRanker.com ---
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
--- Content provided by FirstRanker.com ---
heart and soulDEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and ElectronicsEngineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
--- Content provided by FirstRanker.com ---
professional ethical code.? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
--- Content provided by FirstRanker.com ---
VISION
MISSION
--- Content provided by FirstRanker.com ---
VISIONMISSION
FirstRanker.com - FirstRanker's Choice
--- Content provided by FirstRanker.com ---
1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
?
--- Content provided by FirstRanker.com ---
DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
III SEMESTER - R 2017CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________Register No : _______________________________________
Section : _______________________________________
--- Content provided by FirstRanker.com ---
LABORATORY MANUAL
--- Content provided by FirstRanker.com ---
2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
--- Content provided by FirstRanker.com ---
training.--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
--- Content provided by FirstRanker.com ---
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag onheart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
--- Content provided by FirstRanker.com ---
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering toprofessional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
--- Content provided by FirstRanker.com ---
VISION
MISSION
--- Content provided by FirstRanker.com ---
VISION
MISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
--- Content provided by FirstRanker.com ---
1. FundamentalsTo provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
2. Core Competence
--- Content provided by FirstRanker.com ---
To train the students to meet the needs of core industry with an attitude of learning newtechnologies.
3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
--- Content provided by FirstRanker.com ---
enable them to find solutions to problems in industry and research that contributes to the overalldevelopment of society.
4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
--- Content provided by FirstRanker.com ---
team and stand as a good decision maker to manage any constraint environment with goodprofessional ethics at all strategies.
5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
--- Content provided by FirstRanker.com ---
commitment and lifelong learning needed for successful professional career.--- Content provided by FirstRanker.com ---
FirstRanker.com - FirstRanker's Choice1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
?
--- Content provided by FirstRanker.com ---
DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
III SEMESTER - R 2017
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
Section : _______________________________________
--- Content provided by FirstRanker.com ---
LABORATORY MANUAL
--- Content provided by FirstRanker.com ---
2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
--- Content provided by FirstRanker.com ---
enterprising professionals conforming to global standards through value based quality education andtraining.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
--- Content provided by FirstRanker.com ---
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
--- Content provided by FirstRanker.com ---
needs.? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
--- Content provided by FirstRanker.com ---
industry by continuous assessment and training.VISION
--- Content provided by FirstRanker.com ---
MISSIONVISION
MISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
--- Content provided by FirstRanker.com ---
1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
--- Content provided by FirstRanker.com ---
2. Core CompetenceTo train the students to meet the needs of core industry with an attitude of learning new
technologies.
3. Breadth
--- Content provided by FirstRanker.com ---
To provide relevant training and experience to bridge the gap between theory and practice whichenable them to find solutions to problems in industry and research that contributes to the overall
development of society.
4. Professionalism
--- Content provided by FirstRanker.com ---
To inculcate professional and effective communication skills to the students to make them lead ateam and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
5. Lifelong Learning/Ethics
--- Content provided by FirstRanker.com ---
To practice ethical and professional responsibilities in the organization and society withcommitment and lifelong learning needed for successful professional career.
--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM OUTCOMES (POs)
--- Content provided by FirstRanker.com ---
a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
--- Content provided by FirstRanker.com ---
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment toanalyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
--- Content provided by FirstRanker.com ---
will be aware of contemporary issues.j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
FirstRanker.com - FirstRanker's Choice
--- Content provided by FirstRanker.com ---
1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
?
--- Content provided by FirstRanker.com ---
DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
--- Content provided by FirstRanker.com ---
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
Name : _______________________________________
--- Content provided by FirstRanker.com ---
Register No : _______________________________________Section : _______________________________________
--- Content provided by FirstRanker.com ---
LABORATORY MANUAL
--- Content provided by FirstRanker.com ---
2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
training.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
--- Content provided by FirstRanker.com ---
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
--- Content provided by FirstRanker.com ---
heart and soulDEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and ElectronicsEngineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
--- Content provided by FirstRanker.com ---
professional ethical code.? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
--- Content provided by FirstRanker.com ---
VISION
MISSION
--- Content provided by FirstRanker.com ---
VISIONMISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
1. Fundamentals
--- Content provided by FirstRanker.com ---
To provide students with a solid foundation in mathematics, science and fundamentals ofengineering enabling them to solve complex problems in order to develop real time applications.
2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
--- Content provided by FirstRanker.com ---
technologies.3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
--- Content provided by FirstRanker.com ---
development of society.4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
--- Content provided by FirstRanker.com ---
professional ethics at all strategies.5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM OUTCOMES (POs)a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
--- Content provided by FirstRanker.com ---
c. Graduates will be able to design and conduct experiments, analyze and interpret data.d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
--- Content provided by FirstRanker.com ---
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
--- Content provided by FirstRanker.com ---
k. Graduate who can participate and succeed in competitive examinations.--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
SYLLABUS
Objectives:
--- Content provided by FirstRanker.com ---
The student should be made to:? Understand the various logic gates.
? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
--- Content provided by FirstRanker.com ---
? Learn to use HDLList of experiments:
1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
--- Content provided by FirstRanker.com ---
3. Design and implementation of combinational circuits using MSI devices:a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
c. Magnitude Comparator
d. Application using multiplexers
--- Content provided by FirstRanker.com ---
4. Design and implementation of sequential circuits:a. Shift ?registers
b. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
--- Content provided by FirstRanker.com ---
Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
--- Content provided by FirstRanker.com ---
? Design the different functional units in a digital computer system.? Design and Implement a simple digital system.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORYFirstRanker.com - FirstRanker's Choice
--- Content provided by FirstRanker.com ---
1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
?DEPARTMENT OF
--- Content provided by FirstRanker.com ---
COMPUTER SCIENCE ENGINEERINGIII SEMESTER - R 2017
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
Section : _______________________________________
--- Content provided by FirstRanker.com ---
LABORATORY MANUAL
--- Content provided by FirstRanker.com ---
2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious andenterprising professionals conforming to global standards through value based quality education and
training.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
--- Content provided by FirstRanker.com ---
levels? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
--- Content provided by FirstRanker.com ---
Electrical and Electronics Engineers.--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?sneeds.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
--- Content provided by FirstRanker.com ---
concepts with strongly supported laboratory and prepare them to meet the global needs of theindustry by continuous assessment and training.
VISION
--- Content provided by FirstRanker.com ---
MISSION
VISION
--- Content provided by FirstRanker.com ---
MISSION--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
--- Content provided by FirstRanker.com ---
1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
--- Content provided by FirstRanker.com ---
2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
technologies.
--- Content provided by FirstRanker.com ---
3. BreadthTo provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
development of society.
--- Content provided by FirstRanker.com ---
4. ProfessionalismTo inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
--- Content provided by FirstRanker.com ---
5. Lifelong Learning/EthicsTo practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PROGRAM OUTCOMES (POs)
--- Content provided by FirstRanker.com ---
a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
--- Content provided by FirstRanker.com ---
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
--- Content provided by FirstRanker.com ---
i. Graduates will show the understanding of impact of engineering solutions on the society and alsowill be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
SYLLABUSObjectives:
The student should be made to:
? Understand the various logic gates.
--- Content provided by FirstRanker.com ---
? Be familiar with various combinational circuits.? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
? Learn to use HDL
List of experiments:
--- Content provided by FirstRanker.com ---
1. Verification of Boolean Theorems using basic gates.2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
--- Content provided by FirstRanker.com ---
b. Parity generator / checkerc. Magnitude Comparator
d. Application using multiplexers
4. Design and implementation of sequential circuits:
a. Shift ?registers
--- Content provided by FirstRanker.com ---
b. Synchronous and asynchronous counters5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
Course Outcomes:
--- Content provided by FirstRanker.com ---
? Use Boolean simplification techniques to design a combinational hardware circuit.? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
ContentSl.No. Name of the Experiment Page No.
1.
Verification of Boolean Theorems using Digital Logic Gates
--- Content provided by FirstRanker.com ---
2.Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
3.
--- Content provided by FirstRanker.com ---
Implementation of half adder and full adder4.
Implementation of half subtractor and full subtractor
5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
--- Content provided by FirstRanker.com ---
MSI Devices6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
--- Content provided by FirstRanker.com ---
7.
Design and Implementation of Magnitude Comparator.
8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
--- Content provided by FirstRanker.com ---
9.Design and Implementation of Shift Registers.
10.
Design and Implementation of Synchronous and Asynchronous Counters.
11.
--- Content provided by FirstRanker.com ---
Simulation of Combinational Circuits using Hardware Description Language (VHDL / VerilogHDL Software Required).
12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
--- Content provided by FirstRanker.com ---
FirstRanker.com - FirstRanker's Choice
--- Content provided by FirstRanker.com ---
1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
?
--- Content provided by FirstRanker.com ---
DEPARTMENT OFCOMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
--- Content provided by FirstRanker.com ---
CS8382 DIGITAL SYSTEMS LABORATORY--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
--- Content provided by FirstRanker.com ---
Section : _______________________________________--- Content provided by FirstRanker.com ---
LABORATORY MANUAL2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
training.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
--- Content provided by FirstRanker.com ---
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at differentlevels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
--- Content provided by FirstRanker.com ---
Engineering and thereby produce extremely well trained employable, socially responsible and innovativeElectrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
--- Content provided by FirstRanker.com ---
? To provide highest quality learning environment for the students emphasizing fundamentalconcepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
--- Content provided by FirstRanker.com ---
VISIONMISSION
VISION
--- Content provided by FirstRanker.com ---
MISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
--- Content provided by FirstRanker.com ---
engineering enabling them to solve complex problems in order to develop real time applications.2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
technologies.
--- Content provided by FirstRanker.com ---
3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
development of society.
--- Content provided by FirstRanker.com ---
4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
--- Content provided by FirstRanker.com ---
5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PROGRAM OUTCOMES (POs)
--- Content provided by FirstRanker.com ---
a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
--- Content provided by FirstRanker.com ---
d. Graduates will be able to design a system, component or process as per needs and specifications.e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
--- Content provided by FirstRanker.com ---
h. Graduates will be able to communicate effectively by both verbal and written form.i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
SYLLABUS
Objectives:
The student should be made to:
--- Content provided by FirstRanker.com ---
? Understand the various logic gates.? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
? Learn to use HDL
--- Content provided by FirstRanker.com ---
List of experiments:1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
--- Content provided by FirstRanker.com ---
a. 4 ? bit binary adder / subtractorb. Parity generator / checker
c. Magnitude Comparator
d. Application using multiplexers
4. Design and implementation of sequential circuits:
--- Content provided by FirstRanker.com ---
a. Shift ?registersb. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
--- Content provided by FirstRanker.com ---
Course Outcomes:? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
--- Content provided by FirstRanker.com ---
? Design and Implement a simple digital system.--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Content
Sl.No. Name of the Experiment Page No.
1.
--- Content provided by FirstRanker.com ---
Verification of Boolean Theorems using Digital Logic Gates2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
--- Content provided by FirstRanker.com ---
3.Implementation of half adder and full adder
4.
Implementation of half subtractor and full subtractor
5.
--- Content provided by FirstRanker.com ---
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates andMSI Devices
6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
--- Content provided by FirstRanker.com ---
Devices7.
Design and Implementation of Magnitude Comparator.
8.
--- Content provided by FirstRanker.com ---
Design and Implementation of Application using Multiplexers / Demultiplexers.9.
Design and Implementation of Shift Registers.
10.
Design and Implementation of Synchronous and Asynchronous Counters.
--- Content provided by FirstRanker.com ---
11.Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
12.
--- Content provided by FirstRanker.com ---
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).--- Content provided by FirstRanker.com ---
7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.1: STUDY OF BASIC GATES
--- Content provided by FirstRanker.com ---
Aim:To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
--- Content provided by FirstRanker.com ---
5. NAND gate IC 7400 16. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
--- Content provided by FirstRanker.com ---
Theory:Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND gate
--- Content provided by FirstRanker.com ---
The AND gate performs a logical multiplication commonly known as AND function. Theoutput is high when both the inputs are high. The output is low level when any one of the inputs is
low.
OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
--- Content provided by FirstRanker.com ---
high when any one of the inputs is high. The output is low level when both the inputs are low.NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
--- Content provided by FirstRanker.com ---
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are lowand any one of the input is low .The output is low level when both inputs are high.
NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
--- Content provided by FirstRanker.com ---
EX-OR gateAn Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
FirstRanker.com - FirstRanker's Choice
--- Content provided by FirstRanker.com ---
1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
?
--- Content provided by FirstRanker.com ---
DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
III SEMESTER - R 2017CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________Register No : _______________________________________
Section : _______________________________________
--- Content provided by FirstRanker.com ---
LABORATORY MANUAL
--- Content provided by FirstRanker.com ---
2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
--- Content provided by FirstRanker.com ---
training.--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
--- Content provided by FirstRanker.com ---
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag onheart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
--- Content provided by FirstRanker.com ---
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering toprofessional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
--- Content provided by FirstRanker.com ---
VISION
MISSION
--- Content provided by FirstRanker.com ---
VISION
MISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
--- Content provided by FirstRanker.com ---
1. FundamentalsTo provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
2. Core Competence
--- Content provided by FirstRanker.com ---
To train the students to meet the needs of core industry with an attitude of learning newtechnologies.
3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
--- Content provided by FirstRanker.com ---
enable them to find solutions to problems in industry and research that contributes to the overalldevelopment of society.
4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
--- Content provided by FirstRanker.com ---
team and stand as a good decision maker to manage any constraint environment with goodprofessional ethics at all strategies.
5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
--- Content provided by FirstRanker.com ---
commitment and lifelong learning needed for successful professional career.--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM OUTCOMES (POs)
a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
--- Content provided by FirstRanker.com ---
b. Graduates will be able to identify, formulate and solve electrical engineering problems.c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
--- Content provided by FirstRanker.com ---
analyze problems.g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
--- Content provided by FirstRanker.com ---
j. Graduates will develop confidence for self-education and ability for lifelong learning.k. Graduate who can participate and succeed in competitive examinations.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00SYLLABUS
--- Content provided by FirstRanker.com ---
Objectives:The student should be made to:
? Understand the various logic gates.
? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
--- Content provided by FirstRanker.com ---
? Be exposed to sequential circuits? Learn to use HDL
List of experiments:
1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
--- Content provided by FirstRanker.com ---
functions, code converters.3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
c. Magnitude Comparator
--- Content provided by FirstRanker.com ---
d. Application using multiplexers4. Design and implementation of sequential circuits:
a. Shift ?registers
b. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
--- Content provided by FirstRanker.com ---
6. Design and implementation of a simple digital system (Mini Project).Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
--- Content provided by FirstRanker.com ---
? Analyze a given digital circuit ? combinational and sequential.? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Content
--- Content provided by FirstRanker.com ---
Sl.No. Name of the Experiment Page No.1.
Verification of Boolean Theorems using Digital Logic Gates
2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
--- Content provided by FirstRanker.com ---
Functions, Code Converters3.
Implementation of half adder and full adder
4.
--- Content provided by FirstRanker.com ---
Implementation of half subtractor and full subtractor5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
--- Content provided by FirstRanker.com ---
6.Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
7.
--- Content provided by FirstRanker.com ---
Design and Implementation of Magnitude Comparator.8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
Design and Implementation of Shift Registers.
--- Content provided by FirstRanker.com ---
10.Design and Implementation of Synchronous and Asynchronous Counters.
11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
--- Content provided by FirstRanker.com ---
12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
--- Content provided by FirstRanker.com ---
7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Expt.No.1: STUDY OF BASIC GATESAim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
--- Content provided by FirstRanker.com ---
Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
--- Content provided by FirstRanker.com ---
3. OR gate IC 7432 14. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
--- Content provided by FirstRanker.com ---
8. Connecting wires As requiredTheory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
--- Content provided by FirstRanker.com ---
universal gates. Basic gates form these gates.AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
low.
--- Content provided by FirstRanker.com ---
OR gateThe OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
--- Content provided by FirstRanker.com ---
called an inverter. The output is high when the input is low. The output is low when the input is high.NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
NOR gate
--- Content provided by FirstRanker.com ---
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. Theoutput is low when one or both inputs are high.
EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
--- Content provided by FirstRanker.com ---
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
AND Gate Symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
OR Gate:
--- Content provided by FirstRanker.com ---
OR GATE:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
FirstRanker.com - FirstRanker's Choice
--- Content provided by FirstRanker.com ---
1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
?
--- Content provided by FirstRanker.com ---
DEPARTMENT OFCOMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
--- Content provided by FirstRanker.com ---
CS8382 DIGITAL SYSTEMS LABORATORY--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
--- Content provided by FirstRanker.com ---
Section : _______________________________________--- Content provided by FirstRanker.com ---
LABORATORY MANUAL2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
training.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
--- Content provided by FirstRanker.com ---
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at differentlevels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
--- Content provided by FirstRanker.com ---
Engineering and thereby produce extremely well trained employable, socially responsible and innovativeElectrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
--- Content provided by FirstRanker.com ---
? To provide highest quality learning environment for the students emphasizing fundamentalconcepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
--- Content provided by FirstRanker.com ---
VISIONMISSION
VISION
--- Content provided by FirstRanker.com ---
MISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
--- Content provided by FirstRanker.com ---
engineering enabling them to solve complex problems in order to develop real time applications.2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
technologies.
--- Content provided by FirstRanker.com ---
3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
development of society.
--- Content provided by FirstRanker.com ---
4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
--- Content provided by FirstRanker.com ---
5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PROGRAM OUTCOMES (POs)
--- Content provided by FirstRanker.com ---
a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
--- Content provided by FirstRanker.com ---
d. Graduates will be able to design a system, component or process as per needs and specifications.e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
--- Content provided by FirstRanker.com ---
h. Graduates will be able to communicate effectively by both verbal and written form.i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
SYLLABUS
Objectives:
The student should be made to:
--- Content provided by FirstRanker.com ---
? Understand the various logic gates.? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
? Learn to use HDL
--- Content provided by FirstRanker.com ---
List of experiments:1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
--- Content provided by FirstRanker.com ---
a. 4 ? bit binary adder / subtractorb. Parity generator / checker
c. Magnitude Comparator
d. Application using multiplexers
4. Design and implementation of sequential circuits:
--- Content provided by FirstRanker.com ---
a. Shift ?registersb. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
--- Content provided by FirstRanker.com ---
Course Outcomes:? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
--- Content provided by FirstRanker.com ---
? Design and Implement a simple digital system.--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Content
Sl.No. Name of the Experiment Page No.
1.
--- Content provided by FirstRanker.com ---
Verification of Boolean Theorems using Digital Logic Gates2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
--- Content provided by FirstRanker.com ---
3.Implementation of half adder and full adder
4.
Implementation of half subtractor and full subtractor
5.
--- Content provided by FirstRanker.com ---
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates andMSI Devices
6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
--- Content provided by FirstRanker.com ---
Devices7.
Design and Implementation of Magnitude Comparator.
8.
--- Content provided by FirstRanker.com ---
Design and Implementation of Application using Multiplexers / Demultiplexers.9.
Design and Implementation of Shift Registers.
10.
Design and Implementation of Synchronous and Asynchronous Counters.
--- Content provided by FirstRanker.com ---
11.Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
12.
--- Content provided by FirstRanker.com ---
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).--- Content provided by FirstRanker.com ---
7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.1: STUDY OF BASIC GATES
--- Content provided by FirstRanker.com ---
Aim:To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
--- Content provided by FirstRanker.com ---
5. NAND gate IC 7400 16. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
--- Content provided by FirstRanker.com ---
Theory:Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND gate
--- Content provided by FirstRanker.com ---
The AND gate performs a logical multiplication commonly known as AND function. Theoutput is high when both the inputs are high. The output is low level when any one of the inputs is
low.
OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
--- Content provided by FirstRanker.com ---
high when any one of the inputs is high. The output is low level when both the inputs are low.NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
--- Content provided by FirstRanker.com ---
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are lowand any one of the input is low .The output is low level when both inputs are high.
NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
--- Content provided by FirstRanker.com ---
EX-OR gateAn Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
--- Content provided by FirstRanker.com ---
8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
AND Gate Symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
OR Gate:--- Content provided by FirstRanker.com ---
OR GATE:--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
NOT Gate symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
EXOR Gate symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
FirstRanker.com - FirstRanker's Choice
--- Content provided by FirstRanker.com ---
1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
?
--- Content provided by FirstRanker.com ---
DEPARTMENT OFCOMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
--- Content provided by FirstRanker.com ---
CS8382 DIGITAL SYSTEMS LABORATORY--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
--- Content provided by FirstRanker.com ---
Section : _______________________________________--- Content provided by FirstRanker.com ---
LABORATORY MANUAL2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
training.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
--- Content provided by FirstRanker.com ---
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at differentlevels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
--- Content provided by FirstRanker.com ---
Engineering and thereby produce extremely well trained employable, socially responsible and innovativeElectrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
--- Content provided by FirstRanker.com ---
? To provide highest quality learning environment for the students emphasizing fundamentalconcepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
--- Content provided by FirstRanker.com ---
VISIONMISSION
VISION
--- Content provided by FirstRanker.com ---
MISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
--- Content provided by FirstRanker.com ---
engineering enabling them to solve complex problems in order to develop real time applications.2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
technologies.
--- Content provided by FirstRanker.com ---
3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
development of society.
--- Content provided by FirstRanker.com ---
4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
--- Content provided by FirstRanker.com ---
5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PROGRAM OUTCOMES (POs)
--- Content provided by FirstRanker.com ---
a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
--- Content provided by FirstRanker.com ---
d. Graduates will be able to design a system, component or process as per needs and specifications.e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
--- Content provided by FirstRanker.com ---
h. Graduates will be able to communicate effectively by both verbal and written form.i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
SYLLABUS
Objectives:
The student should be made to:
--- Content provided by FirstRanker.com ---
? Understand the various logic gates.? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
? Learn to use HDL
--- Content provided by FirstRanker.com ---
List of experiments:1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
--- Content provided by FirstRanker.com ---
a. 4 ? bit binary adder / subtractorb. Parity generator / checker
c. Magnitude Comparator
d. Application using multiplexers
4. Design and implementation of sequential circuits:
--- Content provided by FirstRanker.com ---
a. Shift ?registersb. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
--- Content provided by FirstRanker.com ---
Course Outcomes:? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
--- Content provided by FirstRanker.com ---
? Design and Implement a simple digital system.--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Content
Sl.No. Name of the Experiment Page No.
1.
--- Content provided by FirstRanker.com ---
Verification of Boolean Theorems using Digital Logic Gates2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
--- Content provided by FirstRanker.com ---
3.Implementation of half adder and full adder
4.
Implementation of half subtractor and full subtractor
5.
--- Content provided by FirstRanker.com ---
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates andMSI Devices
6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
--- Content provided by FirstRanker.com ---
Devices7.
Design and Implementation of Magnitude Comparator.
8.
--- Content provided by FirstRanker.com ---
Design and Implementation of Application using Multiplexers / Demultiplexers.9.
Design and Implementation of Shift Registers.
10.
Design and Implementation of Synchronous and Asynchronous Counters.
--- Content provided by FirstRanker.com ---
11.Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
12.
--- Content provided by FirstRanker.com ---
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).--- Content provided by FirstRanker.com ---
7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.1: STUDY OF BASIC GATES
--- Content provided by FirstRanker.com ---
Aim:To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
--- Content provided by FirstRanker.com ---
5. NAND gate IC 7400 16. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
--- Content provided by FirstRanker.com ---
Theory:Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND gate
--- Content provided by FirstRanker.com ---
The AND gate performs a logical multiplication commonly known as AND function. Theoutput is high when both the inputs are high. The output is low level when any one of the inputs is
low.
OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
--- Content provided by FirstRanker.com ---
high when any one of the inputs is high. The output is low level when both the inputs are low.NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
--- Content provided by FirstRanker.com ---
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are lowand any one of the input is low .The output is low level when both inputs are high.
NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
--- Content provided by FirstRanker.com ---
EX-OR gateAn Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
--- Content provided by FirstRanker.com ---
8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
AND Gate Symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
OR Gate:--- Content provided by FirstRanker.com ---
OR GATE:--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
NOT Gate symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
EXOR Gate symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00NAND Gate symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
NOR Gate:--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
FirstRanker.com - FirstRanker's Choice
--- Content provided by FirstRanker.com ---
1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
?
--- Content provided by FirstRanker.com ---
DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
III SEMESTER - R 2017CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________Register No : _______________________________________
Section : _______________________________________
--- Content provided by FirstRanker.com ---
LABORATORY MANUAL
--- Content provided by FirstRanker.com ---
2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
--- Content provided by FirstRanker.com ---
training.--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
--- Content provided by FirstRanker.com ---
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag onheart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
--- Content provided by FirstRanker.com ---
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering toprofessional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
--- Content provided by FirstRanker.com ---
VISION
MISSION
--- Content provided by FirstRanker.com ---
VISION
MISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
--- Content provided by FirstRanker.com ---
1. FundamentalsTo provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
2. Core Competence
--- Content provided by FirstRanker.com ---
To train the students to meet the needs of core industry with an attitude of learning newtechnologies.
3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
--- Content provided by FirstRanker.com ---
enable them to find solutions to problems in industry and research that contributes to the overalldevelopment of society.
4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
--- Content provided by FirstRanker.com ---
team and stand as a good decision maker to manage any constraint environment with goodprofessional ethics at all strategies.
5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
--- Content provided by FirstRanker.com ---
commitment and lifelong learning needed for successful professional career.--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM OUTCOMES (POs)
a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
--- Content provided by FirstRanker.com ---
b. Graduates will be able to identify, formulate and solve electrical engineering problems.c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
--- Content provided by FirstRanker.com ---
analyze problems.g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
--- Content provided by FirstRanker.com ---
j. Graduates will develop confidence for self-education and ability for lifelong learning.k. Graduate who can participate and succeed in competitive examinations.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00SYLLABUS
--- Content provided by FirstRanker.com ---
Objectives:The student should be made to:
? Understand the various logic gates.
? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
--- Content provided by FirstRanker.com ---
? Be exposed to sequential circuits? Learn to use HDL
List of experiments:
1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
--- Content provided by FirstRanker.com ---
functions, code converters.3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
c. Magnitude Comparator
--- Content provided by FirstRanker.com ---
d. Application using multiplexers4. Design and implementation of sequential circuits:
a. Shift ?registers
b. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
--- Content provided by FirstRanker.com ---
6. Design and implementation of a simple digital system (Mini Project).Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
--- Content provided by FirstRanker.com ---
? Analyze a given digital circuit ? combinational and sequential.? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Content
--- Content provided by FirstRanker.com ---
Sl.No. Name of the Experiment Page No.1.
Verification of Boolean Theorems using Digital Logic Gates
2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
--- Content provided by FirstRanker.com ---
Functions, Code Converters3.
Implementation of half adder and full adder
4.
--- Content provided by FirstRanker.com ---
Implementation of half subtractor and full subtractor5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
--- Content provided by FirstRanker.com ---
6.Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
7.
--- Content provided by FirstRanker.com ---
Design and Implementation of Magnitude Comparator.8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
Design and Implementation of Shift Registers.
--- Content provided by FirstRanker.com ---
10.Design and Implementation of Synchronous and Asynchronous Counters.
11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
--- Content provided by FirstRanker.com ---
12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
--- Content provided by FirstRanker.com ---
7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Expt.No.1: STUDY OF BASIC GATESAim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
--- Content provided by FirstRanker.com ---
Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
--- Content provided by FirstRanker.com ---
3. OR gate IC 7432 14. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
--- Content provided by FirstRanker.com ---
8. Connecting wires As requiredTheory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
--- Content provided by FirstRanker.com ---
universal gates. Basic gates form these gates.AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
low.
--- Content provided by FirstRanker.com ---
OR gateThe OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
--- Content provided by FirstRanker.com ---
called an inverter. The output is high when the input is low. The output is low when the input is high.NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
NOR gate
--- Content provided by FirstRanker.com ---
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. Theoutput is low when one or both inputs are high.
EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
--- Content provided by FirstRanker.com ---
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
AND Gate Symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
OR Gate:
--- Content provided by FirstRanker.com ---
OR GATE:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
NOT Gate symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
EXOR Gate symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
NAND Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
NOR Gate:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Procedure:
1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
--- Content provided by FirstRanker.com ---
thpin is grounded and 14
th
pin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
--- Content provided by FirstRanker.com ---
Result:
The truth tables of all the basic logic gates were verified.
--- Content provided by FirstRanker.com ---
Outcome:
At the completion of an experiment student will able to verify the truth
table of all basic gates
--- Content provided by FirstRanker.com ---
1. List out the basic gate.
--- Content provided by FirstRanker.com ---
2. Mention the universal gate.3. How many gates presented in IC 7408?
4. What is IC?
5. What are the applications of gates?
6. Write the truth table of AND gate.
--- Content provided by FirstRanker.com ---
7. Write the truth table of OR gate.8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
--- Content provided by FirstRanker.com ---
12. What are the classifications of IC?13. What are types of linear integrated circuit?
14. What is meant by etching?
15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
--- Content provided by FirstRanker.com ---
Viva ? VoceFirstRanker.com - FirstRanker's Choice
--- Content provided by FirstRanker.com ---
1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
?
--- Content provided by FirstRanker.com ---
DEPARTMENT OFCOMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
--- Content provided by FirstRanker.com ---
CS8382 DIGITAL SYSTEMS LABORATORY--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
--- Content provided by FirstRanker.com ---
Section : _______________________________________--- Content provided by FirstRanker.com ---
LABORATORY MANUAL2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
training.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
--- Content provided by FirstRanker.com ---
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at differentlevels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
--- Content provided by FirstRanker.com ---
Engineering and thereby produce extremely well trained employable, socially responsible and innovativeElectrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
--- Content provided by FirstRanker.com ---
? To provide highest quality learning environment for the students emphasizing fundamentalconcepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
--- Content provided by FirstRanker.com ---
VISIONMISSION
VISION
--- Content provided by FirstRanker.com ---
MISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
--- Content provided by FirstRanker.com ---
engineering enabling them to solve complex problems in order to develop real time applications.2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
technologies.
--- Content provided by FirstRanker.com ---
3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
development of society.
--- Content provided by FirstRanker.com ---
4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
--- Content provided by FirstRanker.com ---
5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PROGRAM OUTCOMES (POs)
--- Content provided by FirstRanker.com ---
a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
--- Content provided by FirstRanker.com ---
d. Graduates will be able to design a system, component or process as per needs and specifications.e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
--- Content provided by FirstRanker.com ---
h. Graduates will be able to communicate effectively by both verbal and written form.i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
SYLLABUS
Objectives:
The student should be made to:
--- Content provided by FirstRanker.com ---
? Understand the various logic gates.? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
? Learn to use HDL
--- Content provided by FirstRanker.com ---
List of experiments:1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
--- Content provided by FirstRanker.com ---
a. 4 ? bit binary adder / subtractorb. Parity generator / checker
c. Magnitude Comparator
d. Application using multiplexers
4. Design and implementation of sequential circuits:
--- Content provided by FirstRanker.com ---
a. Shift ?registersb. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
--- Content provided by FirstRanker.com ---
Course Outcomes:? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
--- Content provided by FirstRanker.com ---
? Design and Implement a simple digital system.--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Content
Sl.No. Name of the Experiment Page No.
1.
--- Content provided by FirstRanker.com ---
Verification of Boolean Theorems using Digital Logic Gates2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
--- Content provided by FirstRanker.com ---
3.Implementation of half adder and full adder
4.
Implementation of half subtractor and full subtractor
5.
--- Content provided by FirstRanker.com ---
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates andMSI Devices
6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
--- Content provided by FirstRanker.com ---
Devices7.
Design and Implementation of Magnitude Comparator.
8.
--- Content provided by FirstRanker.com ---
Design and Implementation of Application using Multiplexers / Demultiplexers.9.
Design and Implementation of Shift Registers.
10.
Design and Implementation of Synchronous and Asynchronous Counters.
--- Content provided by FirstRanker.com ---
11.Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
12.
--- Content provided by FirstRanker.com ---
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).--- Content provided by FirstRanker.com ---
7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.1: STUDY OF BASIC GATES
--- Content provided by FirstRanker.com ---
Aim:To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
--- Content provided by FirstRanker.com ---
5. NAND gate IC 7400 16. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
--- Content provided by FirstRanker.com ---
Theory:Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND gate
--- Content provided by FirstRanker.com ---
The AND gate performs a logical multiplication commonly known as AND function. Theoutput is high when both the inputs are high. The output is low level when any one of the inputs is
low.
OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
--- Content provided by FirstRanker.com ---
high when any one of the inputs is high. The output is low level when both the inputs are low.NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
--- Content provided by FirstRanker.com ---
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are lowand any one of the input is low .The output is low level when both inputs are high.
NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
--- Content provided by FirstRanker.com ---
EX-OR gateAn Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
--- Content provided by FirstRanker.com ---
8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
AND Gate Symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
OR Gate:--- Content provided by FirstRanker.com ---
OR GATE:--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
NOT Gate symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
EXOR Gate symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00NAND Gate symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
NOR Gate:--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
--- Content provided by FirstRanker.com ---
1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
th
pin is grounded and 14
--- Content provided by FirstRanker.com ---
thpin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
--- Content provided by FirstRanker.com ---
Result:The truth tables of all the basic logic gates were verified.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to verify the truth
table of all basic gates
--- Content provided by FirstRanker.com ---
1. List out the basic gate.
2. Mention the universal gate.
3. How many gates presented in IC 7408?
--- Content provided by FirstRanker.com ---
4. What is IC?5. What are the applications of gates?
6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
--- Content provided by FirstRanker.com ---
9. Write the truth table of NAND gate.10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
13. What are types of linear integrated circuit?
--- Content provided by FirstRanker.com ---
14. What is meant by etching?15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
Viva ? Voce
--- Content provided by FirstRanker.com ---
12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Expt.No.2:VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
--- Content provided by FirstRanker.com ---
Aim: To verification of Boolean theorems using logic gates
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
--- Content provided by FirstRanker.com ---
5. NAND gate IC 7400 16. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
8. Connecting wires As required
--- Content provided by FirstRanker.com ---
Theory:
BASIC Boolean Laws
--- Content provided by FirstRanker.com ---
1. Commutative LawThe binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A
--- Content provided by FirstRanker.com ---
2. Associative Law
The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
--- Content provided by FirstRanker.com ---
2. A.(B.C) = (A.B).C3. Distributive Law
The binary operator OR, AND is said to be distributive if,
--- Content provided by FirstRanker.com ---
1. A+(B.C) = (A+B).(A+C)2. A.(B+C) = (A.B)+(A.C)
4. Absorption Law
--- Content provided by FirstRanker.com ---
1. A+AB = A2. A+AB =A+B
--- Content provided by FirstRanker.com ---
FirstRanker.com - FirstRanker's Choice
--- Content provided by FirstRanker.com ---
1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
?
--- Content provided by FirstRanker.com ---
DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
--- Content provided by FirstRanker.com ---
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
Name : _______________________________________
--- Content provided by FirstRanker.com ---
Register No : _______________________________________Section : _______________________________________
--- Content provided by FirstRanker.com ---
LABORATORY MANUAL
--- Content provided by FirstRanker.com ---
2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
training.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
--- Content provided by FirstRanker.com ---
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
--- Content provided by FirstRanker.com ---
heart and soulDEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and ElectronicsEngineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
--- Content provided by FirstRanker.com ---
professional ethical code.? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
--- Content provided by FirstRanker.com ---
VISION
MISSION
--- Content provided by FirstRanker.com ---
VISIONMISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
1. Fundamentals
--- Content provided by FirstRanker.com ---
To provide students with a solid foundation in mathematics, science and fundamentals ofengineering enabling them to solve complex problems in order to develop real time applications.
2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
--- Content provided by FirstRanker.com ---
technologies.3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
--- Content provided by FirstRanker.com ---
development of society.4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
--- Content provided by FirstRanker.com ---
professional ethics at all strategies.5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM OUTCOMES (POs)a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
--- Content provided by FirstRanker.com ---
c. Graduates will be able to design and conduct experiments, analyze and interpret data.d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
--- Content provided by FirstRanker.com ---
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
--- Content provided by FirstRanker.com ---
k. Graduate who can participate and succeed in competitive examinations.--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
SYLLABUS
Objectives:
--- Content provided by FirstRanker.com ---
The student should be made to:? Understand the various logic gates.
? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
--- Content provided by FirstRanker.com ---
? Learn to use HDLList of experiments:
1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
--- Content provided by FirstRanker.com ---
3. Design and implementation of combinational circuits using MSI devices:a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
c. Magnitude Comparator
d. Application using multiplexers
--- Content provided by FirstRanker.com ---
4. Design and implementation of sequential circuits:a. Shift ?registers
b. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
--- Content provided by FirstRanker.com ---
Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
--- Content provided by FirstRanker.com ---
? Design the different functional units in a digital computer system.? Design and Implement a simple digital system.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Content
Sl.No. Name of the Experiment Page No.
--- Content provided by FirstRanker.com ---
1.Verification of Boolean Theorems using Digital Logic Gates
2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
--- Content provided by FirstRanker.com ---
3.
Implementation of half adder and full adder
4.
Implementation of half subtractor and full subtractor
--- Content provided by FirstRanker.com ---
5.Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
6.
--- Content provided by FirstRanker.com ---
Design and Implementation of Parity Generator / Checker using Basic Gates and MSIDevices
7.
Design and Implementation of Magnitude Comparator.
--- Content provided by FirstRanker.com ---
8.Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
Design and Implementation of Shift Registers.
10.
--- Content provided by FirstRanker.com ---
Design and Implementation of Synchronous and Asynchronous Counters.11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
--- Content provided by FirstRanker.com ---
12.Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
--- Content provided by FirstRanker.com ---
7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.1: STUDY OF BASIC GATES
--- Content provided by FirstRanker.com ---
Aim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
--- Content provided by FirstRanker.com ---
4. NOT gate IC 7404 15. NAND gate IC 7400 1
6. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
--- Content provided by FirstRanker.com ---
Theory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
--- Content provided by FirstRanker.com ---
AND gateThe AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
low.
OR gate
--- Content provided by FirstRanker.com ---
The OR gate performs a logical addition commonly known as OR function. The output ishigh when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
--- Content provided by FirstRanker.com ---
NAND gateThe NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
--- Content provided by FirstRanker.com ---
output is low when one or both inputs are high.EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
--- Content provided by FirstRanker.com ---
8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
AND Gate Symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
OR Gate:
--- Content provided by FirstRanker.com ---
OR GATE:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
NOT Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
EXOR Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
NAND Gate symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
NOR Gate:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Procedure:1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
th
--- Content provided by FirstRanker.com ---
pin is grounded and 14th
pin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
--- Content provided by FirstRanker.com ---
Result:
The truth tables of all the basic logic gates were verified.
--- Content provided by FirstRanker.com ---
Outcome:At the completion of an experiment student will able to verify the truth
table of all basic gates
--- Content provided by FirstRanker.com ---
1. List out the basic gate.
2. Mention the universal gate.
--- Content provided by FirstRanker.com ---
3. How many gates presented in IC 7408?4. What is IC?
5. What are the applications of gates?
6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
--- Content provided by FirstRanker.com ---
8. Write the truth table of NOT gate.9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
--- Content provided by FirstRanker.com ---
13. What are types of linear integrated circuit?14. What is meant by etching?
15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
Viva ? Voce
--- Content provided by FirstRanker.com ---
12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Expt.No.2:
VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
--- Content provided by FirstRanker.com ---
Aim: To verification of Boolean theorems using logic gates
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
--- Content provided by FirstRanker.com ---
4. NOT gate IC 7404 15. NAND gate IC 7400 1
6. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
8. Connecting wires As required
--- Content provided by FirstRanker.com ---
Theory:
BASIC Boolean Laws
--- Content provided by FirstRanker.com ---
1. Commutative Law
The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
--- Content provided by FirstRanker.com ---
2. A.B=B.A2. Associative Law
The binary operator OR, AND is said to be associative if,
--- Content provided by FirstRanker.com ---
1. A+(B+C) = (A+B)+C2. A.(B.C) = (A.B).C
3. Distributive Law
--- Content provided by FirstRanker.com ---
The binary operator OR, AND is said to be distributive if,1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
4. Absorption Law
--- Content provided by FirstRanker.com ---
1. A+AB = A
2. A+AB =A+B
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
5. Idempotent Law
1. A+A = A
2. A.A = A
--- Content provided by FirstRanker.com ---
6. Complementary Law
1. A+A' = 1
2. A.A' = 0
--- Content provided by FirstRanker.com ---
7. De Morgan ?s Theorem
1. The complement of the sum is equal to the sum of the product of the individual
complements.
--- Content provided by FirstRanker.com ---
A+B = A.B2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
--- Content provided by FirstRanker.com ---
Design1. Absorption Law
A+AB = A
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
2. Involution (or) Double complement Law
A = A
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
3. Idempotent Law
1. A+A = A
--- Content provided by FirstRanker.com ---
2. A.A = A
--- Content provided by FirstRanker.com ---
FirstRanker.com - FirstRanker's Choice
--- Content provided by FirstRanker.com ---
1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
?
--- Content provided by FirstRanker.com ---
DEPARTMENT OFCOMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
--- Content provided by FirstRanker.com ---
CS8382 DIGITAL SYSTEMS LABORATORY--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
--- Content provided by FirstRanker.com ---
Section : _______________________________________--- Content provided by FirstRanker.com ---
LABORATORY MANUAL2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
training.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
--- Content provided by FirstRanker.com ---
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at differentlevels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
--- Content provided by FirstRanker.com ---
Engineering and thereby produce extremely well trained employable, socially responsible and innovativeElectrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
--- Content provided by FirstRanker.com ---
? To provide highest quality learning environment for the students emphasizing fundamentalconcepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
--- Content provided by FirstRanker.com ---
VISIONMISSION
VISION
--- Content provided by FirstRanker.com ---
MISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
--- Content provided by FirstRanker.com ---
engineering enabling them to solve complex problems in order to develop real time applications.2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
technologies.
--- Content provided by FirstRanker.com ---
3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
development of society.
--- Content provided by FirstRanker.com ---
4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
--- Content provided by FirstRanker.com ---
5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PROGRAM OUTCOMES (POs)
--- Content provided by FirstRanker.com ---
a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
--- Content provided by FirstRanker.com ---
d. Graduates will be able to design a system, component or process as per needs and specifications.e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
--- Content provided by FirstRanker.com ---
h. Graduates will be able to communicate effectively by both verbal and written form.i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
SYLLABUS
Objectives:
The student should be made to:
--- Content provided by FirstRanker.com ---
? Understand the various logic gates.? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
? Learn to use HDL
--- Content provided by FirstRanker.com ---
List of experiments:1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
--- Content provided by FirstRanker.com ---
a. 4 ? bit binary adder / subtractorb. Parity generator / checker
c. Magnitude Comparator
d. Application using multiplexers
4. Design and implementation of sequential circuits:
--- Content provided by FirstRanker.com ---
a. Shift ?registersb. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
--- Content provided by FirstRanker.com ---
Course Outcomes:? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
--- Content provided by FirstRanker.com ---
? Design and Implement a simple digital system.--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Content
Sl.No. Name of the Experiment Page No.
1.
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Verification of Boolean Theorems using Digital Logic Gates2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
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3.Implementation of half adder and full adder
4.
Implementation of half subtractor and full subtractor
5.
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Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates andMSI Devices
6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
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Devices7.
Design and Implementation of Magnitude Comparator.
8.
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Design and Implementation of Application using Multiplexers / Demultiplexers.9.
Design and Implementation of Shift Registers.
10.
Design and Implementation of Synchronous and Asynchronous Counters.
--- Content provided by FirstRanker.com ---
11.Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
12.
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Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).--- Content provided by FirstRanker.com ---
7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.1: STUDY OF BASIC GATES
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Aim:To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
--- Content provided by FirstRanker.com ---
5. NAND gate IC 7400 16. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
--- Content provided by FirstRanker.com ---
Theory:Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND gate
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The AND gate performs a logical multiplication commonly known as AND function. Theoutput is high when both the inputs are high. The output is low level when any one of the inputs is
low.
OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
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high when any one of the inputs is high. The output is low level when both the inputs are low.NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
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The NAND gate is a contraction of AND-NOT. The output is high when both inputs are lowand any one of the input is low .The output is low level when both inputs are high.
NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
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EX-OR gateAn Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
--- Content provided by FirstRanker.com ---
8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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AND Gate Symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
OR Gate:--- Content provided by FirstRanker.com ---
OR GATE:--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00NAND Gate symbol: PIN Diagram:
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NOR Gate:--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
--- Content provided by FirstRanker.com ---
1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
th
pin is grounded and 14
--- Content provided by FirstRanker.com ---
thpin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
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Result:The truth tables of all the basic logic gates were verified.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to verify the truth
table of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
3. How many gates presented in IC 7408?
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4. What is IC?5. What are the applications of gates?
6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
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9. Write the truth table of NAND gate.10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
13. What are types of linear integrated circuit?
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14. What is meant by etching?15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Expt.No.2:VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
--- Content provided by FirstRanker.com ---
Aim: To verification of Boolean theorems using logic gates
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
--- Content provided by FirstRanker.com ---
5. NAND gate IC 7400 16. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
BASIC Boolean Laws
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1. Commutative LawThe binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A
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2. Associative Law
The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
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2. A.(B.C) = (A.B).C3. Distributive Law
The binary operator OR, AND is said to be distributive if,
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1. A+(B.C) = (A+B).(A+C)2. A.(B+C) = (A.B)+(A.C)
4. Absorption Law
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1. A+AB = A2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law1. A+A = A
2. A.A = A
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6. Complementary Law1. A+A' = 1
2. A.A' = 0
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7. De Morgan ?s Theorem1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
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2. The complement of the product is equal to the sum of the individual complements.A.B = A+B
Design
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1. Absorption LawA+AB = A
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2. Involution (or) Double complement LawA = A
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3. Idempotent Law
1. A+A = A
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2. A.A = A--- Content provided by FirstRanker.com ---
14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
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A+B = A.B5. Distributive Law
A+(B.C) = (A+B).(A+C)
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Procedure:
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
cc
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.3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
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Result:Thus the above stated Boolean laws are verified.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to know the basic laws with their truth table.1. What is Demorgan?s law?
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2. What is associative law?3. What is mean by compliment gate?
4. Explain the basic laws in digital electronics
5. What is double complement?
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Viva ? VoceFirstRanker.com - FirstRanker's Choice
--- Content provided by FirstRanker.com ---
1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OFCOMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
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CS8382 DIGITAL SYSTEMS LABORATORY--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
--- Content provided by FirstRanker.com ---
Section : _______________________________________--- Content provided by FirstRanker.com ---
LABORATORY MANUAL2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
training.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
--- Content provided by FirstRanker.com ---
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at differentlevels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
--- Content provided by FirstRanker.com ---
Engineering and thereby produce extremely well trained employable, socially responsible and innovativeElectrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
--- Content provided by FirstRanker.com ---
? To provide highest quality learning environment for the students emphasizing fundamentalconcepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
--- Content provided by FirstRanker.com ---
VISIONMISSION
VISION
--- Content provided by FirstRanker.com ---
MISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
--- Content provided by FirstRanker.com ---
engineering enabling them to solve complex problems in order to develop real time applications.2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
technologies.
--- Content provided by FirstRanker.com ---
3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
development of society.
--- Content provided by FirstRanker.com ---
4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
--- Content provided by FirstRanker.com ---
5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
--- Content provided by FirstRanker.com ---
d. Graduates will be able to design a system, component or process as per needs and specifications.e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
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h. Graduates will be able to communicate effectively by both verbal and written form.i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
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CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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SYLLABUS
Objectives:
The student should be made to:
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? Understand the various logic gates.? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
? Learn to use HDL
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List of experiments:1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
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a. 4 ? bit binary adder / subtractorb. Parity generator / checker
c. Magnitude Comparator
d. Application using multiplexers
4. Design and implementation of sequential circuits:
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a. Shift ?registersb. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
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Course Outcomes:? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
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? Design and Implement a simple digital system.--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Content
Sl.No. Name of the Experiment Page No.
1.
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Verification of Boolean Theorems using Digital Logic Gates2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
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3.Implementation of half adder and full adder
4.
Implementation of half subtractor and full subtractor
5.
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Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates andMSI Devices
6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
--- Content provided by FirstRanker.com ---
Devices7.
Design and Implementation of Magnitude Comparator.
8.
--- Content provided by FirstRanker.com ---
Design and Implementation of Application using Multiplexers / Demultiplexers.9.
Design and Implementation of Shift Registers.
10.
Design and Implementation of Synchronous and Asynchronous Counters.
--- Content provided by FirstRanker.com ---
11.Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
12.
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Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).--- Content provided by FirstRanker.com ---
7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.1: STUDY OF BASIC GATES
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Aim:To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
--- Content provided by FirstRanker.com ---
5. NAND gate IC 7400 16. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
--- Content provided by FirstRanker.com ---
Theory:Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND gate
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The AND gate performs a logical multiplication commonly known as AND function. Theoutput is high when both the inputs are high. The output is low level when any one of the inputs is
low.
OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
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high when any one of the inputs is high. The output is low level when both the inputs are low.NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
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The NAND gate is a contraction of AND-NOT. The output is high when both inputs are lowand any one of the input is low .The output is low level when both inputs are high.
NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
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EX-OR gateAn Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
--- Content provided by FirstRanker.com ---
8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
AND Gate Symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
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OR Gate:--- Content provided by FirstRanker.com ---
OR GATE:--- Content provided by FirstRanker.com ---
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00NAND Gate symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
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NOR Gate:--- Content provided by FirstRanker.com ---
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
--- Content provided by FirstRanker.com ---
1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
th
pin is grounded and 14
--- Content provided by FirstRanker.com ---
thpin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
--- Content provided by FirstRanker.com ---
Result:The truth tables of all the basic logic gates were verified.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to verify the truth
table of all basic gates
--- Content provided by FirstRanker.com ---
1. List out the basic gate.
2. Mention the universal gate.
3. How many gates presented in IC 7408?
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4. What is IC?5. What are the applications of gates?
6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
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9. Write the truth table of NAND gate.10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
13. What are types of linear integrated circuit?
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14. What is meant by etching?15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Expt.No.2:VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gates
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
--- Content provided by FirstRanker.com ---
5. NAND gate IC 7400 16. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
BASIC Boolean Laws
--- Content provided by FirstRanker.com ---
1. Commutative LawThe binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A
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2. Associative Law
The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
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2. A.(B.C) = (A.B).C3. Distributive Law
The binary operator OR, AND is said to be distributive if,
--- Content provided by FirstRanker.com ---
1. A+(B.C) = (A+B).(A+C)2. A.(B+C) = (A.B)+(A.C)
4. Absorption Law
--- Content provided by FirstRanker.com ---
1. A+AB = A2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law1. A+A = A
2. A.A = A
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6. Complementary Law1. A+A' = 1
2. A.A' = 0
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7. De Morgan ?s Theorem1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
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2. The complement of the product is equal to the sum of the individual complements.A.B = A+B
Design
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1. Absorption LawA+AB = A
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2. Involution (or) Double complement LawA = A
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3. Idempotent Law
1. A+A = A
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2. A.A = A--- Content provided by FirstRanker.com ---
14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
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A+B = A.B5. Distributive Law
A+(B.C) = (A+B).(A+C)
--- Content provided by FirstRanker.com ---
Procedure:
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
cc
--- Content provided by FirstRanker.com ---
.3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
--- Content provided by FirstRanker.com ---
Result:Thus the above stated Boolean laws are verified.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to know the basic laws with their truth table.1. What is Demorgan?s law?
--- Content provided by FirstRanker.com ---
2. What is associative law?3. What is mean by compliment gate?
4. Explain the basic laws in digital electronics
5. What is double complement?
--- Content provided by FirstRanker.com ---
Viva ? Voce--- Content provided by FirstRanker.com ---
15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
To design and verify the truth table of the Half Adder & Full Adder circuits
--- Content provided by FirstRanker.com ---
Apparatus required:
S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
--- Content provided by FirstRanker.com ---
2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
--- Content provided by FirstRanker.com ---
Theory:
The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
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0 + 0 = 0
0 + 1 = 1
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1 + 0 = 11 + 1 = 0 (with 1 as carry)
The first three operations produce a sum of whose length is one digit, but when the last operation is
--- Content provided by FirstRanker.com ---
performed the sum is two digits. The higher significant bit of this result is called a carry and lowersignificant bit is called the sum.
Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
--- Content provided by FirstRanker.com ---
Full adder:
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
--- Content provided by FirstRanker.com ---
From the truth table, the expression for sum and carry bits of the output can be obtained as,
SUM = A?B?C + A?BC? + AB?C? + ABC
CARRY = A?BC + AB?C + ABC? +ABC
--- Content provided by FirstRanker.com ---
FirstRanker.com - FirstRanker's Choice1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
?
--- Content provided by FirstRanker.com ---
DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
III SEMESTER - R 2017
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
Section : _______________________________________
--- Content provided by FirstRanker.com ---
LABORATORY MANUAL
--- Content provided by FirstRanker.com ---
2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
--- Content provided by FirstRanker.com ---
enterprising professionals conforming to global standards through value based quality education andtraining.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
--- Content provided by FirstRanker.com ---
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
--- Content provided by FirstRanker.com ---
needs.? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
--- Content provided by FirstRanker.com ---
industry by continuous assessment and training.VISION
--- Content provided by FirstRanker.com ---
MISSIONVISION
MISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
--- Content provided by FirstRanker.com ---
1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
--- Content provided by FirstRanker.com ---
2. Core CompetenceTo train the students to meet the needs of core industry with an attitude of learning new
technologies.
3. Breadth
--- Content provided by FirstRanker.com ---
To provide relevant training and experience to bridge the gap between theory and practice whichenable them to find solutions to problems in industry and research that contributes to the overall
development of society.
4. Professionalism
--- Content provided by FirstRanker.com ---
To inculcate professional and effective communication skills to the students to make them lead ateam and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
5. Lifelong Learning/Ethics
--- Content provided by FirstRanker.com ---
To practice ethical and professional responsibilities in the organization and society withcommitment and lifelong learning needed for successful professional career.
--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM OUTCOMES (POs)
--- Content provided by FirstRanker.com ---
a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
--- Content provided by FirstRanker.com ---
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment toanalyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
--- Content provided by FirstRanker.com ---
will be aware of contemporary issues.j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
SYLLABUS
--- Content provided by FirstRanker.com ---
Objectives:
The student should be made to:
? Understand the various logic gates.
? Be familiar with various combinational circuits.
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? Understand the various components used in the design of digital computers.? Be exposed to sequential circuits
? Learn to use HDL
List of experiments:
1. Verification of Boolean Theorems using basic gates.
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2. Design and implementation of combinational circuits using basic gates for arbitraryfunctions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
--- Content provided by FirstRanker.com ---
c. Magnitude Comparatord. Application using multiplexers
4. Design and implementation of sequential circuits:
a. Shift ?registers
b. Synchronous and asynchronous counters
--- Content provided by FirstRanker.com ---
5. Coding combinational / sequential circuits using HDL.6. Design and implementation of a simple digital system (Mini Project).
Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
--- Content provided by FirstRanker.com ---
? Design and Implement combinational and sequential circuits.? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Content
--- Content provided by FirstRanker.com ---
Sl.No. Name of the Experiment Page No.
1.
Verification of Boolean Theorems using Digital Logic Gates
2.
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Design and Implementation of Combinational Circuits using Basic Gates for ArbitraryFunctions, Code Converters
3.
Implementation of half adder and full adder
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4.Implementation of half subtractor and full subtractor
5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
--- Content provided by FirstRanker.com ---
6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
--- Content provided by FirstRanker.com ---
7.Design and Implementation of Magnitude Comparator.
8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
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Design and Implementation of Shift Registers.10.
Design and Implementation of Synchronous and Asynchronous Counters.
11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
--- Content provided by FirstRanker.com ---
HDL Software Required).12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
--- Content provided by FirstRanker.com ---
7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Expt.No.1: STUDY OF BASIC GATES
Aim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
--- Content provided by FirstRanker.com ---
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
--- Content provided by FirstRanker.com ---
2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
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7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
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more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known asuniversal gates. Basic gates form these gates.
AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
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low.OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
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A NOT gate is the physical realization of the complementation operation. The NOT gate iscalled an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
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NOR gateThe NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
--- Content provided by FirstRanker.com ---
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusiveOR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
--- Content provided by FirstRanker.com ---
8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00AND Gate Symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
OR Gate:
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OR GATE:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
NOT Gate symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
NAND Gate symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
NOR Gate:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Procedure:
1. Connections are given as per the circuit diagram.
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2. For all the IC?s 7th
pin is grounded and 14
th
pin is given +5 supply.
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3. Apply the inputs and verify the truth table for all gates.Result:
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The truth tables of all the basic logic gates were verified.Outcome:
At the completion of an experiment student will able to verify the truth
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table of all basic gates--- Content provided by FirstRanker.com ---
1. List out the basic gate.2. Mention the universal gate.
3. How many gates presented in IC 7408?
4. What is IC?
5. What are the applications of gates?
--- Content provided by FirstRanker.com ---
6. Write the truth table of AND gate.7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
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11. Write the truth table of EX- OR gate.12. What are the classifications of IC?
13. What are types of linear integrated circuit?
14. What is meant by etching?
15. What are the advantages of IC?
--- Content provided by FirstRanker.com ---
16. Write the truth table of EX- NOR gate.Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.2:
--- Content provided by FirstRanker.com ---
VERIFICATION OF BOOLEAN THEOREMS USING LOGICGATES
Aim: To verification of Boolean theorems using logic gates
--- Content provided by FirstRanker.com ---
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
--- Content provided by FirstRanker.com ---
2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 3
--- Content provided by FirstRanker.com ---
7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
--- Content provided by FirstRanker.com ---
BASIC Boolean Laws
1. Commutative Law
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The binary operator OR, AND is said to be commutative if,1. A+B = B+A
2. A.B=B.A
2. Associative Law
--- Content provided by FirstRanker.com ---
The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
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3. Distributive LawThe binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
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4. Absorption Law
1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
5. Idempotent Law
--- Content provided by FirstRanker.com ---
1. A+A = A2. A.A = A
6. Complementary Law
--- Content provided by FirstRanker.com ---
1. A+A' = 12. A.A' = 0
7. De Morgan ?s Theorem
--- Content provided by FirstRanker.com ---
1. The complement of the sum is equal to the sum of the product of the individualcomplements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
--- Content provided by FirstRanker.com ---
Design
1. Absorption Law
--- Content provided by FirstRanker.com ---
A+AB = A--- Content provided by FirstRanker.com ---
2. Involution (or) Double complement Law
--- Content provided by FirstRanker.com ---
A = A--- Content provided by FirstRanker.com ---
3. Idempotent Law
--- Content provided by FirstRanker.com ---
1. A+A = A
2. A.A = A
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
4. Demorgan ?s Law
A+B = A.B
--- Content provided by FirstRanker.com ---
5. Distributive Law
A+(B.C) = (A+B).(A+C)
Procedure:
--- Content provided by FirstRanker.com ---
1. Obtain the required IC along with the Digital trainer kit.2. Connect zero volts to GND pin and +5 volts to V
cc
.
3. Apply the inputs to the respective input pins.
--- Content provided by FirstRanker.com ---
4. Verify the output with the truth table.Result:
--- Content provided by FirstRanker.com ---
Thus the above stated Boolean laws are verified.Outcome:
At the completion of an experiment student will able to know the basic laws with their truth table.
--- Content provided by FirstRanker.com ---
1. What is Demorgan?s law?
2. What is associative law?
3. What is mean by compliment gate?
--- Content provided by FirstRanker.com ---
4. Explain the basic laws in digital electronics5. What is double complement?
Viva ? Voce
--- Content provided by FirstRanker.com ---
15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Expt.No.3: HALF ADDER AND FULL ADDERAim:
To design and verify the truth table of the Half Adder & Full Adder circuits
Apparatus required:
--- Content provided by FirstRanker.com ---
S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
--- Content provided by FirstRanker.com ---
4. NOT gate IC 7404 15. EX-OR gate IC 7486 1
6. Connecting wires As required
--- Content provided by FirstRanker.com ---
Theory:The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
0 + 0 = 0
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0 + 1 = 1
1 + 0 = 1
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1 + 1 = 0 (with 1 as carry)The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
--- Content provided by FirstRanker.com ---
Half adder:A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
Full adder:
--- Content provided by FirstRanker.com ---
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. Thethree input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
From the truth table, the expression for sum and carry bits of the output can be obtained as,
--- Content provided by FirstRanker.com ---
SUM = A?B?C + A?BC? + AB?C? + ABCCARRY = A?BC + AB?C + ABC? +ABC
--- Content provided by FirstRanker.com ---
16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half Adder
--- Content provided by FirstRanker.com ---
Truth table:--- Content provided by FirstRanker.com ---
From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
--- Content provided by FirstRanker.com ---
S = A BCarry, C = A . B
--- Content provided by FirstRanker.com ---
Circuit diagram:--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Full adder
--- Content provided by FirstRanker.com ---
Truth table:Sl.No. Input Output
A B C S C
1. 0 0 0 0 0
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2. 0 0 1 1 03. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
--- Content provided by FirstRanker.com ---
7. 1 1 0 0 18. 1 1 1 1 1
Sl.No. Input Output
--- Content provided by FirstRanker.com ---
A B S C1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
4. 1 1 1 1
--- Content provided by FirstRanker.com ---
FirstRanker.com - FirstRanker's Choice1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
?
--- Content provided by FirstRanker.com ---
DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
III SEMESTER - R 2017
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
Section : _______________________________________
--- Content provided by FirstRanker.com ---
LABORATORY MANUAL
--- Content provided by FirstRanker.com ---
2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
--- Content provided by FirstRanker.com ---
enterprising professionals conforming to global standards through value based quality education andtraining.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
--- Content provided by FirstRanker.com ---
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
--- Content provided by FirstRanker.com ---
needs.? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
--- Content provided by FirstRanker.com ---
industry by continuous assessment and training.VISION
--- Content provided by FirstRanker.com ---
MISSIONVISION
MISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
--- Content provided by FirstRanker.com ---
1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
--- Content provided by FirstRanker.com ---
2. Core CompetenceTo train the students to meet the needs of core industry with an attitude of learning new
technologies.
3. Breadth
--- Content provided by FirstRanker.com ---
To provide relevant training and experience to bridge the gap between theory and practice whichenable them to find solutions to problems in industry and research that contributes to the overall
development of society.
4. Professionalism
--- Content provided by FirstRanker.com ---
To inculcate professional and effective communication skills to the students to make them lead ateam and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
5. Lifelong Learning/Ethics
--- Content provided by FirstRanker.com ---
To practice ethical and professional responsibilities in the organization and society withcommitment and lifelong learning needed for successful professional career.
--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM OUTCOMES (POs)
--- Content provided by FirstRanker.com ---
a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
--- Content provided by FirstRanker.com ---
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment toanalyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
--- Content provided by FirstRanker.com ---
will be aware of contemporary issues.j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
SYLLABUS
--- Content provided by FirstRanker.com ---
Objectives:
The student should be made to:
? Understand the various logic gates.
? Be familiar with various combinational circuits.
--- Content provided by FirstRanker.com ---
? Understand the various components used in the design of digital computers.? Be exposed to sequential circuits
? Learn to use HDL
List of experiments:
1. Verification of Boolean Theorems using basic gates.
--- Content provided by FirstRanker.com ---
2. Design and implementation of combinational circuits using basic gates for arbitraryfunctions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
--- Content provided by FirstRanker.com ---
c. Magnitude Comparatord. Application using multiplexers
4. Design and implementation of sequential circuits:
a. Shift ?registers
b. Synchronous and asynchronous counters
--- Content provided by FirstRanker.com ---
5. Coding combinational / sequential circuits using HDL.6. Design and implementation of a simple digital system (Mini Project).
Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
--- Content provided by FirstRanker.com ---
? Design and Implement combinational and sequential circuits.? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Content
--- Content provided by FirstRanker.com ---
Sl.No. Name of the Experiment Page No.
1.
Verification of Boolean Theorems using Digital Logic Gates
2.
--- Content provided by FirstRanker.com ---
Design and Implementation of Combinational Circuits using Basic Gates for ArbitraryFunctions, Code Converters
3.
Implementation of half adder and full adder
--- Content provided by FirstRanker.com ---
4.Implementation of half subtractor and full subtractor
5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
--- Content provided by FirstRanker.com ---
6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
--- Content provided by FirstRanker.com ---
7.Design and Implementation of Magnitude Comparator.
8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
--- Content provided by FirstRanker.com ---
Design and Implementation of Shift Registers.10.
Design and Implementation of Synchronous and Asynchronous Counters.
11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
--- Content provided by FirstRanker.com ---
HDL Software Required).12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
--- Content provided by FirstRanker.com ---
7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.1: STUDY OF BASIC GATES
Aim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
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7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
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more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known asuniversal gates. Basic gates form these gates.
AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
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low.OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
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A NOT gate is the physical realization of the complementation operation. The NOT gate iscalled an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
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NOR gateThe NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
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similar to OR gate but excludes the combination of both A and B being equal to one. The exclusiveOR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Procedure:
1. Connections are given as per the circuit diagram.
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2. For all the IC?s 7th
pin is grounded and 14
th
pin is given +5 supply.
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3. Apply the inputs and verify the truth table for all gates.Result:
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The truth tables of all the basic logic gates were verified.Outcome:
At the completion of an experiment student will able to verify the truth
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table of all basic gates--- Content provided by FirstRanker.com ---
1. List out the basic gate.2. Mention the universal gate.
3. How many gates presented in IC 7408?
4. What is IC?
5. What are the applications of gates?
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6. Write the truth table of AND gate.7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
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11. Write the truth table of EX- OR gate.12. What are the classifications of IC?
13. What are types of linear integrated circuit?
14. What is meant by etching?
15. What are the advantages of IC?
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16. Write the truth table of EX- NOR gate.Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.2:
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VERIFICATION OF BOOLEAN THEOREMS USING LOGICGATES
Aim: To verification of Boolean theorems using logic gates
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 3
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7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
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BASIC Boolean Laws
1. Commutative Law
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The binary operator OR, AND is said to be commutative if,1. A+B = B+A
2. A.B=B.A
2. Associative Law
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The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
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3. Distributive LawThe binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
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4. Absorption Law
1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
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1. A+A = A2. A.A = A
6. Complementary Law
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1. A+A' = 12. A.A' = 0
7. De Morgan ?s Theorem
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1. The complement of the sum is equal to the sum of the product of the individualcomplements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design
1. Absorption Law
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A+AB = A--- Content provided by FirstRanker.com ---
2. Involution (or) Double complement Law
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A = A--- Content provided by FirstRanker.com ---
3. Idempotent Law
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1. A+A = A
2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
A+B = A.B
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5. Distributive Law
A+(B.C) = (A+B).(A+C)
Procedure:
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1. Obtain the required IC along with the Digital trainer kit.2. Connect zero volts to GND pin and +5 volts to V
cc
.
3. Apply the inputs to the respective input pins.
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4. Verify the output with the truth table.Result:
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Thus the above stated Boolean laws are verified.Outcome:
At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?
2. What is associative law?
3. What is mean by compliment gate?
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4. Explain the basic laws in digital electronics5. What is double complement?
Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.3: HALF ADDER AND FULL ADDERAim:
To design and verify the truth table of the Half Adder & Full Adder circuits
Apparatus required:
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S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
0 + 0 = 0
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0 + 1 = 1
1 + 0 = 1
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1 + 1 = 0 (with 1 as carry)The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
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Half adder:A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
Full adder:
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A combinational circuit which performs the arithmetic sum of three input bits is called full adder. Thethree input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
From the truth table, the expression for sum and carry bits of the output can be obtained as,
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SUM = A?B?C + A?BC? + AB?C? + ABCCARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half Adder
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Truth table:--- Content provided by FirstRanker.com ---
From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
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S = A BCarry, C = A . B
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Circuit diagram:--- Content provided by FirstRanker.com ---
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Full adder
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Truth table:Sl.No. Input Output
A B C S C
1. 0 0 0 0 0
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2. 0 0 1 1 03. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
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7. 1 1 0 0 18. 1 1 1 1 1
Sl.No. Input Output
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A B S C1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:--- Content provided by FirstRanker.com ---
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CARRY = AB + AC + BC
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Logic Diagram:
FirstRanker.com - FirstRanker's Choice
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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
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CS8382 DIGITAL SYSTEMS LABORATORY
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Name : _______________________________________
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Register No : _______________________________________Section : _______________________________________
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LABORATORY MANUAL
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2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
training.
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? To provide competent technical manpower capable of meeting requirements of the industry
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? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
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heart and soulDEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
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To provide candidates with knowledge and skill in the field of Electrical and ElectronicsEngineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
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? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
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professional ethical code.? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
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VISION
MISSION
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VISIONMISSION
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3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
1. Fundamentals
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To provide students with a solid foundation in mathematics, science and fundamentals ofengineering enabling them to solve complex problems in order to develop real time applications.
2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
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technologies.3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
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development of society.4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
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professional ethics at all strategies.5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM OUTCOMES (POs)a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
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c. Graduates will be able to design and conduct experiments, analyze and interpret data.d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
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g. Graduates will demonstrate knowledge of professional and ethical responsibilities.h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
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k. Graduate who can participate and succeed in competitive examinations.--- Content provided by FirstRanker.com ---
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CS8381 DIGITAL SYSTEMS LABORATORY5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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SYLLABUS
Objectives:
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The student should be made to:? Understand the various logic gates.
? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
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? Learn to use HDLList of experiments:
1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
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3. Design and implementation of combinational circuits using MSI devices:a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
c. Magnitude Comparator
d. Application using multiplexers
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4. Design and implementation of sequential circuits:a. Shift ?registers
b. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
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Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
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? Design the different functional units in a digital computer system.? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Content
Sl.No. Name of the Experiment Page No.
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1.Verification of Boolean Theorems using Digital Logic Gates
2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
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3.
Implementation of half adder and full adder
4.
Implementation of half subtractor and full subtractor
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5.Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
6.
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Design and Implementation of Parity Generator / Checker using Basic Gates and MSIDevices
7.
Design and Implementation of Magnitude Comparator.
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8.Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
Design and Implementation of Shift Registers.
10.
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Design and Implementation of Synchronous and Asynchronous Counters.11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
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12.Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.1: STUDY OF BASIC GATES
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Aim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. NAND gate IC 7400 1
6. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
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AND gateThe AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
low.
OR gate
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The OR gate performs a logical addition commonly known as OR function. The output ishigh when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
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NAND gateThe NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
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output is low when one or both inputs are high.EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
EXOR Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
th
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pin is grounded and 14th
pin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
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Result:
The truth tables of all the basic logic gates were verified.
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Outcome:At the completion of an experiment student will able to verify the truth
table of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
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3. How many gates presented in IC 7408?4. What is IC?
5. What are the applications of gates?
6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
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8. Write the truth table of NOT gate.9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
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13. What are types of linear integrated circuit?14. What is meant by etching?
15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.2:
VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gates
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. NAND gate IC 7400 1
6. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
BASIC Boolean Laws
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1. Commutative Law
The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
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2. A.B=B.A2. Associative Law
The binary operator OR, AND is said to be associative if,
--- Content provided by FirstRanker.com ---
1. A+(B+C) = (A+B)+C2. A.(B.C) = (A.B).C
3. Distributive Law
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The binary operator OR, AND is said to be distributive if,1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
4. Absorption Law
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1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
1. A+A = A
2. A.A = A
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6. Complementary Law
1. A+A' = 1
2. A.A' = 0
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7. De Morgan ?s Theorem
1. The complement of the sum is equal to the sum of the product of the individual
complements.
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A+B = A.B2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design1. Absorption Law
A+AB = A
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2. Involution (or) Double complement Law
A = A
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3. Idempotent Law
1. A+A = A
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2. A.A = A
--- Content provided by FirstRanker.com ---
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:004. Demorgan ?s Law
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A+B = A.B
5. Distributive Law
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A+(B.C) = (A+B).(A+C)Procedure:
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
--- Content provided by FirstRanker.com ---
cc.
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
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Result:
Thus the above stated Boolean laws are verified.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to know the basic laws with their truth table.
--- Content provided by FirstRanker.com ---
1. What is Demorgan?s law?2. What is associative law?
3. What is mean by compliment gate?
4. Explain the basic laws in digital electronics
5. What is double complement?
--- Content provided by FirstRanker.com ---
Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
--- Content provided by FirstRanker.com ---
To design and verify the truth table of the Half Adder & Full Adder circuitsApparatus required:
S. No. Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
--- Content provided by FirstRanker.com ---
6. Connecting wires As requiredTheory:
The most basic arithmetic operation is the addition of two binary digits. There are four
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possible elementary operations, namely,0 + 0 = 0
0 + 1 = 1
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1 + 0 = 1
1 + 1 = 0 (with 1 as carry)
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The first three operations produce a sum of whose length is one digit, but when the last operation isperformed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
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designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.Full adder:
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
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with two half adders and one OR gate.From the truth table, the expression for sum and carry bits of the output can be obtained as,
SUM = A?B?C + A?BC? + AB?C? + ABC
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CARRY = A?BC + AB?C + ABC? +ABC16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half Adder
Truth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
S = A B
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Carry, C = A . BCircuit diagram:
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Full adder
Truth table:
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Sl.No. Input OutputA B C S C
1. 0 0 0 0 0
2. 0 0 1 1 0
3. 0 1 0 1 0
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4. 0 1 1 0 15. 1 0 0 1 0
6. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input Output
A B S C
1. 0 0 0 0
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2. 0 1 1 03. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Sum:--- Content provided by FirstRanker.com ---
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B CCarry:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
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CARRY = AB + AC + BC
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Logic Diagram:18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections are given as per the circuit diagrams.
--- Content provided by FirstRanker.com ---
2. For all the IC?s 7th
pin is grounded and 14
th
pin is given +5 V supply.
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3. Apply the inputs and verify the truth table for the half adder and full adder circuits.Result:
The design of the half adder and full adder circuits was done and their truth tables were verified.
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Outcome:At the completion of an experiment student will able to design the half adder circuit and the
full adder circuit.
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FirstRanker.com - FirstRanker's Choice1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
III SEMESTER - R 2017
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
Section : _______________________________________
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LABORATORY MANUAL
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2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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is committed to provide highly disciplined, conscientious and
--- Content provided by FirstRanker.com ---
enterprising professionals conforming to global standards through value based quality education andtraining.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
--- Content provided by FirstRanker.com ---
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
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DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
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needs.? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
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industry by continuous assessment and training.VISION
--- Content provided by FirstRanker.com ---
MISSIONVISION
MISSION
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3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
--- Content provided by FirstRanker.com ---
1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
--- Content provided by FirstRanker.com ---
2. Core CompetenceTo train the students to meet the needs of core industry with an attitude of learning new
technologies.
3. Breadth
--- Content provided by FirstRanker.com ---
To provide relevant training and experience to bridge the gap between theory and practice whichenable them to find solutions to problems in industry and research that contributes to the overall
development of society.
4. Professionalism
--- Content provided by FirstRanker.com ---
To inculcate professional and effective communication skills to the students to make them lead ateam and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
5. Lifelong Learning/Ethics
--- Content provided by FirstRanker.com ---
To practice ethical and professional responsibilities in the organization and society withcommitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
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f. Graduates will demonstrate skills to use modern engineering tools, software and equipment toanalyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
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will be aware of contemporary issues.j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
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--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
SYLLABUS
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Objectives:
The student should be made to:
? Understand the various logic gates.
? Be familiar with various combinational circuits.
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? Understand the various components used in the design of digital computers.? Be exposed to sequential circuits
? Learn to use HDL
List of experiments:
1. Verification of Boolean Theorems using basic gates.
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2. Design and implementation of combinational circuits using basic gates for arbitraryfunctions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
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c. Magnitude Comparatord. Application using multiplexers
4. Design and implementation of sequential circuits:
a. Shift ?registers
b. Synchronous and asynchronous counters
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5. Coding combinational / sequential circuits using HDL.6. Design and implementation of a simple digital system (Mini Project).
Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
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? Design and Implement combinational and sequential circuits.? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Content
--- Content provided by FirstRanker.com ---
Sl.No. Name of the Experiment Page No.
1.
Verification of Boolean Theorems using Digital Logic Gates
2.
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Design and Implementation of Combinational Circuits using Basic Gates for ArbitraryFunctions, Code Converters
3.
Implementation of half adder and full adder
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4.Implementation of half subtractor and full subtractor
5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
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6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
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7.Design and Implementation of Magnitude Comparator.
8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
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Design and Implementation of Shift Registers.10.
Design and Implementation of Synchronous and Asynchronous Counters.
11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
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HDL Software Required).12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.1: STUDY OF BASIC GATES
Aim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
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7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
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more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known asuniversal gates. Basic gates form these gates.
AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
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low.OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
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A NOT gate is the physical realization of the complementation operation. The NOT gate iscalled an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
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NOR gateThe NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
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similar to OR gate but excludes the combination of both A and B being equal to one. The exclusiveOR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Procedure:
1. Connections are given as per the circuit diagram.
--- Content provided by FirstRanker.com ---
2. For all the IC?s 7th
pin is grounded and 14
th
pin is given +5 supply.
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3. Apply the inputs and verify the truth table for all gates.Result:
--- Content provided by FirstRanker.com ---
The truth tables of all the basic logic gates were verified.Outcome:
At the completion of an experiment student will able to verify the truth
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table of all basic gates--- Content provided by FirstRanker.com ---
1. List out the basic gate.2. Mention the universal gate.
3. How many gates presented in IC 7408?
4. What is IC?
5. What are the applications of gates?
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6. Write the truth table of AND gate.7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
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11. Write the truth table of EX- OR gate.12. What are the classifications of IC?
13. What are types of linear integrated circuit?
14. What is meant by etching?
15. What are the advantages of IC?
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16. Write the truth table of EX- NOR gate.Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.2:
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VERIFICATION OF BOOLEAN THEOREMS USING LOGICGATES
Aim: To verification of Boolean theorems using logic gates
--- Content provided by FirstRanker.com ---
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
--- Content provided by FirstRanker.com ---
2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 3
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7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
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BASIC Boolean Laws
1. Commutative Law
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The binary operator OR, AND is said to be commutative if,1. A+B = B+A
2. A.B=B.A
2. Associative Law
--- Content provided by FirstRanker.com ---
The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
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3. Distributive LawThe binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
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4. Absorption Law
1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
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1. A+A = A2. A.A = A
6. Complementary Law
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1. A+A' = 12. A.A' = 0
7. De Morgan ?s Theorem
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1. The complement of the sum is equal to the sum of the product of the individualcomplements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design
1. Absorption Law
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A+AB = A--- Content provided by FirstRanker.com ---
2. Involution (or) Double complement Law
--- Content provided by FirstRanker.com ---
A = A--- Content provided by FirstRanker.com ---
3. Idempotent Law
--- Content provided by FirstRanker.com ---
1. A+A = A
2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
4. Demorgan ?s Law
A+B = A.B
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5. Distributive Law
A+(B.C) = (A+B).(A+C)
Procedure:
--- Content provided by FirstRanker.com ---
1. Obtain the required IC along with the Digital trainer kit.2. Connect zero volts to GND pin and +5 volts to V
cc
.
3. Apply the inputs to the respective input pins.
--- Content provided by FirstRanker.com ---
4. Verify the output with the truth table.Result:
--- Content provided by FirstRanker.com ---
Thus the above stated Boolean laws are verified.Outcome:
At the completion of an experiment student will able to know the basic laws with their truth table.
--- Content provided by FirstRanker.com ---
1. What is Demorgan?s law?
2. What is associative law?
3. What is mean by compliment gate?
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4. Explain the basic laws in digital electronics5. What is double complement?
Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.3: HALF ADDER AND FULL ADDERAim:
To design and verify the truth table of the Half Adder & Full Adder circuits
Apparatus required:
--- Content provided by FirstRanker.com ---
S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
--- Content provided by FirstRanker.com ---
4. NOT gate IC 7404 15. EX-OR gate IC 7486 1
6. Connecting wires As required
--- Content provided by FirstRanker.com ---
Theory:The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
0 + 0 = 0
--- Content provided by FirstRanker.com ---
0 + 1 = 1
1 + 0 = 1
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1 + 1 = 0 (with 1 as carry)The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
--- Content provided by FirstRanker.com ---
Half adder:A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
Full adder:
--- Content provided by FirstRanker.com ---
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. Thethree input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
From the truth table, the expression for sum and carry bits of the output can be obtained as,
--- Content provided by FirstRanker.com ---
SUM = A?B?C + A?BC? + AB?C? + ABCCARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half Adder
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Truth table:--- Content provided by FirstRanker.com ---
From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
--- Content provided by FirstRanker.com ---
S = A BCarry, C = A . B
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Circuit diagram:--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
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Full adder
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Truth table:Sl.No. Input Output
A B C S C
1. 0 0 0 0 0
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2. 0 0 1 1 03. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
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7. 1 1 0 0 18. 1 1 1 1 1
Sl.No. Input Output
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A B S C1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,Sum:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CARRY = AB + AC + BC
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Logic Diagram:
--- Content provided by FirstRanker.com ---
18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
--- Content provided by FirstRanker.com ---
1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
th
pin is grounded and 14
--- Content provided by FirstRanker.com ---
thpin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
Result:
--- Content provided by FirstRanker.com ---
The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
At the completion of an experiment student will able to design the half adder circuit and the
--- Content provided by FirstRanker.com ---
full adder circuit.--- Content provided by FirstRanker.com ---
19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
Aim:
--- Content provided by FirstRanker.com ---
To design and verify the truth table of the half subtractor & full subtractor circuitsApparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
--- Content provided by FirstRanker.com ---
2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
--- Content provided by FirstRanker.com ---
Theory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
subtrahend bit, hence 1 is borrowed.
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Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
--- Content provided by FirstRanker.com ---
Full subtractor:A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
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From the truth table the expression for difference and borrow bits of the output can be obtainedas,
Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
--- Content provided by FirstRanker.com ---
Borrow, BORR = A?BC + AB?C + ABC? +ABC--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
FirstRanker.com - FirstRanker's Choice
--- Content provided by FirstRanker.com ---
1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
?DEPARTMENT OF
--- Content provided by FirstRanker.com ---
COMPUTER SCIENCE ENGINEERINGIII SEMESTER - R 2017
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
Section : _______________________________________
--- Content provided by FirstRanker.com ---
LABORATORY MANUAL
--- Content provided by FirstRanker.com ---
2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious andenterprising professionals conforming to global standards through value based quality education and
training.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
--- Content provided by FirstRanker.com ---
levels? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
--- Content provided by FirstRanker.com ---
Electrical and Electronics Engineers.--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?sneeds.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
--- Content provided by FirstRanker.com ---
concepts with strongly supported laboratory and prepare them to meet the global needs of theindustry by continuous assessment and training.
VISION
--- Content provided by FirstRanker.com ---
MISSION
VISION
--- Content provided by FirstRanker.com ---
MISSION--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
--- Content provided by FirstRanker.com ---
1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
--- Content provided by FirstRanker.com ---
2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
technologies.
--- Content provided by FirstRanker.com ---
3. BreadthTo provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
development of society.
--- Content provided by FirstRanker.com ---
4. ProfessionalismTo inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
--- Content provided by FirstRanker.com ---
5. Lifelong Learning/EthicsTo practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PROGRAM OUTCOMES (POs)
--- Content provided by FirstRanker.com ---
a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
--- Content provided by FirstRanker.com ---
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
--- Content provided by FirstRanker.com ---
i. Graduates will show the understanding of impact of engineering solutions on the society and alsowill be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
SYLLABUSObjectives:
The student should be made to:
? Understand the various logic gates.
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? Be familiar with various combinational circuits.? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
? Learn to use HDL
List of experiments:
--- Content provided by FirstRanker.com ---
1. Verification of Boolean Theorems using basic gates.2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
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b. Parity generator / checkerc. Magnitude Comparator
d. Application using multiplexers
4. Design and implementation of sequential circuits:
a. Shift ?registers
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b. Synchronous and asynchronous counters5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
Course Outcomes:
--- Content provided by FirstRanker.com ---
? Use Boolean simplification techniques to design a combinational hardware circuit.? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
ContentSl.No. Name of the Experiment Page No.
1.
Verification of Boolean Theorems using Digital Logic Gates
--- Content provided by FirstRanker.com ---
2.Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
3.
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Implementation of half adder and full adder4.
Implementation of half subtractor and full subtractor
5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
--- Content provided by FirstRanker.com ---
MSI Devices6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
--- Content provided by FirstRanker.com ---
7.
Design and Implementation of Magnitude Comparator.
8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
--- Content provided by FirstRanker.com ---
9.Design and Implementation of Shift Registers.
10.
Design and Implementation of Synchronous and Asynchronous Counters.
11.
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Simulation of Combinational Circuits using Hardware Description Language (VHDL / VerilogHDL Software Required).
12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.1: STUDY OF BASIC GATES
Aim:
--- Content provided by FirstRanker.com ---
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gatesApparatus required:
Sl.No Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
--- Content provided by FirstRanker.com ---
6. NOR gate IC 7402 17. EX-OR gate IC 7486 1
8. Connecting wires As required
Theory:
--- Content provided by FirstRanker.com ---
Circuit that takes the logical decision and the process are called logic gates. Each gate has one ormore input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
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output is high when both the inputs are high. The output is low level when any one of the inputs islow.
OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
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NOT gateA NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
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and any one of the input is low .The output is low level when both inputs are high.NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
EX-OR gate
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An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It issimilar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
AND Gate Symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
OR Gate:
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OR GATE:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
NOT Gate symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
NAND Gate symbol: PIN Diagram:
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NOR Gate:
--- Content provided by FirstRanker.com ---
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
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1. Connections are given as per the circuit diagram.2. For all the IC?s 7
th
pin is grounded and 14
th
--- Content provided by FirstRanker.com ---
pin is given +5 supply.3. Apply the inputs and verify the truth table for all gates.
Result:
--- Content provided by FirstRanker.com ---
The truth tables of all the basic logic gates were verified.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to verify the truthtable of all basic gates
--- Content provided by FirstRanker.com ---
1. List out the basic gate.
2. Mention the universal gate.
3. How many gates presented in IC 7408?
4. What is IC?
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5. What are the applications of gates?6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
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10. Write the truth table of NOR gate.11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
13. What are types of linear integrated circuit?
14. What is meant by etching?
--- Content provided by FirstRanker.com ---
15. What are the advantages of IC?16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.2:
--- Content provided by FirstRanker.com ---
VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
--- Content provided by FirstRanker.com ---
Aim: To verification of Boolean theorems using logic gatesApparatus required:
Sl.No Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
--- Content provided by FirstRanker.com ---
6. NOR gate IC 7402 37. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:BASIC Boolean Laws
1. Commutative Law
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The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A
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2. Associative LawThe binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
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3. Distributive Law
The binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
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2. A.(B+C) = (A.B)+(A.C)4. Absorption Law
1. A+AB = A
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2. A+AB =A+B--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
13 Format No.FirstRanker/stud/LM/34/issue:00/revision:005. Idempotent Law
--- Content provided by FirstRanker.com ---
1. A+A = A
2. A.A = A
6. Complementary Law
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1. A+A' = 1
2. A.A' = 0
7. De Morgan ?s Theorem
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1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
--- Content provided by FirstRanker.com ---
A.B = A+BDesign
1. Absorption Law
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A+AB = A
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2. Involution (or) Double complement Law
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A = A
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3. Idempotent Law1. A+A = A
2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
4. Demorgan ?s Law
A+B = A.B
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5. Distributive Law
A+(B.C) = (A+B).(A+C)
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Procedure:1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
cc
.
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3. Apply the inputs to the respective input pins.4. Verify the output with the truth table.
Result:
--- Content provided by FirstRanker.com ---
Thus the above stated Boolean laws are verified.
Outcome:
At the completion of an experiment student will able to know the basic laws with their truth table.
--- Content provided by FirstRanker.com ---
1. What is Demorgan?s law?
2. What is associative law?
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3. What is mean by compliment gate?4. Explain the basic laws in digital electronics
5. What is double complement?
Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
To design and verify the truth table of the Half Adder & Full Adder circuits
--- Content provided by FirstRanker.com ---
Apparatus required:S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:
The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
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0 + 0 = 00 + 1 = 1
1 + 0 = 1
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1 + 1 = 0 (with 1 as carry)
The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
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significant bit is called the sum.Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
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Full adder:A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
--- Content provided by FirstRanker.com ---
From the truth table, the expression for sum and carry bits of the output can be obtained as,SUM = A?B?C + A?BC? + AB?C? + ABC
CARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Half AdderTruth table:
--- Content provided by FirstRanker.com ---
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,S = A B
Carry, C = A . B
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Circuit diagram:
--- Content provided by FirstRanker.com ---
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Full adderTruth table:
Sl.No. Input Output
A B C S C
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1. 0 0 0 0 02. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
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6. 1 0 1 0 17. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input OutputA B S C
1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
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4. 1 1 1 117 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Sum:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CARRY = AB + AC + BCLogic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Procedure:1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
th
--- Content provided by FirstRanker.com ---
pin is grounded and 14th
pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
--- Content provided by FirstRanker.com ---
Result:The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to design the half adder circuit and thefull adder circuit.
--- Content provided by FirstRanker.com ---
19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
--- Content provided by FirstRanker.com ---
Aim:To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
--- Content provided by FirstRanker.com ---
6. Connecting wires As requiredTheory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
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subtrahend bit, hence 1 is borrowed.Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
--- Content provided by FirstRanker.com ---
difference and borrow bits.Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
--- Content provided by FirstRanker.com ---
From the truth table the expression for difference and borrow bits of the output can be obtained
as,
Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
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Borrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Half subtractor
Truth table:
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Sl.No. Input Output
A B Difference Borrow
1. 0 0 0 0
2. 0 1 1 1
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3. 1 0 1 04. 1 1 0 0
From the truth table the expression for difference and borrow bits of the output can be obtained as,
--- Content provided by FirstRanker.com ---
Difference, DIFF = A BBorrow, BORR = A?. B
Logic diagram:
--- Content provided by FirstRanker.com ---
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2. Full subtractor
Truth table:
--- Content provided by FirstRanker.com ---
Sl.No.Input Output
A B C Difference Borrow
1. 0 0 0 0 0
2. 0 0 1 1 1
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3. 0 1 0 1 14. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
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8. 1 1 1 1 1FirstRanker.com - FirstRanker's Choice
--- Content provided by FirstRanker.com ---
1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
?
--- Content provided by FirstRanker.com ---
DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
--- Content provided by FirstRanker.com ---
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
Name : _______________________________________
--- Content provided by FirstRanker.com ---
Register No : _______________________________________Section : _______________________________________
--- Content provided by FirstRanker.com ---
LABORATORY MANUAL
--- Content provided by FirstRanker.com ---
2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
training.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
--- Content provided by FirstRanker.com ---
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
--- Content provided by FirstRanker.com ---
heart and soulDEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and ElectronicsEngineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
--- Content provided by FirstRanker.com ---
professional ethical code.? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
--- Content provided by FirstRanker.com ---
VISION
MISSION
--- Content provided by FirstRanker.com ---
VISIONMISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
1. Fundamentals
--- Content provided by FirstRanker.com ---
To provide students with a solid foundation in mathematics, science and fundamentals ofengineering enabling them to solve complex problems in order to develop real time applications.
2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
--- Content provided by FirstRanker.com ---
technologies.3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
--- Content provided by FirstRanker.com ---
development of society.4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
--- Content provided by FirstRanker.com ---
professional ethics at all strategies.5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM OUTCOMES (POs)a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
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c. Graduates will be able to design and conduct experiments, analyze and interpret data.d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
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g. Graduates will demonstrate knowledge of professional and ethical responsibilities.h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
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k. Graduate who can participate and succeed in competitive examinations.--- Content provided by FirstRanker.com ---
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CS8381 DIGITAL SYSTEMS LABORATORY5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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SYLLABUS
Objectives:
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The student should be made to:? Understand the various logic gates.
? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
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? Learn to use HDLList of experiments:
1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
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3. Design and implementation of combinational circuits using MSI devices:a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
c. Magnitude Comparator
d. Application using multiplexers
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4. Design and implementation of sequential circuits:a. Shift ?registers
b. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
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Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
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? Design the different functional units in a digital computer system.? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Content
Sl.No. Name of the Experiment Page No.
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1.Verification of Boolean Theorems using Digital Logic Gates
2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
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3.
Implementation of half adder and full adder
4.
Implementation of half subtractor and full subtractor
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5.Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
6.
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Design and Implementation of Parity Generator / Checker using Basic Gates and MSIDevices
7.
Design and Implementation of Magnitude Comparator.
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8.Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
Design and Implementation of Shift Registers.
10.
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Design and Implementation of Synchronous and Asynchronous Counters.11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
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12.Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.1: STUDY OF BASIC GATES
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Aim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. NAND gate IC 7400 1
6. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
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AND gateThe AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
low.
OR gate
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The OR gate performs a logical addition commonly known as OR function. The output ishigh when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
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NAND gateThe NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
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output is low when one or both inputs are high.EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
EXOR Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
th
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pin is grounded and 14th
pin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
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Result:
The truth tables of all the basic logic gates were verified.
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Outcome:At the completion of an experiment student will able to verify the truth
table of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
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3. How many gates presented in IC 7408?4. What is IC?
5. What are the applications of gates?
6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
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8. Write the truth table of NOT gate.9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
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13. What are types of linear integrated circuit?14. What is meant by etching?
15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.2:
VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gates
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. NAND gate IC 7400 1
6. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
BASIC Boolean Laws
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1. Commutative Law
The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
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2. A.B=B.A2. Associative Law
The binary operator OR, AND is said to be associative if,
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1. A+(B+C) = (A+B)+C2. A.(B.C) = (A.B).C
3. Distributive Law
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The binary operator OR, AND is said to be distributive if,1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
4. Absorption Law
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1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
1. A+A = A
2. A.A = A
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6. Complementary Law
1. A+A' = 1
2. A.A' = 0
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7. De Morgan ?s Theorem
1. The complement of the sum is equal to the sum of the product of the individual
complements.
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A+B = A.B2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design1. Absorption Law
A+AB = A
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2. Involution (or) Double complement Law
A = A
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3. Idempotent Law
1. A+A = A
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2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:004. Demorgan ?s Law
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A+B = A.B
5. Distributive Law
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A+(B.C) = (A+B).(A+C)Procedure:
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
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cc.
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
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Result:
Thus the above stated Boolean laws are verified.
Outcome:
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At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?2. What is associative law?
3. What is mean by compliment gate?
4. Explain the basic laws in digital electronics
5. What is double complement?
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Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
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To design and verify the truth table of the Half Adder & Full Adder circuitsApparatus required:
S. No. Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
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6. Connecting wires As requiredTheory:
The most basic arithmetic operation is the addition of two binary digits. There are four
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possible elementary operations, namely,0 + 0 = 0
0 + 1 = 1
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1 + 0 = 1
1 + 1 = 0 (with 1 as carry)
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The first three operations produce a sum of whose length is one digit, but when the last operation isperformed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
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designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.Full adder:
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
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with two half adders and one OR gate.From the truth table, the expression for sum and carry bits of the output can be obtained as,
SUM = A?B?C + A?BC? + AB?C? + ABC
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CARRY = A?BC + AB?C + ABC? +ABC16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half Adder
Truth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
S = A B
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Carry, C = A . BCircuit diagram:
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Full adder
Truth table:
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Sl.No. Input OutputA B C S C
1. 0 0 0 0 0
2. 0 0 1 1 0
3. 0 1 0 1 0
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4. 0 1 1 0 15. 1 0 0 1 0
6. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input Output
A B S C
1. 0 0 0 0
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2. 0 1 1 03. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Sum:--- Content provided by FirstRanker.com ---
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B CCarry:
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CARRY = AB + AC + BC
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Logic Diagram:18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections are given as per the circuit diagrams.
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2. For all the IC?s 7th
pin is grounded and 14
th
pin is given +5 V supply.
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3. Apply the inputs and verify the truth table for the half adder and full adder circuits.Result:
The design of the half adder and full adder circuits was done and their truth tables were verified.
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Outcome:At the completion of an experiment student will able to design the half adder circuit and the
full adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTORAim:
To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. EX-OR gate IC 7486 1
6. Connecting wires As required
Theory:
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The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bitis subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
subtrahend bit, hence 1 is borrowed.
Half subtractor:
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A combinational circuit which performs the subtraction of two bits is called half subtractor. The inputvariables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
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three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can beimplemented with two half subtractors and one OR gate.
From the truth table the expression for difference and borrow bits of the output can be obtained
as,
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Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
Borrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half subtractor
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Truth table:
Sl.No. Input Output
A B Difference Borrow
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1. 0 0 0 02. 0 1 1 1
3. 1 0 1 0
4. 1 1 0 0
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From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A B
Borrow, BORR = A?. B
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Logic diagram:
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2. Full subtractor
Truth table:
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Sl.No.
Input Output
A B C Difference Borrow
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1. 0 0 0 0 02. 0 0 1 1 1
3. 0 1 0 1 1
4. 0 1 1 0 1
5. 1 0 0 1 0
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6. 1 0 1 0 07. 1 1 0 0 0
8. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
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Borrow--- Content provided by FirstRanker.com ---
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Borrow = A?B + A?C + BC
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Circuit diagram:
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FirstRanker.com - FirstRanker's Choice
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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
?
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DEPARTMENT OFCOMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
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CS8382 DIGITAL SYSTEMS LABORATORY--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
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Section : _______________________________________--- Content provided by FirstRanker.com ---
LABORATORY MANUAL2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
training.
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? To provide competent technical manpower capable of meeting requirements of the industry
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? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at differentlevels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
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DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
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Engineering and thereby produce extremely well trained employable, socially responsible and innovativeElectrical and Electronics Engineers.
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? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
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? To provide highest quality learning environment for the students emphasizing fundamentalconcepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
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VISIONMISSION
VISION
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MISSION
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3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
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engineering enabling them to solve complex problems in order to develop real time applications.2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
technologies.
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3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
development of society.
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4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
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5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
--- Content provided by FirstRanker.com ---
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
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d. Graduates will be able to design a system, component or process as per needs and specifications.e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
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h. Graduates will be able to communicate effectively by both verbal and written form.i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
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CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
SYLLABUS
Objectives:
The student should be made to:
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? Understand the various logic gates.? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
? Learn to use HDL
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List of experiments:1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
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a. 4 ? bit binary adder / subtractorb. Parity generator / checker
c. Magnitude Comparator
d. Application using multiplexers
4. Design and implementation of sequential circuits:
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a. Shift ?registersb. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
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Course Outcomes:? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
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? Design and Implement a simple digital system.--- Content provided by FirstRanker.com ---
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Content
Sl.No. Name of the Experiment Page No.
1.
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Verification of Boolean Theorems using Digital Logic Gates2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
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3.Implementation of half adder and full adder
4.
Implementation of half subtractor and full subtractor
5.
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Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates andMSI Devices
6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
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Devices7.
Design and Implementation of Magnitude Comparator.
8.
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Design and Implementation of Application using Multiplexers / Demultiplexers.9.
Design and Implementation of Shift Registers.
10.
Design and Implementation of Synchronous and Asynchronous Counters.
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11.Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
12.
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Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).--- Content provided by FirstRanker.com ---
7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.1: STUDY OF BASIC GATES
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Aim:To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
--- Content provided by FirstRanker.com ---
5. NAND gate IC 7400 16. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND gate
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The AND gate performs a logical multiplication commonly known as AND function. Theoutput is high when both the inputs are high. The output is low level when any one of the inputs is
low.
OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
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high when any one of the inputs is high. The output is low level when both the inputs are low.NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
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The NAND gate is a contraction of AND-NOT. The output is high when both inputs are lowand any one of the input is low .The output is low level when both inputs are high.
NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
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EX-OR gateAn Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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AND Gate Symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
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OR Gate:--- Content provided by FirstRanker.com ---
OR GATE:--- Content provided by FirstRanker.com ---
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00NAND Gate symbol: PIN Diagram:
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NOR Gate:--- Content provided by FirstRanker.com ---
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
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1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
th
pin is grounded and 14
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thpin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
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Result:The truth tables of all the basic logic gates were verified.
Outcome:
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At the completion of an experiment student will able to verify the truth
table of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
3. How many gates presented in IC 7408?
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4. What is IC?5. What are the applications of gates?
6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
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9. Write the truth table of NAND gate.10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
13. What are types of linear integrated circuit?
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14. What is meant by etching?15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Expt.No.2:VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gates
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
--- Content provided by FirstRanker.com ---
5. NAND gate IC 7400 16. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
BASIC Boolean Laws
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1. Commutative LawThe binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A
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2. Associative Law
The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
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2. A.(B.C) = (A.B).C3. Distributive Law
The binary operator OR, AND is said to be distributive if,
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1. A+(B.C) = (A+B).(A+C)2. A.(B+C) = (A.B)+(A.C)
4. Absorption Law
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1. A+AB = A2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law1. A+A = A
2. A.A = A
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6. Complementary Law1. A+A' = 1
2. A.A' = 0
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7. De Morgan ?s Theorem1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
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2. The complement of the product is equal to the sum of the individual complements.A.B = A+B
Design
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1. Absorption LawA+AB = A
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2. Involution (or) Double complement LawA = A
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3. Idempotent Law
1. A+A = A
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2. A.A = A--- Content provided by FirstRanker.com ---
14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
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A+B = A.B5. Distributive Law
A+(B.C) = (A+B).(A+C)
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Procedure:
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
cc
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.3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
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Result:Thus the above stated Boolean laws are verified.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to know the basic laws with their truth table.1. What is Demorgan?s law?
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2. What is associative law?3. What is mean by compliment gate?
4. Explain the basic laws in digital electronics
5. What is double complement?
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Viva ? Voce--- Content provided by FirstRanker.com ---
15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
To design and verify the truth table of the Half Adder & Full Adder circuits
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Apparatus required:
S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
--- Content provided by FirstRanker.com ---
2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:
The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
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0 + 0 = 0
0 + 1 = 1
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1 + 0 = 11 + 1 = 0 (with 1 as carry)
The first three operations produce a sum of whose length is one digit, but when the last operation is
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performed the sum is two digits. The higher significant bit of this result is called a carry and lowersignificant bit is called the sum.
Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
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Full adder:
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
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From the truth table, the expression for sum and carry bits of the output can be obtained as,
SUM = A?B?C + A?BC? + AB?C? + ABC
CARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Half Adder
Truth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
S = A B
Carry, C = A . B
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Circuit diagram:
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Full adder
Truth table:
Sl.No. Input Output
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A B C S C1. 0 0 0 0 0
2. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
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5. 1 0 0 1 06. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input Output
A B S C
1. 0 0 0 0
2. 0 1 1 0
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3. 1 0 1 04. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:
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CARRY = AB + AC + BC
Logic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Procedure:
1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
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thpin is grounded and 14
th
pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
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Result:
The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to design the half adder circuit and the
full adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
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Aim:
To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
--- Content provided by FirstRanker.com ---
5. EX-OR gate IC 7486 16. Connecting wires As required
Theory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
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is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than thesubtrahend bit, hence 1 is borrowed.
Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
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variables designate the minuend and the subtrahend bit, whereas the output variables produce thedifference and borrow bits.
Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
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implemented with two half subtractors and one OR gate.From the truth table the expression for difference and borrow bits of the output can be obtained
as,
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Difference, DIFF= A?B?C + A?BC? + AB?C? + ABCBorrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half subtractor
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Truth table:Sl.No. Input Output
A B Difference Borrow
1. 0 0 0 0
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2. 0 1 1 13. 1 0 1 0
4. 1 1 0 0
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From the truth table the expression for difference and borrow bits of the output can be obtained as,Difference, DIFF = A B
Borrow, BORR = A?. B
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Logic diagram:--- Content provided by FirstRanker.com ---
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2. Full subtractor
Truth table:
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Sl.No.
Input Output
A B C Difference Borrow
1. 0 0 0 0 0
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2. 0 0 1 1 13. 0 1 0 1 1
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 0
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7. 1 1 0 0 08. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
Borrow
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Borrow = A?B + A?C + BC
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Circuit diagram:--- Content provided by FirstRanker.com ---
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
Aim:
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To design and implement 4-bit adder and subtractor using IC 7483Apparatus required:
Sl.No Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. IC IC 7483 1
3. NOT gate IC 7404 1
4. EX-OR gate IC 7486 1
5. Connecting wires As required
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Theory:
4 BIT Binary adder:
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A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can beconstructed with full adders connected in cascade, with the output carry from each full adder connected to
the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
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0and it ripples through
the full adder to the output carry C
4
.
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4 BIT Binary subtractor:The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
?B? and the corresponding input of full adder. The input carry C
0
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must be equal to 1 when performingsubtraction.
4 BIT Binary adder / subtractor:
The addition and subtraction operation can be combined into one circuit with one common binary
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adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, itbecomes subtractor.
FirstRanker.com - FirstRanker's Choice
--- Content provided by FirstRanker.com ---
1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OFCOMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
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CS8382 DIGITAL SYSTEMS LABORATORY--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
--- Content provided by FirstRanker.com ---
Section : _______________________________________--- Content provided by FirstRanker.com ---
LABORATORY MANUAL2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
training.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
--- Content provided by FirstRanker.com ---
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at differentlevels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
--- Content provided by FirstRanker.com ---
Engineering and thereby produce extremely well trained employable, socially responsible and innovativeElectrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
--- Content provided by FirstRanker.com ---
? To provide highest quality learning environment for the students emphasizing fundamentalconcepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
--- Content provided by FirstRanker.com ---
VISIONMISSION
VISION
--- Content provided by FirstRanker.com ---
MISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
--- Content provided by FirstRanker.com ---
engineering enabling them to solve complex problems in order to develop real time applications.2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
technologies.
--- Content provided by FirstRanker.com ---
3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
development of society.
--- Content provided by FirstRanker.com ---
4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
--- Content provided by FirstRanker.com ---
5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
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d. Graduates will be able to design a system, component or process as per needs and specifications.e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
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h. Graduates will be able to communicate effectively by both verbal and written form.i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
SYLLABUS
Objectives:
The student should be made to:
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? Understand the various logic gates.? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
? Learn to use HDL
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List of experiments:1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
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a. 4 ? bit binary adder / subtractorb. Parity generator / checker
c. Magnitude Comparator
d. Application using multiplexers
4. Design and implementation of sequential circuits:
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a. Shift ?registersb. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
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Course Outcomes:? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
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? Design and Implement a simple digital system.--- Content provided by FirstRanker.com ---
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Content
Sl.No. Name of the Experiment Page No.
1.
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Verification of Boolean Theorems using Digital Logic Gates2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
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3.Implementation of half adder and full adder
4.
Implementation of half subtractor and full subtractor
5.
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Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates andMSI Devices
6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
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Devices7.
Design and Implementation of Magnitude Comparator.
8.
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Design and Implementation of Application using Multiplexers / Demultiplexers.9.
Design and Implementation of Shift Registers.
10.
Design and Implementation of Synchronous and Asynchronous Counters.
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11.Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
12.
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Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).--- Content provided by FirstRanker.com ---
7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.1: STUDY OF BASIC GATES
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Aim:To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
--- Content provided by FirstRanker.com ---
5. NAND gate IC 7400 16. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND gate
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The AND gate performs a logical multiplication commonly known as AND function. Theoutput is high when both the inputs are high. The output is low level when any one of the inputs is
low.
OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
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high when any one of the inputs is high. The output is low level when both the inputs are low.NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
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The NAND gate is a contraction of AND-NOT. The output is high when both inputs are lowand any one of the input is low .The output is low level when both inputs are high.
NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
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EX-OR gateAn Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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AND Gate Symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
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OR Gate:--- Content provided by FirstRanker.com ---
OR GATE:--- Content provided by FirstRanker.com ---
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00NAND Gate symbol: PIN Diagram:
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NOR Gate:--- Content provided by FirstRanker.com ---
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
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1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
th
pin is grounded and 14
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thpin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
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Result:The truth tables of all the basic logic gates were verified.
Outcome:
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At the completion of an experiment student will able to verify the truth
table of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
3. How many gates presented in IC 7408?
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4. What is IC?5. What are the applications of gates?
6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
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9. Write the truth table of NAND gate.10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
13. What are types of linear integrated circuit?
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14. What is meant by etching?15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.2:VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gates
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. NAND gate IC 7400 16. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
BASIC Boolean Laws
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1. Commutative LawThe binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A
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2. Associative Law
The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
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2. A.(B.C) = (A.B).C3. Distributive Law
The binary operator OR, AND is said to be distributive if,
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1. A+(B.C) = (A+B).(A+C)2. A.(B+C) = (A.B)+(A.C)
4. Absorption Law
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1. A+AB = A2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law1. A+A = A
2. A.A = A
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6. Complementary Law1. A+A' = 1
2. A.A' = 0
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7. De Morgan ?s Theorem1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
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2. The complement of the product is equal to the sum of the individual complements.A.B = A+B
Design
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1. Absorption LawA+AB = A
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2. Involution (or) Double complement LawA = A
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3. Idempotent Law
1. A+A = A
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2. A.A = A--- Content provided by FirstRanker.com ---
14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
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A+B = A.B5. Distributive Law
A+(B.C) = (A+B).(A+C)
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Procedure:
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
cc
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.3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
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Result:Thus the above stated Boolean laws are verified.
Outcome:
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At the completion of an experiment student will able to know the basic laws with their truth table.1. What is Demorgan?s law?
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2. What is associative law?3. What is mean by compliment gate?
4. Explain the basic laws in digital electronics
5. What is double complement?
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Viva ? Voce--- Content provided by FirstRanker.com ---
15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
To design and verify the truth table of the Half Adder & Full Adder circuits
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Apparatus required:
S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:
The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
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0 + 0 = 0
0 + 1 = 1
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1 + 0 = 11 + 1 = 0 (with 1 as carry)
The first three operations produce a sum of whose length is one digit, but when the last operation is
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performed the sum is two digits. The higher significant bit of this result is called a carry and lowersignificant bit is called the sum.
Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
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Full adder:
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
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From the truth table, the expression for sum and carry bits of the output can be obtained as,
SUM = A?B?C + A?BC? + AB?C? + ABC
CARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half Adder
Truth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
S = A B
Carry, C = A . B
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Circuit diagram:
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Full adder
Truth table:
Sl.No. Input Output
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A B C S C1. 0 0 0 0 0
2. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
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5. 1 0 0 1 06. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input Output
A B S C
1. 0 0 0 0
2. 0 1 1 0
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3. 1 0 1 04. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:
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CARRY = AB + AC + BC
Logic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
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thpin is grounded and 14
th
pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
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Result:
The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
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At the completion of an experiment student will able to design the half adder circuit and the
full adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
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Aim:
To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. EX-OR gate IC 7486 16. Connecting wires As required
Theory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
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is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than thesubtrahend bit, hence 1 is borrowed.
Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
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variables designate the minuend and the subtrahend bit, whereas the output variables produce thedifference and borrow bits.
Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
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implemented with two half subtractors and one OR gate.From the truth table the expression for difference and borrow bits of the output can be obtained
as,
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Difference, DIFF= A?B?C + A?BC? + AB?C? + ABCBorrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half subtractor
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Truth table:Sl.No. Input Output
A B Difference Borrow
1. 0 0 0 0
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2. 0 1 1 13. 1 0 1 0
4. 1 1 0 0
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From the truth table the expression for difference and borrow bits of the output can be obtained as,Difference, DIFF = A B
Borrow, BORR = A?. B
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Logic diagram:--- Content provided by FirstRanker.com ---
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2. Full subtractor
Truth table:
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Sl.No.
Input Output
A B C Difference Borrow
1. 0 0 0 0 0
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2. 0 0 1 1 13. 0 1 0 1 1
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 0
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7. 1 1 0 0 08. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
Borrow
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Borrow = A?B + A?C + BC
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Circuit diagram:--- Content provided by FirstRanker.com ---
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
Aim:
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To design and implement 4-bit adder and subtractor using IC 7483Apparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. IC IC 7483 1
3. NOT gate IC 7404 1
4. EX-OR gate IC 7486 1
5. Connecting wires As required
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Theory:
4 BIT Binary adder:
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A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can beconstructed with full adders connected in cascade, with the output carry from each full adder connected to
the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
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0and it ripples through
the full adder to the output carry C
4
.
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4 BIT Binary subtractor:The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
?B? and the corresponding input of full adder. The input carry C
0
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must be equal to 1 when performingsubtraction.
4 BIT Binary adder / subtractor:
The addition and subtraction operation can be combined into one circuit with one common binary
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adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, itbecomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PIN Diagram for IC 7483:
Logic Diagram: 4-Bit Binary Diagram:
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Logic diagram: 4-Bit Binary Subtractor:
4-Bit Binary Adder /Subtractor:
FirstRanker.com - FirstRanker's Choice
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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
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III SEMESTER - R 2017CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________Register No : _______________________________________
Section : _______________________________________
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LABORATORY MANUAL
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2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
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training.--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
--- Content provided by FirstRanker.com ---
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag onheart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
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? To produce electrical engineers of high calibre, conscious of the universal moral values adhering toprofessional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
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VISION
MISSION
--- Content provided by FirstRanker.com ---
VISION
MISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
--- Content provided by FirstRanker.com ---
1. FundamentalsTo provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
2. Core Competence
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To train the students to meet the needs of core industry with an attitude of learning newtechnologies.
3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
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enable them to find solutions to problems in industry and research that contributes to the overalldevelopment of society.
4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
--- Content provided by FirstRanker.com ---
team and stand as a good decision maker to manage any constraint environment with goodprofessional ethics at all strategies.
5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
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commitment and lifelong learning needed for successful professional career.--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM OUTCOMES (POs)
a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
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b. Graduates will be able to identify, formulate and solve electrical engineering problems.c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
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analyze problems.g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
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j. Graduates will develop confidence for self-education and ability for lifelong learning.k. Graduate who can participate and succeed in competitive examinations.
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CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00SYLLABUS
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Objectives:The student should be made to:
? Understand the various logic gates.
? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
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? Be exposed to sequential circuits? Learn to use HDL
List of experiments:
1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
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functions, code converters.3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
c. Magnitude Comparator
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d. Application using multiplexers4. Design and implementation of sequential circuits:
a. Shift ?registers
b. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
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6. Design and implementation of a simple digital system (Mini Project).Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
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? Analyze a given digital circuit ? combinational and sequential.? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Content
--- Content provided by FirstRanker.com ---
Sl.No. Name of the Experiment Page No.1.
Verification of Boolean Theorems using Digital Logic Gates
2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
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Functions, Code Converters3.
Implementation of half adder and full adder
4.
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Implementation of half subtractor and full subtractor5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
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6.Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
7.
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Design and Implementation of Magnitude Comparator.8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
Design and Implementation of Shift Registers.
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10.Design and Implementation of Synchronous and Asynchronous Counters.
11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
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12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.1: STUDY OF BASIC GATESAim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
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8. Connecting wires As requiredTheory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
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universal gates. Basic gates form these gates.AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
low.
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OR gateThe OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
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called an inverter. The output is high when the input is low. The output is low when the input is high.NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
NOR gate
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The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. Theoutput is low when one or both inputs are high.
EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
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OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NAND Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
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thpin is grounded and 14
th
pin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
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Result:
The truth tables of all the basic logic gates were verified.
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Outcome:
At the completion of an experiment student will able to verify the truth
table of all basic gates
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1. List out the basic gate.
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2. Mention the universal gate.3. How many gates presented in IC 7408?
4. What is IC?
5. What are the applications of gates?
6. Write the truth table of AND gate.
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7. Write the truth table of OR gate.8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
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12. What are the classifications of IC?13. What are types of linear integrated circuit?
14. What is meant by etching?
15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
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Viva ? Voce--- Content provided by FirstRanker.com ---
12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.2:
VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
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GATESAim: To verification of Boolean theorems using logic gates
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
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8. Connecting wires As requiredTheory:
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BASIC Boolean Laws1. Commutative Law
The binary operator OR, AND is said to be commutative if,
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1. A+B = B+A2. A.B=B.A
2. Associative Law
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The binary operator OR, AND is said to be associative if,1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
3. Distributive Law
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The binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
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4. Absorption Law1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
1. A+A = A
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2. A.A = A6. Complementary Law
1. A+A' = 1
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2. A.A' = 07. De Morgan ?s Theorem
1. The complement of the sum is equal to the sum of the product of the individual
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complements.A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design
1. Absorption Law
A+AB = A
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2. Involution (or) Double complement Law
A = A
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3. Idempotent Law
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1. A+A = A2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s LawA+B = A.B
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5. Distributive LawA+(B.C) = (A+B).(A+C)
Procedure:
1. Obtain the required IC along with the Digital trainer kit.
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2. Connect zero volts to GND pin and +5 volts to Vcc
.
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
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Result:
Thus the above stated Boolean laws are verified.
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Outcome:At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?
2. What is associative law?
3. What is mean by compliment gate?
4. Explain the basic laws in digital electronics
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5. What is double complement?Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.3: HALF ADDER AND FULL ADDER
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Aim:To design and verify the truth table of the Half Adder & Full Adder circuits
Apparatus required:
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S. No. Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. EX-OR gate IC 7486 16. Connecting wires As required
Theory:
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The most basic arithmetic operation is the addition of two binary digits. There are fourpossible elementary operations, namely,
0 + 0 = 0
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0 + 1 = 11 + 0 = 1
1 + 1 = 0 (with 1 as carry)
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The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
Half adder:
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A combinational circuit which performs the addition of two bits is called half adder. The input variablesdesignate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
Full adder:
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
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three input bits include two significant bits and a previous carry bit. A full adder circuit can be implementedwith two half adders and one OR gate.
From the truth table, the expression for sum and carry bits of the output can be obtained as,
SUM = A?B?C + A?BC? + AB?C? + ABC
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CARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Half Adder
Truth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
S = A B
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Carry, C = A . B
Circuit diagram:
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Full adder
Truth table:
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Sl.No. Input Output
A B C S C
1. 0 0 0 0 0
2. 0 0 1 1 0
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3. 0 1 0 1 04. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
7. 1 1 0 0 1
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8. 1 1 1 1 1Sl.No. Input Output
A B S C
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1. 0 0 0 02. 0 1 1 0
3. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
Carry:
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CARRY = AB + AC + BC
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Logic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Procedure:
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1. Connections are given as per the circuit diagrams.2. For all the IC?s 7
th
pin is grounded and 14
th
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pin is given +5 V supply.3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
Result:
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The design of the half adder and full adder circuits was done and their truth tables were verified.Outcome:
At the completion of an experiment student will able to design the half adder circuit and the
full adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
Aim:
To design and verify the truth table of the half subtractor & full subtractor circuits
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
subtrahend bit, hence 1 is borrowed.
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Half subtractor:A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
Full subtractor:
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A combinational circuit which performs the subtraction of three input bits is called full subtractor. Thethree input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
From the truth table the expression for difference and borrow bits of the output can be obtained
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as,Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
Borrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half subtractorTruth table:
Sl.No. Input Output
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A B Difference Borrow1. 0 0 0 0
2. 0 1 1 1
3. 1 0 1 0
4. 1 1 0 0
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From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A B
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Borrow, BORR = A?. BLogic diagram:
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2. Full subtractor
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Truth table:Sl.No.
Input Output
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A B C Difference Borrow1. 0 0 0 0 0
2. 0 0 1 1 1
3. 0 1 0 1 1
4. 0 1 1 0 1
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5. 1 0 0 1 06. 1 0 1 0 0
7. 1 1 0 0 0
8. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
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Borrow
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Borrow = A?B + A?C + BC
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Circuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
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Aim:
To design and implement 4-bit adder and subtractor using IC 7483
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. IC IC 7483 1
3. NOT gate IC 7404 1
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4. EX-OR gate IC 7486 15. Connecting wires As required
Theory:
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4 BIT Binary adder:A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected to
the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
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designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. Thecarries are connected in chain through full adder. The input carry to the adder is C
0
and it ripples through
the full adder to the output carry C
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4.
4 BIT Binary subtractor:
The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
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?B? and the corresponding input of full adder. The input carry C0
must be equal to 1 when performing
subtraction.
4 BIT Binary adder / subtractor:
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The addition and subtraction operation can be combined into one circuit with one common binary
adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
becomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PIN Diagram for IC 7483:
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Logic Diagram: 4-Bit Binary Diagram:
Logic diagram: 4-Bit Binary Subtractor:
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4-Bit Binary Adder /Subtractor:24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:
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Procedure:
1. Connections are given as per the circuit diagrams.
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2. Logical inputs were given as per circuit diagram.3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
.
Result:
The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
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verified.Outcome:
At the completion of an experiment student will able to design 4-bit binary adder and subtractor
Input Data A Input Data B Addition Subtraction
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A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D11 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
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1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 11 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
FirstRanker.com - FirstRanker's Choice
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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
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CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
Name : _______________________________________
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Register No : _______________________________________Section : _______________________________________
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LABORATORY MANUAL
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2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
training.
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? To provide competent technical manpower capable of meeting requirements of the industry
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? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
--- Content provided by FirstRanker.com ---
heart and soulDEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and ElectronicsEngineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
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? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
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professional ethical code.? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
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VISION
MISSION
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VISIONMISSION
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3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
1. Fundamentals
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To provide students with a solid foundation in mathematics, science and fundamentals ofengineering enabling them to solve complex problems in order to develop real time applications.
2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
--- Content provided by FirstRanker.com ---
technologies.3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
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development of society.4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
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professional ethics at all strategies.5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM OUTCOMES (POs)a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
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c. Graduates will be able to design and conduct experiments, analyze and interpret data.d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
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g. Graduates will demonstrate knowledge of professional and ethical responsibilities.h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
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k. Graduate who can participate and succeed in competitive examinations.--- Content provided by FirstRanker.com ---
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CS8381 DIGITAL SYSTEMS LABORATORY5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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SYLLABUS
Objectives:
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The student should be made to:? Understand the various logic gates.
? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
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? Learn to use HDLList of experiments:
1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
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3. Design and implementation of combinational circuits using MSI devices:a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
c. Magnitude Comparator
d. Application using multiplexers
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4. Design and implementation of sequential circuits:a. Shift ?registers
b. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
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Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
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? Design the different functional units in a digital computer system.? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Content
Sl.No. Name of the Experiment Page No.
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1.Verification of Boolean Theorems using Digital Logic Gates
2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
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3.
Implementation of half adder and full adder
4.
Implementation of half subtractor and full subtractor
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5.Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
6.
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Design and Implementation of Parity Generator / Checker using Basic Gates and MSIDevices
7.
Design and Implementation of Magnitude Comparator.
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8.Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
Design and Implementation of Shift Registers.
10.
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Design and Implementation of Synchronous and Asynchronous Counters.11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
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12.Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.1: STUDY OF BASIC GATES
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Aim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. NAND gate IC 7400 1
6. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
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AND gateThe AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
low.
OR gate
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The OR gate performs a logical addition commonly known as OR function. The output ishigh when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
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NAND gateThe NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
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output is low when one or both inputs are high.EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
EXOR Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
th
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pin is grounded and 14th
pin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
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Result:
The truth tables of all the basic logic gates were verified.
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Outcome:At the completion of an experiment student will able to verify the truth
table of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
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3. How many gates presented in IC 7408?4. What is IC?
5. What are the applications of gates?
6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
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8. Write the truth table of NOT gate.9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
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13. What are types of linear integrated circuit?14. What is meant by etching?
15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.2:
VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gates
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. NAND gate IC 7400 1
6. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
BASIC Boolean Laws
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1. Commutative Law
The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
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2. A.B=B.A2. Associative Law
The binary operator OR, AND is said to be associative if,
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1. A+(B+C) = (A+B)+C2. A.(B.C) = (A.B).C
3. Distributive Law
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The binary operator OR, AND is said to be distributive if,1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
4. Absorption Law
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1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
1. A+A = A
2. A.A = A
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6. Complementary Law
1. A+A' = 1
2. A.A' = 0
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7. De Morgan ?s Theorem
1. The complement of the sum is equal to the sum of the product of the individual
complements.
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A+B = A.B2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design1. Absorption Law
A+AB = A
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2. Involution (or) Double complement Law
A = A
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3. Idempotent Law
1. A+A = A
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2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:004. Demorgan ?s Law
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A+B = A.B
5. Distributive Law
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A+(B.C) = (A+B).(A+C)Procedure:
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
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cc.
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
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Result:
Thus the above stated Boolean laws are verified.
Outcome:
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At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?2. What is associative law?
3. What is mean by compliment gate?
4. Explain the basic laws in digital electronics
5. What is double complement?
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Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
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To design and verify the truth table of the Half Adder & Full Adder circuitsApparatus required:
S. No. Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
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6. Connecting wires As requiredTheory:
The most basic arithmetic operation is the addition of two binary digits. There are four
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possible elementary operations, namely,0 + 0 = 0
0 + 1 = 1
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1 + 0 = 1
1 + 1 = 0 (with 1 as carry)
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The first three operations produce a sum of whose length is one digit, but when the last operation isperformed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
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designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.Full adder:
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
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with two half adders and one OR gate.From the truth table, the expression for sum and carry bits of the output can be obtained as,
SUM = A?B?C + A?BC? + AB?C? + ABC
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CARRY = A?BC + AB?C + ABC? +ABC16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half Adder
Truth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
S = A B
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Carry, C = A . BCircuit diagram:
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Full adder
Truth table:
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Sl.No. Input OutputA B C S C
1. 0 0 0 0 0
2. 0 0 1 1 0
3. 0 1 0 1 0
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4. 0 1 1 0 15. 1 0 0 1 0
6. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input Output
A B S C
1. 0 0 0 0
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2. 0 1 1 03. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Sum:--- Content provided by FirstRanker.com ---
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B CCarry:
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CARRY = AB + AC + BC
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Logic Diagram:18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections are given as per the circuit diagrams.
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2. For all the IC?s 7th
pin is grounded and 14
th
pin is given +5 V supply.
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3. Apply the inputs and verify the truth table for the half adder and full adder circuits.Result:
The design of the half adder and full adder circuits was done and their truth tables were verified.
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Outcome:At the completion of an experiment student will able to design the half adder circuit and the
full adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTORAim:
To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. EX-OR gate IC 7486 1
6. Connecting wires As required
Theory:
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The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bitis subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
subtrahend bit, hence 1 is borrowed.
Half subtractor:
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A combinational circuit which performs the subtraction of two bits is called half subtractor. The inputvariables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
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three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can beimplemented with two half subtractors and one OR gate.
From the truth table the expression for difference and borrow bits of the output can be obtained
as,
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Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
Borrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half subtractor
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Truth table:
Sl.No. Input Output
A B Difference Borrow
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1. 0 0 0 02. 0 1 1 1
3. 1 0 1 0
4. 1 1 0 0
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From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A B
Borrow, BORR = A?. B
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Logic diagram:
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2. Full subtractor
Truth table:
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Sl.No.
Input Output
A B C Difference Borrow
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1. 0 0 0 0 02. 0 0 1 1 1
3. 0 1 0 1 1
4. 0 1 1 0 1
5. 1 0 0 1 0
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6. 1 0 1 0 07. 1 1 0 0 0
8. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
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Borrow--- Content provided by FirstRanker.com ---
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Borrow = A?B + A?C + BC
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Circuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
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Aim:To design and implement 4-bit adder and subtractor using IC 7483
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. IC IC 7483 1
3. NOT gate IC 7404 1
4. EX-OR gate IC 7486 1
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5. Connecting wires As requiredTheory:
4 BIT Binary adder:
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A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected to
the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
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carries are connected in chain through full adder. The input carry to the adder is C0
and it ripples through
the full adder to the output carry C
4
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.4 BIT Binary subtractor:
The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
?B? and the corresponding input of full adder. The input carry C
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0must be equal to 1 when performing
subtraction.
4 BIT Binary adder / subtractor:
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The addition and subtraction operation can be combined into one circuit with one common binaryadder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
becomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PIN Diagram for IC 7483:
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Logic Diagram: 4-Bit Binary Diagram:Logic diagram: 4-Bit Binary Subtractor:
4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:
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Procedure:
1. Connections are given as per the circuit diagrams.
2. Logical inputs were given as per circuit diagram.
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3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor..
Result:
The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
verified.
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Outcome:At the completion of an experiment student will able to design 4-bit binary adder and subtractor
Input Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
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1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 01 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
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1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 11 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
1. What is expression for difference and borrow?
2. Write the truth table for half adder.
3. Write the truth table for full adder.
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4. Write the truth table for half subtrator.5. Write the truth table for full subtrator.
6. Draw the logic diagram of full subtrator.
7. What is adder?
8. List out the application of adders.
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9. Draw the full adder using two half adder circuits.10. What is combinational circuit?
11. What is different between combinational and sequential circuit?
12. What are the gates involved for binary adder?
13. List the properties of Ex-Nor gate?
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14. What is expression for sum and carry?--- Content provided by FirstRanker.com ---
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Viva ? Voce
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FirstRanker.com - FirstRanker's Choice1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
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III SEMESTER - R 2017
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
Section : _______________________________________
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LABORATORY MANUAL
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2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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is committed to provide highly disciplined, conscientious and
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enterprising professionals conforming to global standards through value based quality education andtraining.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
--- Content provided by FirstRanker.com ---
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
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needs.? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
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industry by continuous assessment and training.VISION
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MISSIONVISION
MISSION
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3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
--- Content provided by FirstRanker.com ---
1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
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2. Core CompetenceTo train the students to meet the needs of core industry with an attitude of learning new
technologies.
3. Breadth
--- Content provided by FirstRanker.com ---
To provide relevant training and experience to bridge the gap between theory and practice whichenable them to find solutions to problems in industry and research that contributes to the overall
development of society.
4. Professionalism
--- Content provided by FirstRanker.com ---
To inculcate professional and effective communication skills to the students to make them lead ateam and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
5. Lifelong Learning/Ethics
--- Content provided by FirstRanker.com ---
To practice ethical and professional responsibilities in the organization and society withcommitment and lifelong learning needed for successful professional career.
--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
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f. Graduates will demonstrate skills to use modern engineering tools, software and equipment toanalyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
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will be aware of contemporary issues.j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
SYLLABUS
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Objectives:
The student should be made to:
? Understand the various logic gates.
? Be familiar with various combinational circuits.
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? Understand the various components used in the design of digital computers.? Be exposed to sequential circuits
? Learn to use HDL
List of experiments:
1. Verification of Boolean Theorems using basic gates.
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2. Design and implementation of combinational circuits using basic gates for arbitraryfunctions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
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c. Magnitude Comparatord. Application using multiplexers
4. Design and implementation of sequential circuits:
a. Shift ?registers
b. Synchronous and asynchronous counters
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5. Coding combinational / sequential circuits using HDL.6. Design and implementation of a simple digital system (Mini Project).
Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
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? Design and Implement combinational and sequential circuits.? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Content
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Sl.No. Name of the Experiment Page No.
1.
Verification of Boolean Theorems using Digital Logic Gates
2.
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Design and Implementation of Combinational Circuits using Basic Gates for ArbitraryFunctions, Code Converters
3.
Implementation of half adder and full adder
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4.Implementation of half subtractor and full subtractor
5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
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6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
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7.Design and Implementation of Magnitude Comparator.
8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
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Design and Implementation of Shift Registers.10.
Design and Implementation of Synchronous and Asynchronous Counters.
11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
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HDL Software Required).12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.1: STUDY OF BASIC GATES
Aim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
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7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
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more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known asuniversal gates. Basic gates form these gates.
AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
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low.OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
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A NOT gate is the physical realization of the complementation operation. The NOT gate iscalled an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
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NOR gateThe NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
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similar to OR gate but excludes the combination of both A and B being equal to one. The exclusiveOR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Procedure:
1. Connections are given as per the circuit diagram.
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2. For all the IC?s 7th
pin is grounded and 14
th
pin is given +5 supply.
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3. Apply the inputs and verify the truth table for all gates.Result:
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The truth tables of all the basic logic gates were verified.Outcome:
At the completion of an experiment student will able to verify the truth
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table of all basic gates--- Content provided by FirstRanker.com ---
1. List out the basic gate.2. Mention the universal gate.
3. How many gates presented in IC 7408?
4. What is IC?
5. What are the applications of gates?
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6. Write the truth table of AND gate.7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
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11. Write the truth table of EX- OR gate.12. What are the classifications of IC?
13. What are types of linear integrated circuit?
14. What is meant by etching?
15. What are the advantages of IC?
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16. Write the truth table of EX- NOR gate.Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.2:
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VERIFICATION OF BOOLEAN THEOREMS USING LOGICGATES
Aim: To verification of Boolean theorems using logic gates
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 3
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7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
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BASIC Boolean Laws
1. Commutative Law
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The binary operator OR, AND is said to be commutative if,1. A+B = B+A
2. A.B=B.A
2. Associative Law
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The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
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3. Distributive LawThe binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
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4. Absorption Law
1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
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1. A+A = A2. A.A = A
6. Complementary Law
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1. A+A' = 12. A.A' = 0
7. De Morgan ?s Theorem
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1. The complement of the sum is equal to the sum of the product of the individualcomplements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design
1. Absorption Law
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A+AB = A--- Content provided by FirstRanker.com ---
2. Involution (or) Double complement Law
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A = A--- Content provided by FirstRanker.com ---
3. Idempotent Law
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1. A+A = A
2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
A+B = A.B
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5. Distributive Law
A+(B.C) = (A+B).(A+C)
Procedure:
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1. Obtain the required IC along with the Digital trainer kit.2. Connect zero volts to GND pin and +5 volts to V
cc
.
3. Apply the inputs to the respective input pins.
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4. Verify the output with the truth table.Result:
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Thus the above stated Boolean laws are verified.Outcome:
At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?
2. What is associative law?
3. What is mean by compliment gate?
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4. Explain the basic laws in digital electronics5. What is double complement?
Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.3: HALF ADDER AND FULL ADDERAim:
To design and verify the truth table of the Half Adder & Full Adder circuits
Apparatus required:
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S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
0 + 0 = 0
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0 + 1 = 1
1 + 0 = 1
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1 + 1 = 0 (with 1 as carry)The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
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Half adder:A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
Full adder:
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A combinational circuit which performs the arithmetic sum of three input bits is called full adder. Thethree input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
From the truth table, the expression for sum and carry bits of the output can be obtained as,
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SUM = A?B?C + A?BC? + AB?C? + ABCCARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half Adder
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Truth table:--- Content provided by FirstRanker.com ---
From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
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S = A BCarry, C = A . B
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Circuit diagram:--- Content provided by FirstRanker.com ---
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Full adder
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Truth table:Sl.No. Input Output
A B C S C
1. 0 0 0 0 0
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2. 0 0 1 1 03. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
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7. 1 1 0 0 18. 1 1 1 1 1
Sl.No. Input Output
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A B S C1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:--- Content provided by FirstRanker.com ---
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CARRY = AB + AC + BC
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Logic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
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1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
th
pin is grounded and 14
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thpin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
Result:
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The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
At the completion of an experiment student will able to design the half adder circuit and the
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full adder circuit.--- Content provided by FirstRanker.com ---
19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
Aim:
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To design and verify the truth table of the half subtractor & full subtractor circuitsApparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
subtrahend bit, hence 1 is borrowed.
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Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
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Full subtractor:A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
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From the truth table the expression for difference and borrow bits of the output can be obtainedas,
Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
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Borrow, BORR = A?BC + AB?C + ABC? +ABC--- Content provided by FirstRanker.com ---
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half subtractor
Truth table:
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Sl.No. Input OutputA B Difference Borrow
1. 0 0 0 0
2. 0 1 1 1
3. 1 0 1 0
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4. 1 1 0 0From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A B
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Borrow, BORR = A?. B
Logic diagram:
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2. Full subtractorTruth table:
Sl.No.
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Input OutputA B C Difference Borrow
1. 0 0 0 0 0
2. 0 0 1 1 1
3. 0 1 0 1 1
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4. 0 1 1 0 15. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
8. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
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Borrow
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Borrow = A?B + A?C + BCCircuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
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Aim:
To design and implement 4-bit adder and subtractor using IC 7483
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. IC IC 7483 1
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3. NOT gate IC 7404 14. EX-OR gate IC 7486 1
5. Connecting wires As required
Theory:
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4 BIT Binary adder:
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected to
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the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? aredesignated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
0
and it ripples through
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the full adder to the output carry C4
.
4 BIT Binary subtractor:
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The circuit for subtracting A-B consists of an adder with inverters, placed between each data input?B? and the corresponding input of full adder. The input carry C
0
must be equal to 1 when performing
subtraction.
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4 BIT Binary adder / subtractor:The addition and subtraction operation can be combined into one circuit with one common binary
adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
becomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PIN Diagram for IC 7483:Logic Diagram: 4-Bit Binary Diagram:
Logic diagram: 4-Bit Binary Subtractor:
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4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Truth table:
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Procedure:
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1. Connections are given as per the circuit diagrams.2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
.
Result:
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The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table wasverified.
Outcome:
At the completion of an experiment student will able to design 4-bit binary adder and subtractor
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Input Data A Input Data B Addition SubtractionA4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
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0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 01 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?
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2. Write the truth table for half adder.3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
5. Write the truth table for full subtrator.
6. Draw the logic diagram of full subtrator.
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7. What is adder?8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
10. What is combinational circuit?
11. What is different between combinational and sequential circuit?
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12. What are the gates involved for binary adder?13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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Viva ? Voce--- Content provided by FirstRanker.com ---
26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.6: MAGNITUDE COMPARATOR
Aim:
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To design, construct and study the performance of 2 bit magnitude comparatorApparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:
The comparison of two numbers is an operator that determines one number is greater than, less
than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
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numbers A and B and determines their relative magnitude. The outcome of the comparator is specified bythree binary variables that indicate whether A>B, A=B (or) A
Truth table:
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FirstRanker.com - FirstRanker's Choice1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
--- Content provided by FirstRanker.com ---
DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
III SEMESTER - R 2017
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
Section : _______________________________________
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LABORATORY MANUAL
--- Content provided by FirstRanker.com ---
2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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is committed to provide highly disciplined, conscientious and
--- Content provided by FirstRanker.com ---
enterprising professionals conforming to global standards through value based quality education andtraining.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
--- Content provided by FirstRanker.com ---
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
--- Content provided by FirstRanker.com ---
needs.? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
--- Content provided by FirstRanker.com ---
industry by continuous assessment and training.VISION
--- Content provided by FirstRanker.com ---
MISSIONVISION
MISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
--- Content provided by FirstRanker.com ---
1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
--- Content provided by FirstRanker.com ---
2. Core CompetenceTo train the students to meet the needs of core industry with an attitude of learning new
technologies.
3. Breadth
--- Content provided by FirstRanker.com ---
To provide relevant training and experience to bridge the gap between theory and practice whichenable them to find solutions to problems in industry and research that contributes to the overall
development of society.
4. Professionalism
--- Content provided by FirstRanker.com ---
To inculcate professional and effective communication skills to the students to make them lead ateam and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
5. Lifelong Learning/Ethics
--- Content provided by FirstRanker.com ---
To practice ethical and professional responsibilities in the organization and society withcommitment and lifelong learning needed for successful professional career.
--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
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f. Graduates will demonstrate skills to use modern engineering tools, software and equipment toanalyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
--- Content provided by FirstRanker.com ---
will be aware of contemporary issues.j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
SYLLABUS
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Objectives:
The student should be made to:
? Understand the various logic gates.
? Be familiar with various combinational circuits.
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? Understand the various components used in the design of digital computers.? Be exposed to sequential circuits
? Learn to use HDL
List of experiments:
1. Verification of Boolean Theorems using basic gates.
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2. Design and implementation of combinational circuits using basic gates for arbitraryfunctions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
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c. Magnitude Comparatord. Application using multiplexers
4. Design and implementation of sequential circuits:
a. Shift ?registers
b. Synchronous and asynchronous counters
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5. Coding combinational / sequential circuits using HDL.6. Design and implementation of a simple digital system (Mini Project).
Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
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? Design and Implement combinational and sequential circuits.? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Content
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Sl.No. Name of the Experiment Page No.
1.
Verification of Boolean Theorems using Digital Logic Gates
2.
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Design and Implementation of Combinational Circuits using Basic Gates for ArbitraryFunctions, Code Converters
3.
Implementation of half adder and full adder
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4.Implementation of half subtractor and full subtractor
5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
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6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
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7.Design and Implementation of Magnitude Comparator.
8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
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Design and Implementation of Shift Registers.10.
Design and Implementation of Synchronous and Asynchronous Counters.
11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
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HDL Software Required).12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.1: STUDY OF BASIC GATES
Aim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
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7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
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more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known asuniversal gates. Basic gates form these gates.
AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
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low.OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
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A NOT gate is the physical realization of the complementation operation. The NOT gate iscalled an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
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NOR gateThe NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
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similar to OR gate but excludes the combination of both A and B being equal to one. The exclusiveOR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Procedure:
1. Connections are given as per the circuit diagram.
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2. For all the IC?s 7th
pin is grounded and 14
th
pin is given +5 supply.
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3. Apply the inputs and verify the truth table for all gates.Result:
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The truth tables of all the basic logic gates were verified.Outcome:
At the completion of an experiment student will able to verify the truth
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table of all basic gates--- Content provided by FirstRanker.com ---
1. List out the basic gate.2. Mention the universal gate.
3. How many gates presented in IC 7408?
4. What is IC?
5. What are the applications of gates?
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6. Write the truth table of AND gate.7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
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11. Write the truth table of EX- OR gate.12. What are the classifications of IC?
13. What are types of linear integrated circuit?
14. What is meant by etching?
15. What are the advantages of IC?
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16. Write the truth table of EX- NOR gate.Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.2:
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VERIFICATION OF BOOLEAN THEOREMS USING LOGICGATES
Aim: To verification of Boolean theorems using logic gates
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 3
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7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
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BASIC Boolean Laws
1. Commutative Law
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The binary operator OR, AND is said to be commutative if,1. A+B = B+A
2. A.B=B.A
2. Associative Law
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The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
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3. Distributive LawThe binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
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4. Absorption Law
1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
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1. A+A = A2. A.A = A
6. Complementary Law
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1. A+A' = 12. A.A' = 0
7. De Morgan ?s Theorem
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1. The complement of the sum is equal to the sum of the product of the individualcomplements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design
1. Absorption Law
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A+AB = A--- Content provided by FirstRanker.com ---
2. Involution (or) Double complement Law
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A = A--- Content provided by FirstRanker.com ---
3. Idempotent Law
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1. A+A = A
2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
A+B = A.B
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5. Distributive Law
A+(B.C) = (A+B).(A+C)
Procedure:
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1. Obtain the required IC along with the Digital trainer kit.2. Connect zero volts to GND pin and +5 volts to V
cc
.
3. Apply the inputs to the respective input pins.
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4. Verify the output with the truth table.Result:
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Thus the above stated Boolean laws are verified.Outcome:
At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?
2. What is associative law?
3. What is mean by compliment gate?
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4. Explain the basic laws in digital electronics5. What is double complement?
Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.3: HALF ADDER AND FULL ADDERAim:
To design and verify the truth table of the Half Adder & Full Adder circuits
Apparatus required:
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S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
0 + 0 = 0
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0 + 1 = 1
1 + 0 = 1
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1 + 1 = 0 (with 1 as carry)The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
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Half adder:A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
Full adder:
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A combinational circuit which performs the arithmetic sum of three input bits is called full adder. Thethree input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
From the truth table, the expression for sum and carry bits of the output can be obtained as,
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SUM = A?B?C + A?BC? + AB?C? + ABCCARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half Adder
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Truth table:--- Content provided by FirstRanker.com ---
From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
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S = A BCarry, C = A . B
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Circuit diagram:--- Content provided by FirstRanker.com ---
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Full adder
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Truth table:Sl.No. Input Output
A B C S C
1. 0 0 0 0 0
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2. 0 0 1 1 03. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
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7. 1 1 0 0 18. 1 1 1 1 1
Sl.No. Input Output
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A B S C1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:--- Content provided by FirstRanker.com ---
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CARRY = AB + AC + BC
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Logic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
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1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
th
pin is grounded and 14
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thpin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
Result:
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The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
At the completion of an experiment student will able to design the half adder circuit and the
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full adder circuit.--- Content provided by FirstRanker.com ---
19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
Aim:
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To design and verify the truth table of the half subtractor & full subtractor circuitsApparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
subtrahend bit, hence 1 is borrowed.
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Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
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Full subtractor:A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
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From the truth table the expression for difference and borrow bits of the output can be obtainedas,
Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
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Borrow, BORR = A?BC + AB?C + ABC? +ABC--- Content provided by FirstRanker.com ---
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half subtractor
Truth table:
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Sl.No. Input OutputA B Difference Borrow
1. 0 0 0 0
2. 0 1 1 1
3. 1 0 1 0
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4. 1 1 0 0From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A B
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Borrow, BORR = A?. B
Logic diagram:
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2. Full subtractorTruth table:
Sl.No.
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Input OutputA B C Difference Borrow
1. 0 0 0 0 0
2. 0 0 1 1 1
3. 0 1 0 1 1
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4. 0 1 1 0 15. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
8. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
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Borrow
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Borrow = A?B + A?C + BCCircuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
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Aim:
To design and implement 4-bit adder and subtractor using IC 7483
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. IC IC 7483 1
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3. NOT gate IC 7404 14. EX-OR gate IC 7486 1
5. Connecting wires As required
Theory:
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4 BIT Binary adder:
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected to
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the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? aredesignated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
0
and it ripples through
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the full adder to the output carry C4
.
4 BIT Binary subtractor:
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The circuit for subtracting A-B consists of an adder with inverters, placed between each data input?B? and the corresponding input of full adder. The input carry C
0
must be equal to 1 when performing
subtraction.
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4 BIT Binary adder / subtractor:The addition and subtraction operation can be combined into one circuit with one common binary
adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
becomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PIN Diagram for IC 7483:Logic Diagram: 4-Bit Binary Diagram:
Logic diagram: 4-Bit Binary Subtractor:
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4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Truth table:
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Procedure:
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1. Connections are given as per the circuit diagrams.2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
.
Result:
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The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table wasverified.
Outcome:
At the completion of an experiment student will able to design 4-bit binary adder and subtractor
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Input Data A Input Data B Addition SubtractionA4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
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0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 01 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?
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2. Write the truth table for half adder.3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
5. Write the truth table for full subtrator.
6. Draw the logic diagram of full subtrator.
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7. What is adder?8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
10. What is combinational circuit?
11. What is different between combinational and sequential circuit?
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12. What are the gates involved for binary adder?13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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Viva ? Voce--- Content provided by FirstRanker.com ---
26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.6: MAGNITUDE COMPARATOR
Aim:
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To design, construct and study the performance of 2 bit magnitude comparatorApparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:
The comparison of two numbers is an operator that determines one number is greater than, less
than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
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numbers A and B and determines their relative magnitude. The outcome of the comparator is specified bythree binary variables that indicate whether A>B, A=B (or) A
Truth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K-map
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FirstRanker.com - FirstRanker's Choice
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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
?DEPARTMENT OF
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COMPUTER SCIENCE ENGINEERINGIII SEMESTER - R 2017
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
Section : _______________________________________
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LABORATORY MANUAL
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2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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is committed to provide highly disciplined, conscientious andenterprising professionals conforming to global standards through value based quality education and
training.
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? To provide competent technical manpower capable of meeting requirements of the industry
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
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levels? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
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DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
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Electrical and Electronics Engineers.--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?sneeds.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
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concepts with strongly supported laboratory and prepare them to meet the global needs of theindustry by continuous assessment and training.
VISION
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MISSION
VISION
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MISSION--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
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1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
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2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
technologies.
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3. BreadthTo provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
development of society.
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4. ProfessionalismTo inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
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5. Lifelong Learning/EthicsTo practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
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e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
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i. Graduates will show the understanding of impact of engineering solutions on the society and alsowill be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
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CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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SYLLABUSObjectives:
The student should be made to:
? Understand the various logic gates.
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? Be familiar with various combinational circuits.? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
? Learn to use HDL
List of experiments:
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1. Verification of Boolean Theorems using basic gates.2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
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b. Parity generator / checkerc. Magnitude Comparator
d. Application using multiplexers
4. Design and implementation of sequential circuits:
a. Shift ?registers
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b. Synchronous and asynchronous counters5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
Course Outcomes:
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? Use Boolean simplification techniques to design a combinational hardware circuit.? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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ContentSl.No. Name of the Experiment Page No.
1.
Verification of Boolean Theorems using Digital Logic Gates
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2.Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
3.
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Implementation of half adder and full adder4.
Implementation of half subtractor and full subtractor
5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
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MSI Devices6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
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7.
Design and Implementation of Magnitude Comparator.
8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
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9.Design and Implementation of Shift Registers.
10.
Design and Implementation of Synchronous and Asynchronous Counters.
11.
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Simulation of Combinational Circuits using Hardware Description Language (VHDL / VerilogHDL Software Required).
12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.1: STUDY OF BASIC GATES
Aim:
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To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gatesApparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
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6. NOR gate IC 7402 17. EX-OR gate IC 7486 1
8. Connecting wires As required
Theory:
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Circuit that takes the logical decision and the process are called logic gates. Each gate has one ormore input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
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output is high when both the inputs are high. The output is low level when any one of the inputs islow.
OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
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NOT gateA NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
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and any one of the input is low .The output is low level when both inputs are high.NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
EX-OR gate
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An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It issimilar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
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1. Connections are given as per the circuit diagram.2. For all the IC?s 7
th
pin is grounded and 14
th
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pin is given +5 supply.3. Apply the inputs and verify the truth table for all gates.
Result:
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The truth tables of all the basic logic gates were verified.
Outcome:
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At the completion of an experiment student will able to verify the truthtable of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
3. How many gates presented in IC 7408?
4. What is IC?
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5. What are the applications of gates?6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
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10. Write the truth table of NOR gate.11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
13. What are types of linear integrated circuit?
14. What is meant by etching?
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15. What are the advantages of IC?16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.2:
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VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gatesApparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
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6. NOR gate IC 7402 37. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:BASIC Boolean Laws
1. Commutative Law
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The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A
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2. Associative LawThe binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
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3. Distributive Law
The binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
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2. A.(B+C) = (A.B)+(A.C)4. Absorption Law
1. A+AB = A
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2. A+AB =A+B--- Content provided by FirstRanker.com ---
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:005. Idempotent Law
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1. A+A = A
2. A.A = A
6. Complementary Law
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1. A+A' = 1
2. A.A' = 0
7. De Morgan ?s Theorem
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1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
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A.B = A+BDesign
1. Absorption Law
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A+AB = A
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2. Involution (or) Double complement Law
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A = A
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3. Idempotent Law1. A+A = A
2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
A+B = A.B
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5. Distributive Law
A+(B.C) = (A+B).(A+C)
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Procedure:1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
cc
.
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3. Apply the inputs to the respective input pins.4. Verify the output with the truth table.
Result:
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Thus the above stated Boolean laws are verified.
Outcome:
At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?
2. What is associative law?
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3. What is mean by compliment gate?4. Explain the basic laws in digital electronics
5. What is double complement?
Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
To design and verify the truth table of the Half Adder & Full Adder circuits
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Apparatus required:S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:
The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
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0 + 0 = 00 + 1 = 1
1 + 0 = 1
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1 + 1 = 0 (with 1 as carry)
The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
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significant bit is called the sum.Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
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Full adder:A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
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From the truth table, the expression for sum and carry bits of the output can be obtained as,SUM = A?B?C + A?BC? + AB?C? + ABC
CARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half AdderTruth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,S = A B
Carry, C = A . B
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Circuit diagram:
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Full adderTruth table:
Sl.No. Input Output
A B C S C
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1. 0 0 0 0 02. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
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6. 1 0 1 0 17. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input OutputA B S C
1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
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4. 1 1 1 117 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:
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CARRY = AB + AC + BCLogic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
th
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pin is grounded and 14th
pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
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Result:The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
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At the completion of an experiment student will able to design the half adder circuit and thefull adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
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Aim:To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
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6. Connecting wires As requiredTheory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
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subtrahend bit, hence 1 is borrowed.Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
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difference and borrow bits.Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
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From the truth table the expression for difference and borrow bits of the output can be obtained
as,
Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
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Borrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Half subtractor
Truth table:
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Sl.No. Input Output
A B Difference Borrow
1. 0 0 0 0
2. 0 1 1 1
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3. 1 0 1 04. 1 1 0 0
From the truth table the expression for difference and borrow bits of the output can be obtained as,
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Difference, DIFF = A BBorrow, BORR = A?. B
Logic diagram:
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2. Full subtractor
Truth table:
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Sl.No.Input Output
A B C Difference Borrow
1. 0 0 0 0 0
2. 0 0 1 1 1
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3. 0 1 0 1 14. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
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8. 1 1 1 1 1--- Content provided by FirstRanker.com ---
21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Difference--- Content provided by FirstRanker.com ---
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Difference = A?B?C + A?BC? + AB?C? + ABCBorrow
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Borrow = A?B + A?C + BC
Circuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.5: 4-BIT ADDER AND SUBTRACTORAim:
To design and implement 4-bit adder and subtractor using IC 7483
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. IC IC 7483 13. NOT gate IC 7404 1
4. EX-OR gate IC 7486 1
5. Connecting wires As required
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Theory:4 BIT Binary adder:
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
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constructed with full adders connected in cascade, with the output carry from each full adder connected tothe input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
0
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and it ripples throughthe full adder to the output carry C
4
.
4 BIT Binary subtractor:
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The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
?B? and the corresponding input of full adder. The input carry C
0
must be equal to 1 when performing
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subtraction.4 BIT Binary adder / subtractor:
The addition and subtraction operation can be combined into one circuit with one common binary
adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
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becomes subtractor.23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PIN Diagram for IC 7483:
Logic Diagram: 4-Bit Binary Diagram:
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Logic diagram: 4-Bit Binary Subtractor:4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:--- Content provided by FirstRanker.com ---
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Procedure:1. Connections are given as per the circuit diagrams.
2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
.
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Result:The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
verified.
Outcome:
At the completion of an experiment student will able to design 4-bit binary adder and subtractor
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Input Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
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0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 00 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?2. Write the truth table for half adder.
3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
5. Write the truth table for full subtrator.
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6. Draw the logic diagram of full subtrator.7. What is adder?
8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
10. What is combinational circuit?
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11. What is different between combinational and sequential circuit?12. What are the gates involved for binary adder?
13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.6: MAGNITUDE COMPARATOR
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Aim:To design, construct and study the performance of 2 bit magnitude comparator
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
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7. Connecting wires As requiredTheory:
The comparison of two numbers is an operator that determines one number is greater than, less
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than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares twonumbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
three binary variables that indicate whether A>B, A=B (or) A
Truth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Logic Diagram:
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Pin Diagram for IC 7485:
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Logic Diagram:
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FirstRanker.com - FirstRanker's Choice1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
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III SEMESTER - R 2017
CS8382 DIGITAL SYSTEMS LABORATORY
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--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
Section : _______________________________________
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LABORATORY MANUAL
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2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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is committed to provide highly disciplined, conscientious and
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enterprising professionals conforming to global standards through value based quality education andtraining.
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? To provide competent technical manpower capable of meeting requirements of the industry
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
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? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
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DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
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To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
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? To provide the students rigorous learning experience to produce creative solutions to society?s
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needs.? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
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industry by continuous assessment and training.VISION
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MISSIONVISION
MISSION
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3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
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1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
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2. Core CompetenceTo train the students to meet the needs of core industry with an attitude of learning new
technologies.
3. Breadth
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To provide relevant training and experience to bridge the gap between theory and practice whichenable them to find solutions to problems in industry and research that contributes to the overall
development of society.
4. Professionalism
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To inculcate professional and effective communication skills to the students to make them lead ateam and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
5. Lifelong Learning/Ethics
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To practice ethical and professional responsibilities in the organization and society withcommitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
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f. Graduates will demonstrate skills to use modern engineering tools, software and equipment toanalyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
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will be aware of contemporary issues.j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
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CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
SYLLABUS
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Objectives:
The student should be made to:
? Understand the various logic gates.
? Be familiar with various combinational circuits.
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? Understand the various components used in the design of digital computers.? Be exposed to sequential circuits
? Learn to use HDL
List of experiments:
1. Verification of Boolean Theorems using basic gates.
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2. Design and implementation of combinational circuits using basic gates for arbitraryfunctions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
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c. Magnitude Comparatord. Application using multiplexers
4. Design and implementation of sequential circuits:
a. Shift ?registers
b. Synchronous and asynchronous counters
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5. Coding combinational / sequential circuits using HDL.6. Design and implementation of a simple digital system (Mini Project).
Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
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? Design and Implement combinational and sequential circuits.? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Content
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Sl.No. Name of the Experiment Page No.
1.
Verification of Boolean Theorems using Digital Logic Gates
2.
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Design and Implementation of Combinational Circuits using Basic Gates for ArbitraryFunctions, Code Converters
3.
Implementation of half adder and full adder
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4.Implementation of half subtractor and full subtractor
5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
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6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
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7.Design and Implementation of Magnitude Comparator.
8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
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Design and Implementation of Shift Registers.10.
Design and Implementation of Synchronous and Asynchronous Counters.
11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
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HDL Software Required).12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.1: STUDY OF BASIC GATES
Aim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
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7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
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more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known asuniversal gates. Basic gates form these gates.
AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
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low.OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
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A NOT gate is the physical realization of the complementation operation. The NOT gate iscalled an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
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NOR gateThe NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
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similar to OR gate but excludes the combination of both A and B being equal to one. The exclusiveOR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Procedure:
1. Connections are given as per the circuit diagram.
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2. For all the IC?s 7th
pin is grounded and 14
th
pin is given +5 supply.
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3. Apply the inputs and verify the truth table for all gates.Result:
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The truth tables of all the basic logic gates were verified.Outcome:
At the completion of an experiment student will able to verify the truth
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table of all basic gates--- Content provided by FirstRanker.com ---
1. List out the basic gate.2. Mention the universal gate.
3. How many gates presented in IC 7408?
4. What is IC?
5. What are the applications of gates?
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6. Write the truth table of AND gate.7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
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11. Write the truth table of EX- OR gate.12. What are the classifications of IC?
13. What are types of linear integrated circuit?
14. What is meant by etching?
15. What are the advantages of IC?
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16. Write the truth table of EX- NOR gate.Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.2:
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VERIFICATION OF BOOLEAN THEOREMS USING LOGICGATES
Aim: To verification of Boolean theorems using logic gates
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
--- Content provided by FirstRanker.com ---
2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 3
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7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
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BASIC Boolean Laws
1. Commutative Law
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The binary operator OR, AND is said to be commutative if,1. A+B = B+A
2. A.B=B.A
2. Associative Law
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The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
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3. Distributive LawThe binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
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4. Absorption Law
1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
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1. A+A = A2. A.A = A
6. Complementary Law
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1. A+A' = 12. A.A' = 0
7. De Morgan ?s Theorem
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1. The complement of the sum is equal to the sum of the product of the individualcomplements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design
1. Absorption Law
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A+AB = A--- Content provided by FirstRanker.com ---
2. Involution (or) Double complement Law
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A = A--- Content provided by FirstRanker.com ---
3. Idempotent Law
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1. A+A = A
2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
A+B = A.B
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5. Distributive Law
A+(B.C) = (A+B).(A+C)
Procedure:
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1. Obtain the required IC along with the Digital trainer kit.2. Connect zero volts to GND pin and +5 volts to V
cc
.
3. Apply the inputs to the respective input pins.
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4. Verify the output with the truth table.Result:
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Thus the above stated Boolean laws are verified.Outcome:
At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?
2. What is associative law?
3. What is mean by compliment gate?
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4. Explain the basic laws in digital electronics5. What is double complement?
Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.3: HALF ADDER AND FULL ADDERAim:
To design and verify the truth table of the Half Adder & Full Adder circuits
Apparatus required:
--- Content provided by FirstRanker.com ---
S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
0 + 0 = 0
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0 + 1 = 1
1 + 0 = 1
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1 + 1 = 0 (with 1 as carry)The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
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Half adder:A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
Full adder:
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A combinational circuit which performs the arithmetic sum of three input bits is called full adder. Thethree input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
From the truth table, the expression for sum and carry bits of the output can be obtained as,
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SUM = A?B?C + A?BC? + AB?C? + ABCCARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half Adder
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Truth table:--- Content provided by FirstRanker.com ---
From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
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S = A BCarry, C = A . B
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Circuit diagram:--- Content provided by FirstRanker.com ---
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Full adder
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Truth table:Sl.No. Input Output
A B C S C
1. 0 0 0 0 0
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2. 0 0 1 1 03. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
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7. 1 1 0 0 18. 1 1 1 1 1
Sl.No. Input Output
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A B S C1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:--- Content provided by FirstRanker.com ---
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CARRY = AB + AC + BC
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Logic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
--- Content provided by FirstRanker.com ---
1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
th
pin is grounded and 14
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thpin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
Result:
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The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
At the completion of an experiment student will able to design the half adder circuit and the
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full adder circuit.--- Content provided by FirstRanker.com ---
19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
Aim:
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To design and verify the truth table of the half subtractor & full subtractor circuitsApparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
--- Content provided by FirstRanker.com ---
2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
subtrahend bit, hence 1 is borrowed.
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Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
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Full subtractor:A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
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From the truth table the expression for difference and borrow bits of the output can be obtainedas,
Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
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Borrow, BORR = A?BC + AB?C + ABC? +ABC--- Content provided by FirstRanker.com ---
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half subtractor
Truth table:
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Sl.No. Input OutputA B Difference Borrow
1. 0 0 0 0
2. 0 1 1 1
3. 1 0 1 0
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4. 1 1 0 0From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A B
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Borrow, BORR = A?. B
Logic diagram:
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2. Full subtractorTruth table:
Sl.No.
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Input OutputA B C Difference Borrow
1. 0 0 0 0 0
2. 0 0 1 1 1
3. 0 1 0 1 1
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4. 0 1 1 0 15. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
8. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
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Borrow
--- Content provided by FirstRanker.com ---
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Borrow = A?B + A?C + BCCircuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
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Aim:
To design and implement 4-bit adder and subtractor using IC 7483
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. IC IC 7483 1
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3. NOT gate IC 7404 14. EX-OR gate IC 7486 1
5. Connecting wires As required
Theory:
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4 BIT Binary adder:
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected to
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the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? aredesignated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
0
and it ripples through
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the full adder to the output carry C4
.
4 BIT Binary subtractor:
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The circuit for subtracting A-B consists of an adder with inverters, placed between each data input?B? and the corresponding input of full adder. The input carry C
0
must be equal to 1 when performing
subtraction.
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4 BIT Binary adder / subtractor:The addition and subtraction operation can be combined into one circuit with one common binary
adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
becomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PIN Diagram for IC 7483:Logic Diagram: 4-Bit Binary Diagram:
Logic diagram: 4-Bit Binary Subtractor:
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4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Truth table:
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Procedure:
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1. Connections are given as per the circuit diagrams.2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
.
Result:
--- Content provided by FirstRanker.com ---
The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table wasverified.
Outcome:
At the completion of an experiment student will able to design 4-bit binary adder and subtractor
--- Content provided by FirstRanker.com ---
Input Data A Input Data B Addition SubtractionA4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
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0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 01 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?
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2. Write the truth table for half adder.3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
5. Write the truth table for full subtrator.
6. Draw the logic diagram of full subtrator.
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7. What is adder?8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
10. What is combinational circuit?
11. What is different between combinational and sequential circuit?
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12. What are the gates involved for binary adder?13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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Viva ? Voce--- Content provided by FirstRanker.com ---
26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.6: MAGNITUDE COMPARATOR
Aim:
--- Content provided by FirstRanker.com ---
To design, construct and study the performance of 2 bit magnitude comparatorApparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
--- Content provided by FirstRanker.com ---
3. OR gate IC 7432 14. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:
The comparison of two numbers is an operator that determines one number is greater than, less
than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
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numbers A and B and determines their relative magnitude. The outcome of the comparator is specified bythree binary variables that indicate whether A>B, A=B (or) A
Truth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:
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Pin Diagram for IC 7485:--- Content provided by FirstRanker.com ---
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:
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Truth table:
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Procedure:1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
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Result:Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
comparator using logic gates.
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A B A>B A=B A0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
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0 1 00 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
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1 0 00 0 0 0
0 0 0 0
0 0 0 1
0 0 0 1
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0 0 1Viva ? Voce
FirstRanker.com - FirstRanker's Choice
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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
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CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
Name : _______________________________________
--- Content provided by FirstRanker.com ---
Register No : _______________________________________Section : _______________________________________
--- Content provided by FirstRanker.com ---
LABORATORY MANUAL
--- Content provided by FirstRanker.com ---
2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
training.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
--- Content provided by FirstRanker.com ---
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
--- Content provided by FirstRanker.com ---
heart and soulDEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and ElectronicsEngineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
--- Content provided by FirstRanker.com ---
professional ethical code.? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
--- Content provided by FirstRanker.com ---
VISION
MISSION
--- Content provided by FirstRanker.com ---
VISIONMISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
1. Fundamentals
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To provide students with a solid foundation in mathematics, science and fundamentals ofengineering enabling them to solve complex problems in order to develop real time applications.
2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
--- Content provided by FirstRanker.com ---
technologies.3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
--- Content provided by FirstRanker.com ---
development of society.4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
--- Content provided by FirstRanker.com ---
professional ethics at all strategies.5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM OUTCOMES (POs)a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
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c. Graduates will be able to design and conduct experiments, analyze and interpret data.d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
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g. Graduates will demonstrate knowledge of professional and ethical responsibilities.h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
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k. Graduate who can participate and succeed in competitive examinations.--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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SYLLABUS
Objectives:
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The student should be made to:? Understand the various logic gates.
? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
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? Learn to use HDLList of experiments:
1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
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3. Design and implementation of combinational circuits using MSI devices:a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
c. Magnitude Comparator
d. Application using multiplexers
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4. Design and implementation of sequential circuits:a. Shift ?registers
b. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
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Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
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? Design the different functional units in a digital computer system.? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Content
Sl.No. Name of the Experiment Page No.
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1.Verification of Boolean Theorems using Digital Logic Gates
2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
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3.
Implementation of half adder and full adder
4.
Implementation of half subtractor and full subtractor
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5.Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
6.
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Design and Implementation of Parity Generator / Checker using Basic Gates and MSIDevices
7.
Design and Implementation of Magnitude Comparator.
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8.Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
Design and Implementation of Shift Registers.
10.
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Design and Implementation of Synchronous and Asynchronous Counters.11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
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12.Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.1: STUDY OF BASIC GATES
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Aim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. NAND gate IC 7400 1
6. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
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AND gateThe AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
low.
OR gate
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The OR gate performs a logical addition commonly known as OR function. The output ishigh when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
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NAND gateThe NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
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output is low when one or both inputs are high.EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
EXOR Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
th
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pin is grounded and 14th
pin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
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Result:
The truth tables of all the basic logic gates were verified.
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Outcome:At the completion of an experiment student will able to verify the truth
table of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
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3. How many gates presented in IC 7408?4. What is IC?
5. What are the applications of gates?
6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
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8. Write the truth table of NOT gate.9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
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13. What are types of linear integrated circuit?14. What is meant by etching?
15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.2:
VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gates
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. NAND gate IC 7400 1
6. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
BASIC Boolean Laws
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1. Commutative Law
The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
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2. A.B=B.A2. Associative Law
The binary operator OR, AND is said to be associative if,
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1. A+(B+C) = (A+B)+C2. A.(B.C) = (A.B).C
3. Distributive Law
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The binary operator OR, AND is said to be distributive if,1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
4. Absorption Law
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1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
1. A+A = A
2. A.A = A
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6. Complementary Law
1. A+A' = 1
2. A.A' = 0
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7. De Morgan ?s Theorem
1. The complement of the sum is equal to the sum of the product of the individual
complements.
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A+B = A.B2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design1. Absorption Law
A+AB = A
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2. Involution (or) Double complement Law
A = A
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3. Idempotent Law
1. A+A = A
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2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:004. Demorgan ?s Law
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A+B = A.B
5. Distributive Law
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A+(B.C) = (A+B).(A+C)Procedure:
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
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cc.
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
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Result:
Thus the above stated Boolean laws are verified.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?2. What is associative law?
3. What is mean by compliment gate?
4. Explain the basic laws in digital electronics
5. What is double complement?
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Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
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To design and verify the truth table of the Half Adder & Full Adder circuitsApparatus required:
S. No. Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
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6. Connecting wires As requiredTheory:
The most basic arithmetic operation is the addition of two binary digits. There are four
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possible elementary operations, namely,0 + 0 = 0
0 + 1 = 1
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1 + 0 = 1
1 + 1 = 0 (with 1 as carry)
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The first three operations produce a sum of whose length is one digit, but when the last operation isperformed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
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designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.Full adder:
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
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with two half adders and one OR gate.From the truth table, the expression for sum and carry bits of the output can be obtained as,
SUM = A?B?C + A?BC? + AB?C? + ABC
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CARRY = A?BC + AB?C + ABC? +ABC16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half Adder
Truth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
S = A B
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Carry, C = A . BCircuit diagram:
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Full adder
Truth table:
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Sl.No. Input OutputA B C S C
1. 0 0 0 0 0
2. 0 0 1 1 0
3. 0 1 0 1 0
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4. 0 1 1 0 15. 1 0 0 1 0
6. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input Output
A B S C
1. 0 0 0 0
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2. 0 1 1 03. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Sum:--- Content provided by FirstRanker.com ---
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B CCarry:
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--- Content provided by FirstRanker.com ---
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CARRY = AB + AC + BC
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Logic Diagram:18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections are given as per the circuit diagrams.
--- Content provided by FirstRanker.com ---
2. For all the IC?s 7th
pin is grounded and 14
th
pin is given +5 V supply.
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3. Apply the inputs and verify the truth table for the half adder and full adder circuits.Result:
The design of the half adder and full adder circuits was done and their truth tables were verified.
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Outcome:At the completion of an experiment student will able to design the half adder circuit and the
full adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTORAim:
To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
--- Content provided by FirstRanker.com ---
4. NOT gate IC 7404 15. EX-OR gate IC 7486 1
6. Connecting wires As required
Theory:
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The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bitis subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
subtrahend bit, hence 1 is borrowed.
Half subtractor:
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A combinational circuit which performs the subtraction of two bits is called half subtractor. The inputvariables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
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three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can beimplemented with two half subtractors and one OR gate.
From the truth table the expression for difference and borrow bits of the output can be obtained
as,
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Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
Borrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half subtractor
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Truth table:
Sl.No. Input Output
A B Difference Borrow
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1. 0 0 0 02. 0 1 1 1
3. 1 0 1 0
4. 1 1 0 0
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From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A B
Borrow, BORR = A?. B
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Logic diagram:
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2. Full subtractor
Truth table:
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Sl.No.
Input Output
A B C Difference Borrow
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1. 0 0 0 0 02. 0 0 1 1 1
3. 0 1 0 1 1
4. 0 1 1 0 1
5. 1 0 0 1 0
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6. 1 0 1 0 07. 1 1 0 0 0
8. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
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Borrow--- Content provided by FirstRanker.com ---
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Borrow = A?B + A?C + BC
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Circuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
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Aim:To design and implement 4-bit adder and subtractor using IC 7483
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. IC IC 7483 1
3. NOT gate IC 7404 1
4. EX-OR gate IC 7486 1
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5. Connecting wires As requiredTheory:
4 BIT Binary adder:
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A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected to
the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
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carries are connected in chain through full adder. The input carry to the adder is C0
and it ripples through
the full adder to the output carry C
4
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.4 BIT Binary subtractor:
The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
?B? and the corresponding input of full adder. The input carry C
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0must be equal to 1 when performing
subtraction.
4 BIT Binary adder / subtractor:
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The addition and subtraction operation can be combined into one circuit with one common binaryadder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
becomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PIN Diagram for IC 7483:
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Logic Diagram: 4-Bit Binary Diagram:Logic diagram: 4-Bit Binary Subtractor:
4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:
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Procedure:
1. Connections are given as per the circuit diagrams.
2. Logical inputs were given as per circuit diagram.
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3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor..
Result:
The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
verified.
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Outcome:At the completion of an experiment student will able to design 4-bit binary adder and subtractor
Input Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
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1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 01 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
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1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 11 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
1. What is expression for difference and borrow?
2. Write the truth table for half adder.
3. Write the truth table for full adder.
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4. Write the truth table for half subtrator.5. Write the truth table for full subtrator.
6. Draw the logic diagram of full subtrator.
7. What is adder?
8. List out the application of adders.
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9. Draw the full adder using two half adder circuits.10. What is combinational circuit?
11. What is different between combinational and sequential circuit?
12. What are the gates involved for binary adder?
13. List the properties of Ex-Nor gate?
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14. What is expression for sum and carry?--- Content provided by FirstRanker.com ---
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.6: MAGNITUDE COMPARATORAim:
To design, construct and study the performance of 2 bit magnitude comparator
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. Magnitude comparator IC 7485 26. EX-OR gate IC 7486 1
7. Connecting wires As required
Theory:
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The comparison of two numbers is an operator that determines one number is greater than, less
than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
three binary variables that indicate whether A>B, A=B (or) A
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Truth table:--- Content provided by FirstRanker.com ---
27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Logic Diagram:
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Pin Diagram for IC 7485:
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
8 Bit Magnitude Comparator:
Truth table:
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Procedure:
1. Connections are given as per circuit diagram.
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2. Logical inputs are given as per circuit diagram.3. Observe the output and verify the truth table.
Result:
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Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.Outcome:
At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
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comparator using logic gates.--- Content provided by FirstRanker.com ---
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A B A>B A=B A0 0 0 0
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0 0 0 00 0 0 0
0 0 0 0
0 1 0
0 0 0 1
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0 0 0 10 0 0 0
0 0 0 0
1 0 0
0 0 0 0
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0 0 0 00 0 0 1
0 0 0 1
0 0 1
Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is magnitude comparator?2. What is most significant bit?
3. Explain operation of AND gate.
4. Explain truth table of a comparator.
5. Explain magnitude comparator7485 IC.
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6. What is 8-bit input Magnitude Comparator?7. What is IC?
8. Explain the k-map simplification of A>B.
9. Explain the k-map simplification of A=B.
10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
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12. What is the truth table of 1-bit magnitude comparator?13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION
FirstRanker.com - FirstRanker's Choice
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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
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III SEMESTER - R 2017CS8382 DIGITAL SYSTEMS LABORATORY
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Name : _______________________________________Register No : _______________________________________
Section : _______________________________________
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LABORATORY MANUAL
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2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
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training.--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
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? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag onheart and soul
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DEPARTMENT OF COMPUTER SCIENCE ENGINEERING--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
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? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
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? To produce electrical engineers of high calibre, conscious of the universal moral values adhering toprofessional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
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VISION
MISSION
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VISION
MISSION
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3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
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1. FundamentalsTo provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
2. Core Competence
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To train the students to meet the needs of core industry with an attitude of learning newtechnologies.
3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
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enable them to find solutions to problems in industry and research that contributes to the overalldevelopment of society.
4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
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team and stand as a good decision maker to manage any constraint environment with goodprofessional ethics at all strategies.
5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
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commitment and lifelong learning needed for successful professional career.--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM OUTCOMES (POs)
a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
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b. Graduates will be able to identify, formulate and solve electrical engineering problems.c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
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analyze problems.g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
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j. Graduates will develop confidence for self-education and ability for lifelong learning.k. Graduate who can participate and succeed in competitive examinations.
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CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00SYLLABUS
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Objectives:The student should be made to:
? Understand the various logic gates.
? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
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? Be exposed to sequential circuits? Learn to use HDL
List of experiments:
1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
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functions, code converters.3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
c. Magnitude Comparator
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d. Application using multiplexers4. Design and implementation of sequential circuits:
a. Shift ?registers
b. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
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6. Design and implementation of a simple digital system (Mini Project).Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
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? Analyze a given digital circuit ? combinational and sequential.? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Content
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Sl.No. Name of the Experiment Page No.1.
Verification of Boolean Theorems using Digital Logic Gates
2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
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Functions, Code Converters3.
Implementation of half adder and full adder
4.
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Implementation of half subtractor and full subtractor5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
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6.Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
7.
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Design and Implementation of Magnitude Comparator.8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
Design and Implementation of Shift Registers.
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10.Design and Implementation of Synchronous and Asynchronous Counters.
11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
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12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.1: STUDY OF BASIC GATESAim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
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8. Connecting wires As requiredTheory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
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universal gates. Basic gates form these gates.AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
low.
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OR gateThe OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
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called an inverter. The output is high when the input is low. The output is low when the input is high.NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
NOR gate
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The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. Theoutput is low when one or both inputs are high.
EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
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OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NAND Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
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thpin is grounded and 14
th
pin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
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Result:
The truth tables of all the basic logic gates were verified.
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Outcome:
At the completion of an experiment student will able to verify the truth
table of all basic gates
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1. List out the basic gate.
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2. Mention the universal gate.3. How many gates presented in IC 7408?
4. What is IC?
5. What are the applications of gates?
6. Write the truth table of AND gate.
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7. Write the truth table of OR gate.8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
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12. What are the classifications of IC?13. What are types of linear integrated circuit?
14. What is meant by etching?
15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
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Viva ? Voce--- Content provided by FirstRanker.com ---
12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.2:
VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
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GATESAim: To verification of Boolean theorems using logic gates
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
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8. Connecting wires As requiredTheory:
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BASIC Boolean Laws1. Commutative Law
The binary operator OR, AND is said to be commutative if,
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1. A+B = B+A2. A.B=B.A
2. Associative Law
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The binary operator OR, AND is said to be associative if,1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
3. Distributive Law
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The binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
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4. Absorption Law1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
1. A+A = A
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2. A.A = A6. Complementary Law
1. A+A' = 1
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2. A.A' = 07. De Morgan ?s Theorem
1. The complement of the sum is equal to the sum of the product of the individual
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complements.A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design
1. Absorption Law
A+AB = A
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2. Involution (or) Double complement Law
A = A
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3. Idempotent Law
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1. A+A = A2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s LawA+B = A.B
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5. Distributive LawA+(B.C) = (A+B).(A+C)
Procedure:
1. Obtain the required IC along with the Digital trainer kit.
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2. Connect zero volts to GND pin and +5 volts to Vcc
.
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
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Result:
Thus the above stated Boolean laws are verified.
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Outcome:At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?
2. What is associative law?
3. What is mean by compliment gate?
4. Explain the basic laws in digital electronics
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5. What is double complement?Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.3: HALF ADDER AND FULL ADDER
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Aim:To design and verify the truth table of the Half Adder & Full Adder circuits
Apparatus required:
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S. No. Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. EX-OR gate IC 7486 16. Connecting wires As required
Theory:
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The most basic arithmetic operation is the addition of two binary digits. There are fourpossible elementary operations, namely,
0 + 0 = 0
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0 + 1 = 11 + 0 = 1
1 + 1 = 0 (with 1 as carry)
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The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
Half adder:
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A combinational circuit which performs the addition of two bits is called half adder. The input variablesdesignate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
Full adder:
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
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three input bits include two significant bits and a previous carry bit. A full adder circuit can be implementedwith two half adders and one OR gate.
From the truth table, the expression for sum and carry bits of the output can be obtained as,
SUM = A?B?C + A?BC? + AB?C? + ABC
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CARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Half Adder
Truth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
S = A B
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Carry, C = A . B
Circuit diagram:
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Full adder
Truth table:
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Sl.No. Input Output
A B C S C
1. 0 0 0 0 0
2. 0 0 1 1 0
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3. 0 1 0 1 04. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
7. 1 1 0 0 1
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8. 1 1 1 1 1Sl.No. Input Output
A B S C
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1. 0 0 0 02. 0 1 1 0
3. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
Carry:
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CARRY = AB + AC + BC
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Logic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Procedure:
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1. Connections are given as per the circuit diagrams.2. For all the IC?s 7
th
pin is grounded and 14
th
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pin is given +5 V supply.3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
Result:
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The design of the half adder and full adder circuits was done and their truth tables were verified.Outcome:
At the completion of an experiment student will able to design the half adder circuit and the
full adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
Aim:
To design and verify the truth table of the half subtractor & full subtractor circuits
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
subtrahend bit, hence 1 is borrowed.
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Half subtractor:A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
Full subtractor:
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A combinational circuit which performs the subtraction of three input bits is called full subtractor. Thethree input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
From the truth table the expression for difference and borrow bits of the output can be obtained
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as,Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
Borrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half subtractorTruth table:
Sl.No. Input Output
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A B Difference Borrow1. 0 0 0 0
2. 0 1 1 1
3. 1 0 1 0
4. 1 1 0 0
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From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A B
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Borrow, BORR = A?. BLogic diagram:
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2. Full subtractor
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Truth table:Sl.No.
Input Output
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A B C Difference Borrow1. 0 0 0 0 0
2. 0 0 1 1 1
3. 0 1 0 1 1
4. 0 1 1 0 1
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5. 1 0 0 1 06. 1 0 1 0 0
7. 1 1 0 0 0
8. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
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Borrow
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Borrow = A?B + A?C + BC
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Circuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
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Aim:
To design and implement 4-bit adder and subtractor using IC 7483
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. IC IC 7483 1
3. NOT gate IC 7404 1
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4. EX-OR gate IC 7486 15. Connecting wires As required
Theory:
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4 BIT Binary adder:A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected to
the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
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designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. Thecarries are connected in chain through full adder. The input carry to the adder is C
0
and it ripples through
the full adder to the output carry C
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4.
4 BIT Binary subtractor:
The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
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?B? and the corresponding input of full adder. The input carry C0
must be equal to 1 when performing
subtraction.
4 BIT Binary adder / subtractor:
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The addition and subtraction operation can be combined into one circuit with one common binary
adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
becomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PIN Diagram for IC 7483:
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Logic Diagram: 4-Bit Binary Diagram:
Logic diagram: 4-Bit Binary Subtractor:
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4-Bit Binary Adder /Subtractor:24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:
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Procedure:
1. Connections are given as per the circuit diagrams.
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2. Logical inputs were given as per circuit diagram.3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
.
Result:
The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
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verified.Outcome:
At the completion of an experiment student will able to design 4-bit binary adder and subtractor
Input Data A Input Data B Addition Subtraction
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A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D11 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
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1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 11 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?
2. Write the truth table for half adder.
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3. Write the truth table for full adder.4. Write the truth table for half subtrator.
5. Write the truth table for full subtrator.
6. Draw the logic diagram of full subtrator.
7. What is adder?
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8. List out the application of adders.9. Draw the full adder using two half adder circuits.
10. What is combinational circuit?
11. What is different between combinational and sequential circuit?
12. What are the gates involved for binary adder?
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13. List the properties of Ex-Nor gate?14. What is expression for sum and carry?
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.6: MAGNITUDE COMPARATOR
Aim:
To design, construct and study the performance of 2 bit magnitude comparator
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:The comparison of two numbers is an operator that determines one number is greater than, less
than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
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three binary variables that indicate whether A>B, A=B (or) ATruth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K-map--- Content provided by FirstRanker.com ---
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:Pin Diagram for IC 7485:
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:
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Truth table:--- Content provided by FirstRanker.com ---
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Procedure:
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1. Connections are given as per circuit diagram.2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
Result:
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Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
Outcome:
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At the completion of an experiment student will able to design the 2-bit and 8-bit magnitudecomparator using logic gates.
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A B A>B A=B A0 0 0 00 0 0 0
0 0 0 0
0 0 0 0
0 1 0
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0 0 0 10 0 0 1
0 0 0 0
0 0 0 0
1 0 0
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0 0 0 00 0 0 0
0 0 0 1
0 0 0 1
0 0 1
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Viva ? Voce--- Content provided by FirstRanker.com ---
30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
1. What is magnitude comparator?
2. What is most significant bit?
3. Explain operation of AND gate.
4. Explain truth table of a comparator.
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5. Explain magnitude comparator7485 IC.6. What is 8-bit input Magnitude Comparator?
7. What is IC?
8. Explain the k-map simplification of A>B.
9. Explain the k-map simplification of A=B.
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10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.12. What is the truth table of 1-bit magnitude comparator?
13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION
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31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Aim:
To design, construct and study the performance of 4-bit different code converters
(i) Binary to gray code converter
(ii) Gray to binary code converter
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(iii) BCD to excess-3 code converter(iv) Excess-3 to BCD code converter
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. Magnitude comparator IC 7485 26. EX-OR gate IC 7486 1
7. Connecting wires As required
Theory:
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The availability of large variety of codes for the same discrete elements of information results in
the use of different codes by different systems. A conversion circuit must be inserted between the two
systems if each uses different codes for same information. Thus, code converter is a circuit that makes the
two systems compatible even though each uses different binary code. The bit combination assigned to
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binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputsand four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a
circuit that makes the two systems compatible even though each uses a different binary code. To convert
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from binary code to Excess-3 code, the input lines must supply the bit combination of elements asspecified by code and the output lines generate the corresponding bit combination of code. Each one of the
four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are
various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is
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C+D has been used to implement partially each of three outputs.Logic diagram:
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FirstRanker.com - FirstRanker's Choice1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
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III SEMESTER - R 2017
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
Section : _______________________________________
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LABORATORY MANUAL
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2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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is committed to provide highly disciplined, conscientious and
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enterprising professionals conforming to global standards through value based quality education andtraining.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
--- Content provided by FirstRanker.com ---
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
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needs.? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
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industry by continuous assessment and training.VISION
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MISSIONVISION
MISSION
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3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
--- Content provided by FirstRanker.com ---
1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
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2. Core CompetenceTo train the students to meet the needs of core industry with an attitude of learning new
technologies.
3. Breadth
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To provide relevant training and experience to bridge the gap between theory and practice whichenable them to find solutions to problems in industry and research that contributes to the overall
development of society.
4. Professionalism
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To inculcate professional and effective communication skills to the students to make them lead ateam and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
5. Lifelong Learning/Ethics
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To practice ethical and professional responsibilities in the organization and society withcommitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
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f. Graduates will demonstrate skills to use modern engineering tools, software and equipment toanalyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
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will be aware of contemporary issues.j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
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CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
SYLLABUS
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Objectives:
The student should be made to:
? Understand the various logic gates.
? Be familiar with various combinational circuits.
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? Understand the various components used in the design of digital computers.? Be exposed to sequential circuits
? Learn to use HDL
List of experiments:
1. Verification of Boolean Theorems using basic gates.
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2. Design and implementation of combinational circuits using basic gates for arbitraryfunctions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
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c. Magnitude Comparatord. Application using multiplexers
4. Design and implementation of sequential circuits:
a. Shift ?registers
b. Synchronous and asynchronous counters
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5. Coding combinational / sequential circuits using HDL.6. Design and implementation of a simple digital system (Mini Project).
Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
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? Design and Implement combinational and sequential circuits.? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Content
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Sl.No. Name of the Experiment Page No.
1.
Verification of Boolean Theorems using Digital Logic Gates
2.
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Design and Implementation of Combinational Circuits using Basic Gates for ArbitraryFunctions, Code Converters
3.
Implementation of half adder and full adder
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4.Implementation of half subtractor and full subtractor
5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
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6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
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7.Design and Implementation of Magnitude Comparator.
8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
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Design and Implementation of Shift Registers.10.
Design and Implementation of Synchronous and Asynchronous Counters.
11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
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HDL Software Required).12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.1: STUDY OF BASIC GATES
Aim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
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7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
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more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known asuniversal gates. Basic gates form these gates.
AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
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low.OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
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A NOT gate is the physical realization of the complementation operation. The NOT gate iscalled an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
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NOR gateThe NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
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similar to OR gate but excludes the combination of both A and B being equal to one. The exclusiveOR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Procedure:
1. Connections are given as per the circuit diagram.
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2. For all the IC?s 7th
pin is grounded and 14
th
pin is given +5 supply.
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3. Apply the inputs and verify the truth table for all gates.Result:
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The truth tables of all the basic logic gates were verified.Outcome:
At the completion of an experiment student will able to verify the truth
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table of all basic gates--- Content provided by FirstRanker.com ---
1. List out the basic gate.2. Mention the universal gate.
3. How many gates presented in IC 7408?
4. What is IC?
5. What are the applications of gates?
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6. Write the truth table of AND gate.7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
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11. Write the truth table of EX- OR gate.12. What are the classifications of IC?
13. What are types of linear integrated circuit?
14. What is meant by etching?
15. What are the advantages of IC?
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16. Write the truth table of EX- NOR gate.Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.2:
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VERIFICATION OF BOOLEAN THEOREMS USING LOGICGATES
Aim: To verification of Boolean theorems using logic gates
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 3
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7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
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BASIC Boolean Laws
1. Commutative Law
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The binary operator OR, AND is said to be commutative if,1. A+B = B+A
2. A.B=B.A
2. Associative Law
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The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
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3. Distributive LawThe binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
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4. Absorption Law
1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
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1. A+A = A2. A.A = A
6. Complementary Law
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1. A+A' = 12. A.A' = 0
7. De Morgan ?s Theorem
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1. The complement of the sum is equal to the sum of the product of the individualcomplements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design
1. Absorption Law
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A+AB = A--- Content provided by FirstRanker.com ---
2. Involution (or) Double complement Law
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A = A--- Content provided by FirstRanker.com ---
3. Idempotent Law
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1. A+A = A
2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
A+B = A.B
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5. Distributive Law
A+(B.C) = (A+B).(A+C)
Procedure:
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1. Obtain the required IC along with the Digital trainer kit.2. Connect zero volts to GND pin and +5 volts to V
cc
.
3. Apply the inputs to the respective input pins.
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4. Verify the output with the truth table.Result:
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Thus the above stated Boolean laws are verified.Outcome:
At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?
2. What is associative law?
3. What is mean by compliment gate?
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4. Explain the basic laws in digital electronics5. What is double complement?
Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.3: HALF ADDER AND FULL ADDERAim:
To design and verify the truth table of the Half Adder & Full Adder circuits
Apparatus required:
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S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
0 + 0 = 0
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0 + 1 = 1
1 + 0 = 1
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1 + 1 = 0 (with 1 as carry)The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
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Half adder:A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
Full adder:
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A combinational circuit which performs the arithmetic sum of three input bits is called full adder. Thethree input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
From the truth table, the expression for sum and carry bits of the output can be obtained as,
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SUM = A?B?C + A?BC? + AB?C? + ABCCARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half Adder
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Truth table:--- Content provided by FirstRanker.com ---
From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
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S = A BCarry, C = A . B
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Circuit diagram:--- Content provided by FirstRanker.com ---
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Full adder
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Truth table:Sl.No. Input Output
A B C S C
1. 0 0 0 0 0
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2. 0 0 1 1 03. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
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7. 1 1 0 0 18. 1 1 1 1 1
Sl.No. Input Output
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A B S C1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:--- Content provided by FirstRanker.com ---
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CARRY = AB + AC + BC
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Logic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
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1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
th
pin is grounded and 14
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thpin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
Result:
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The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
At the completion of an experiment student will able to design the half adder circuit and the
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full adder circuit.--- Content provided by FirstRanker.com ---
19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
Aim:
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To design and verify the truth table of the half subtractor & full subtractor circuitsApparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
subtrahend bit, hence 1 is borrowed.
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Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
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Full subtractor:A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
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From the truth table the expression for difference and borrow bits of the output can be obtainedas,
Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
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Borrow, BORR = A?BC + AB?C + ABC? +ABC--- Content provided by FirstRanker.com ---
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half subtractor
Truth table:
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Sl.No. Input OutputA B Difference Borrow
1. 0 0 0 0
2. 0 1 1 1
3. 1 0 1 0
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4. 1 1 0 0From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A B
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Borrow, BORR = A?. B
Logic diagram:
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2. Full subtractorTruth table:
Sl.No.
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Input OutputA B C Difference Borrow
1. 0 0 0 0 0
2. 0 0 1 1 1
3. 0 1 0 1 1
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4. 0 1 1 0 15. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
8. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
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Borrow
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Borrow = A?B + A?C + BCCircuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
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Aim:
To design and implement 4-bit adder and subtractor using IC 7483
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. IC IC 7483 1
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3. NOT gate IC 7404 14. EX-OR gate IC 7486 1
5. Connecting wires As required
Theory:
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4 BIT Binary adder:
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected to
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the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? aredesignated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
0
and it ripples through
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the full adder to the output carry C4
.
4 BIT Binary subtractor:
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The circuit for subtracting A-B consists of an adder with inverters, placed between each data input?B? and the corresponding input of full adder. The input carry C
0
must be equal to 1 when performing
subtraction.
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4 BIT Binary adder / subtractor:The addition and subtraction operation can be combined into one circuit with one common binary
adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
becomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PIN Diagram for IC 7483:Logic Diagram: 4-Bit Binary Diagram:
Logic diagram: 4-Bit Binary Subtractor:
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4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Truth table:
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Procedure:
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1. Connections are given as per the circuit diagrams.2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
.
Result:
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The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table wasverified.
Outcome:
At the completion of an experiment student will able to design 4-bit binary adder and subtractor
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Input Data A Input Data B Addition SubtractionA4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
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0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 01 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?
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2. Write the truth table for half adder.3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
5. Write the truth table for full subtrator.
6. Draw the logic diagram of full subtrator.
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7. What is adder?8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
10. What is combinational circuit?
11. What is different between combinational and sequential circuit?
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12. What are the gates involved for binary adder?13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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Viva ? Voce--- Content provided by FirstRanker.com ---
26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.6: MAGNITUDE COMPARATOR
Aim:
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To design, construct and study the performance of 2 bit magnitude comparatorApparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:
The comparison of two numbers is an operator that determines one number is greater than, less
than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
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numbers A and B and determines their relative magnitude. The outcome of the comparator is specified bythree binary variables that indicate whether A>B, A=B (or) A
Truth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:
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Pin Diagram for IC 7485:--- Content provided by FirstRanker.com ---
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:
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Truth table:
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Procedure:1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
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Result:Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
Outcome:
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At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
comparator using logic gates.
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A B A>B A=B A0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
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0 1 00 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
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1 0 00 0 0 0
0 0 0 0
0 0 0 1
0 0 0 1
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0 0 1Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is magnitude comparator?
2. What is most significant bit?
3. Explain operation of AND gate.
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4. Explain truth table of a comparator.5. Explain magnitude comparator7485 IC.
6. What is 8-bit input Magnitude Comparator?
7. What is IC?
8. Explain the k-map simplification of A>B.
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9. Explain the k-map simplification of A=B.10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
12. What is the truth table of 1-bit magnitude comparator?
13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Aim:
To design, construct and study the performance of 4-bit different code converters
(i) Binary to gray code converter
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(ii) Gray to binary code converter(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:The availability of large variety of codes for the same discrete elements of information results in
the use of different codes by different systems. A conversion circuit must be inserted between the two
systems if each uses different codes for same information. Thus, code converter is a circuit that makes the
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two systems compatible even though each uses different binary code. The bit combination assigned tobinary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a
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circuit that makes the two systems compatible even though each uses a different binary code. To convertfrom binary code to Excess-3 code, the input lines must supply the bit combination of elements as
specified by code and the output lines generate the corresponding bit combination of code. Each one of the
four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are
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various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output isC+D has been used to implement partially each of three outputs.
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Logic diagram:32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(i) Binary to gray code converter
Logic Diagram:
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K map for G3:
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G3 = B3K map for G2:
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K map for G1:FirstRanker.com - FirstRanker's Choice
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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
?DEPARTMENT OF
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COMPUTER SCIENCE ENGINEERINGIII SEMESTER - R 2017
CS8382 DIGITAL SYSTEMS LABORATORY
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Name : _______________________________________
Register No : _______________________________________
Section : _______________________________________
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LABORATORY MANUAL
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2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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is committed to provide highly disciplined, conscientious andenterprising professionals conforming to global standards through value based quality education and
training.
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? To provide competent technical manpower capable of meeting requirements of the industry
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
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levels? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
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DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
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To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
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Electrical and Electronics Engineers.--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?sneeds.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
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concepts with strongly supported laboratory and prepare them to meet the global needs of theindustry by continuous assessment and training.
VISION
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MISSION
VISION
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MISSION--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
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1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
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2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
technologies.
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3. BreadthTo provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
development of society.
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4. ProfessionalismTo inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
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5. Lifelong Learning/EthicsTo practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
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e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
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i. Graduates will show the understanding of impact of engineering solutions on the society and alsowill be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
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CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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SYLLABUSObjectives:
The student should be made to:
? Understand the various logic gates.
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? Be familiar with various combinational circuits.? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
? Learn to use HDL
List of experiments:
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1. Verification of Boolean Theorems using basic gates.2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
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b. Parity generator / checkerc. Magnitude Comparator
d. Application using multiplexers
4. Design and implementation of sequential circuits:
a. Shift ?registers
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b. Synchronous and asynchronous counters5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
Course Outcomes:
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? Use Boolean simplification techniques to design a combinational hardware circuit.? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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ContentSl.No. Name of the Experiment Page No.
1.
Verification of Boolean Theorems using Digital Logic Gates
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2.Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
3.
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Implementation of half adder and full adder4.
Implementation of half subtractor and full subtractor
5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
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MSI Devices6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
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7.
Design and Implementation of Magnitude Comparator.
8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
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9.Design and Implementation of Shift Registers.
10.
Design and Implementation of Synchronous and Asynchronous Counters.
11.
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Simulation of Combinational Circuits using Hardware Description Language (VHDL / VerilogHDL Software Required).
12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.1: STUDY OF BASIC GATES
Aim:
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To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gatesApparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
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6. NOR gate IC 7402 17. EX-OR gate IC 7486 1
8. Connecting wires As required
Theory:
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Circuit that takes the logical decision and the process are called logic gates. Each gate has one ormore input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
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output is high when both the inputs are high. The output is low level when any one of the inputs islow.
OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
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NOT gateA NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
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and any one of the input is low .The output is low level when both inputs are high.NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
EX-OR gate
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An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It issimilar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
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1. Connections are given as per the circuit diagram.2. For all the IC?s 7
th
pin is grounded and 14
th
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pin is given +5 supply.3. Apply the inputs and verify the truth table for all gates.
Result:
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The truth tables of all the basic logic gates were verified.
Outcome:
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At the completion of an experiment student will able to verify the truthtable of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
3. How many gates presented in IC 7408?
4. What is IC?
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5. What are the applications of gates?6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
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10. Write the truth table of NOR gate.11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
13. What are types of linear integrated circuit?
14. What is meant by etching?
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15. What are the advantages of IC?16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.2:
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VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gatesApparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
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6. NOR gate IC 7402 37. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:BASIC Boolean Laws
1. Commutative Law
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The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A
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2. Associative LawThe binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
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3. Distributive Law
The binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
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2. A.(B+C) = (A.B)+(A.C)4. Absorption Law
1. A+AB = A
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:005. Idempotent Law
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1. A+A = A
2. A.A = A
6. Complementary Law
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1. A+A' = 1
2. A.A' = 0
7. De Morgan ?s Theorem
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1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
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A.B = A+BDesign
1. Absorption Law
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A+AB = A
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2. Involution (or) Double complement Law
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A = A
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3. Idempotent Law1. A+A = A
2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
A+B = A.B
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5. Distributive Law
A+(B.C) = (A+B).(A+C)
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Procedure:1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
cc
.
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3. Apply the inputs to the respective input pins.4. Verify the output with the truth table.
Result:
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Thus the above stated Boolean laws are verified.
Outcome:
At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?
2. What is associative law?
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3. What is mean by compliment gate?4. Explain the basic laws in digital electronics
5. What is double complement?
Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
To design and verify the truth table of the Half Adder & Full Adder circuits
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Apparatus required:S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:
The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
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0 + 0 = 00 + 1 = 1
1 + 0 = 1
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1 + 1 = 0 (with 1 as carry)
The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
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significant bit is called the sum.Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
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Full adder:A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
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From the truth table, the expression for sum and carry bits of the output can be obtained as,SUM = A?B?C + A?BC? + AB?C? + ABC
CARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half AdderTruth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,S = A B
Carry, C = A . B
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Circuit diagram:
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Full adderTruth table:
Sl.No. Input Output
A B C S C
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1. 0 0 0 0 02. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
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6. 1 0 1 0 17. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input OutputA B S C
1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
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4. 1 1 1 117 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:
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CARRY = AB + AC + BCLogic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
th
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pin is grounded and 14th
pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
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Result:The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
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At the completion of an experiment student will able to design the half adder circuit and thefull adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
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Aim:To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
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6. Connecting wires As requiredTheory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
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subtrahend bit, hence 1 is borrowed.Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
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difference and borrow bits.Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
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From the truth table the expression for difference and borrow bits of the output can be obtained
as,
Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
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Borrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Half subtractor
Truth table:
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Sl.No. Input Output
A B Difference Borrow
1. 0 0 0 0
2. 0 1 1 1
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3. 1 0 1 04. 1 1 0 0
From the truth table the expression for difference and borrow bits of the output can be obtained as,
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Difference, DIFF = A BBorrow, BORR = A?. B
Logic diagram:
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2. Full subtractor
Truth table:
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Sl.No.Input Output
A B C Difference Borrow
1. 0 0 0 0 0
2. 0 0 1 1 1
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3. 0 1 0 1 14. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Difference = A?B?C + A?BC? + AB?C? + ABCBorrow
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Borrow = A?B + A?C + BC
Circuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.5: 4-BIT ADDER AND SUBTRACTORAim:
To design and implement 4-bit adder and subtractor using IC 7483
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. IC IC 7483 13. NOT gate IC 7404 1
4. EX-OR gate IC 7486 1
5. Connecting wires As required
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Theory:4 BIT Binary adder:
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
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constructed with full adders connected in cascade, with the output carry from each full adder connected tothe input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
0
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and it ripples throughthe full adder to the output carry C
4
.
4 BIT Binary subtractor:
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The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
?B? and the corresponding input of full adder. The input carry C
0
must be equal to 1 when performing
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subtraction.4 BIT Binary adder / subtractor:
The addition and subtraction operation can be combined into one circuit with one common binary
adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
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becomes subtractor.23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PIN Diagram for IC 7483:
Logic Diagram: 4-Bit Binary Diagram:
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Logic diagram: 4-Bit Binary Subtractor:4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:--- Content provided by FirstRanker.com ---
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Procedure:1. Connections are given as per the circuit diagrams.
2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
.
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Result:The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
verified.
Outcome:
At the completion of an experiment student will able to design 4-bit binary adder and subtractor
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Input Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
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0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 00 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?2. Write the truth table for half adder.
3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
5. Write the truth table for full subtrator.
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6. Draw the logic diagram of full subtrator.7. What is adder?
8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
10. What is combinational circuit?
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11. What is different between combinational and sequential circuit?12. What are the gates involved for binary adder?
13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.6: MAGNITUDE COMPARATOR
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Aim:To design, construct and study the performance of 2 bit magnitude comparator
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
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7. Connecting wires As requiredTheory:
The comparison of two numbers is an operator that determines one number is greater than, less
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than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares twonumbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
three binary variables that indicate whether A>B, A=B (or) A
Truth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Logic Diagram:
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Pin Diagram for IC 7485:
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:
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Truth table:
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Procedure:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
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Result:
Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
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Outcome:At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
comparator using logic gates.
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A B A>B A=B A0 0 0 0
0 0 0 0
0 0 0 0
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0 0 0 00 1 0
0 0 0 1
0 0 0 1
0 0 0 0
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0 0 0 01 0 0
0 0 0 0
0 0 0 0
0 0 0 1
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0 0 0 10 0 1
Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is magnitude comparator?
2. What is most significant bit?
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3. Explain operation of AND gate.4. Explain truth table of a comparator.
5. Explain magnitude comparator7485 IC.
6. What is 8-bit input Magnitude Comparator?
7. What is IC?
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8. Explain the k-map simplification of A>B.9. Explain the k-map simplification of A=B.
10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
12. What is the truth table of 1-bit magnitude comparator?
13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION
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31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Aim:
To design, construct and study the performance of 4-bit different code converters
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(i) Binary to gray code converter(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:
The availability of large variety of codes for the same discrete elements of information results in
the use of different codes by different systems. A conversion circuit must be inserted between the two
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systems if each uses different codes for same information. Thus, code converter is a circuit that makes thetwo systems compatible even though each uses different binary code. The bit combination assigned to
binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
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designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is acircuit that makes the two systems compatible even though each uses a different binary code. To convert
from binary code to Excess-3 code, the input lines must supply the bit combination of elements as
specified by code and the output lines generate the corresponding bit combination of code. Each one of the
four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
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level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These arevarious other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is
C+D has been used to implement partially each of three outputs.
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Logic diagram:
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32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00(i) Binary to gray code converter
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Logic Diagram:K map for G3:
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G3 = B3
K map for G2:
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K map for G1:
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33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
K map for G0:
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Truth table:0
0
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00
0
0
0
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01
1
1
1
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11
1
1
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00
0
0
1
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11
1
0
0
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00
1
1
1
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10
0
1
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10
0
1
1
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00
1
1
0
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01
1
0
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10
1
0
1
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01
0
1
0
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10
1
0
1
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0
0
0
0
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00
0
0
1
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11
1
1
1
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11
0
0
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00
1
1
1
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11
1
1
1
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00
0
0
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00
1
1
1
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10
0
0
0
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11
1
1
0
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00
1
1
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00
1
1
0
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01
1
0
0
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11
0
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(ii) Gray to binary code converter
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FirstRanker.com - FirstRanker's Choice1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
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III SEMESTER - R 2017
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
Section : _______________________________________
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LABORATORY MANUAL
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2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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is committed to provide highly disciplined, conscientious and
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enterprising professionals conforming to global standards through value based quality education andtraining.
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? To provide competent technical manpower capable of meeting requirements of the industry
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
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? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
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DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
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? To provide the students rigorous learning experience to produce creative solutions to society?s
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needs.? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
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industry by continuous assessment and training.VISION
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MISSIONVISION
MISSION
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3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
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1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
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2. Core CompetenceTo train the students to meet the needs of core industry with an attitude of learning new
technologies.
3. Breadth
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To provide relevant training and experience to bridge the gap between theory and practice whichenable them to find solutions to problems in industry and research that contributes to the overall
development of society.
4. Professionalism
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To inculcate professional and effective communication skills to the students to make them lead ateam and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
5. Lifelong Learning/Ethics
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To practice ethical and professional responsibilities in the organization and society withcommitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
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f. Graduates will demonstrate skills to use modern engineering tools, software and equipment toanalyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
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will be aware of contemporary issues.j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
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--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
SYLLABUS
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Objectives:
The student should be made to:
? Understand the various logic gates.
? Be familiar with various combinational circuits.
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? Understand the various components used in the design of digital computers.? Be exposed to sequential circuits
? Learn to use HDL
List of experiments:
1. Verification of Boolean Theorems using basic gates.
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2. Design and implementation of combinational circuits using basic gates for arbitraryfunctions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
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c. Magnitude Comparatord. Application using multiplexers
4. Design and implementation of sequential circuits:
a. Shift ?registers
b. Synchronous and asynchronous counters
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5. Coding combinational / sequential circuits using HDL.6. Design and implementation of a simple digital system (Mini Project).
Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
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? Design and Implement combinational and sequential circuits.? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Content
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Sl.No. Name of the Experiment Page No.
1.
Verification of Boolean Theorems using Digital Logic Gates
2.
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Design and Implementation of Combinational Circuits using Basic Gates for ArbitraryFunctions, Code Converters
3.
Implementation of half adder and full adder
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4.Implementation of half subtractor and full subtractor
5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
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6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
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7.Design and Implementation of Magnitude Comparator.
8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
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Design and Implementation of Shift Registers.10.
Design and Implementation of Synchronous and Asynchronous Counters.
11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
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HDL Software Required).12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.1: STUDY OF BASIC GATES
Aim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
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7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
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more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known asuniversal gates. Basic gates form these gates.
AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
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low.OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
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A NOT gate is the physical realization of the complementation operation. The NOT gate iscalled an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
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NOR gateThe NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
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similar to OR gate but excludes the combination of both A and B being equal to one. The exclusiveOR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Procedure:
1. Connections are given as per the circuit diagram.
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2. For all the IC?s 7th
pin is grounded and 14
th
pin is given +5 supply.
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3. Apply the inputs and verify the truth table for all gates.Result:
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The truth tables of all the basic logic gates were verified.Outcome:
At the completion of an experiment student will able to verify the truth
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table of all basic gates--- Content provided by FirstRanker.com ---
1. List out the basic gate.2. Mention the universal gate.
3. How many gates presented in IC 7408?
4. What is IC?
5. What are the applications of gates?
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6. Write the truth table of AND gate.7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
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11. Write the truth table of EX- OR gate.12. What are the classifications of IC?
13. What are types of linear integrated circuit?
14. What is meant by etching?
15. What are the advantages of IC?
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16. Write the truth table of EX- NOR gate.Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.2:
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VERIFICATION OF BOOLEAN THEOREMS USING LOGICGATES
Aim: To verification of Boolean theorems using logic gates
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 3
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7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
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BASIC Boolean Laws
1. Commutative Law
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The binary operator OR, AND is said to be commutative if,1. A+B = B+A
2. A.B=B.A
2. Associative Law
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The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
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3. Distributive LawThe binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
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4. Absorption Law
1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
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1. A+A = A2. A.A = A
6. Complementary Law
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1. A+A' = 12. A.A' = 0
7. De Morgan ?s Theorem
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1. The complement of the sum is equal to the sum of the product of the individualcomplements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design
1. Absorption Law
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A+AB = A--- Content provided by FirstRanker.com ---
2. Involution (or) Double complement Law
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A = A--- Content provided by FirstRanker.com ---
3. Idempotent Law
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1. A+A = A
2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
A+B = A.B
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5. Distributive Law
A+(B.C) = (A+B).(A+C)
Procedure:
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1. Obtain the required IC along with the Digital trainer kit.2. Connect zero volts to GND pin and +5 volts to V
cc
.
3. Apply the inputs to the respective input pins.
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4. Verify the output with the truth table.Result:
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Thus the above stated Boolean laws are verified.Outcome:
At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?
2. What is associative law?
3. What is mean by compliment gate?
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4. Explain the basic laws in digital electronics5. What is double complement?
Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.3: HALF ADDER AND FULL ADDERAim:
To design and verify the truth table of the Half Adder & Full Adder circuits
Apparatus required:
--- Content provided by FirstRanker.com ---
S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
0 + 0 = 0
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0 + 1 = 1
1 + 0 = 1
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1 + 1 = 0 (with 1 as carry)The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
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Half adder:A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
Full adder:
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A combinational circuit which performs the arithmetic sum of three input bits is called full adder. Thethree input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
From the truth table, the expression for sum and carry bits of the output can be obtained as,
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SUM = A?B?C + A?BC? + AB?C? + ABCCARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half Adder
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Truth table:--- Content provided by FirstRanker.com ---
From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
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S = A BCarry, C = A . B
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Circuit diagram:--- Content provided by FirstRanker.com ---
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Full adder
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Truth table:Sl.No. Input Output
A B C S C
1. 0 0 0 0 0
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2. 0 0 1 1 03. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
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7. 1 1 0 0 18. 1 1 1 1 1
Sl.No. Input Output
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A B S C1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:--- Content provided by FirstRanker.com ---
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CARRY = AB + AC + BC
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Logic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
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1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
th
pin is grounded and 14
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thpin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
Result:
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The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
At the completion of an experiment student will able to design the half adder circuit and the
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full adder circuit.--- Content provided by FirstRanker.com ---
19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
Aim:
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To design and verify the truth table of the half subtractor & full subtractor circuitsApparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
--- Content provided by FirstRanker.com ---
2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
subtrahend bit, hence 1 is borrowed.
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Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
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Full subtractor:A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
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From the truth table the expression for difference and borrow bits of the output can be obtainedas,
Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
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Borrow, BORR = A?BC + AB?C + ABC? +ABC--- Content provided by FirstRanker.com ---
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half subtractor
Truth table:
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Sl.No. Input OutputA B Difference Borrow
1. 0 0 0 0
2. 0 1 1 1
3. 1 0 1 0
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4. 1 1 0 0From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A B
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Borrow, BORR = A?. B
Logic diagram:
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2. Full subtractorTruth table:
Sl.No.
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Input OutputA B C Difference Borrow
1. 0 0 0 0 0
2. 0 0 1 1 1
3. 0 1 0 1 1
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4. 0 1 1 0 15. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
8. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
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Borrow
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--- Content provided by FirstRanker.com ---
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Borrow = A?B + A?C + BCCircuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
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Aim:
To design and implement 4-bit adder and subtractor using IC 7483
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. IC IC 7483 1
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3. NOT gate IC 7404 14. EX-OR gate IC 7486 1
5. Connecting wires As required
Theory:
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4 BIT Binary adder:
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected to
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the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? aredesignated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
0
and it ripples through
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the full adder to the output carry C4
.
4 BIT Binary subtractor:
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The circuit for subtracting A-B consists of an adder with inverters, placed between each data input?B? and the corresponding input of full adder. The input carry C
0
must be equal to 1 when performing
subtraction.
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4 BIT Binary adder / subtractor:The addition and subtraction operation can be combined into one circuit with one common binary
adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
becomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PIN Diagram for IC 7483:Logic Diagram: 4-Bit Binary Diagram:
Logic diagram: 4-Bit Binary Subtractor:
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4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Truth table:
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Procedure:
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1. Connections are given as per the circuit diagrams.2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
.
Result:
--- Content provided by FirstRanker.com ---
The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table wasverified.
Outcome:
At the completion of an experiment student will able to design 4-bit binary adder and subtractor
--- Content provided by FirstRanker.com ---
Input Data A Input Data B Addition SubtractionA4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
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0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 01 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?
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2. Write the truth table for half adder.3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
5. Write the truth table for full subtrator.
6. Draw the logic diagram of full subtrator.
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7. What is adder?8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
10. What is combinational circuit?
11. What is different between combinational and sequential circuit?
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12. What are the gates involved for binary adder?13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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Viva ? Voce--- Content provided by FirstRanker.com ---
26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.6: MAGNITUDE COMPARATOR
Aim:
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To design, construct and study the performance of 2 bit magnitude comparatorApparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
--- Content provided by FirstRanker.com ---
3. OR gate IC 7432 14. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:
The comparison of two numbers is an operator that determines one number is greater than, less
than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
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numbers A and B and determines their relative magnitude. The outcome of the comparator is specified bythree binary variables that indicate whether A>B, A=B (or) A
Truth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:
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Pin Diagram for IC 7485:--- Content provided by FirstRanker.com ---
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:
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Truth table:
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Procedure:1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
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Result:Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
comparator using logic gates.
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--- Content provided by FirstRanker.com ---
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A B A>B A=B A0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
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0 1 00 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
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1 0 00 0 0 0
0 0 0 0
0 0 0 1
0 0 0 1
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0 0 1Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
1. What is magnitude comparator?
2. What is most significant bit?
3. Explain operation of AND gate.
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4. Explain truth table of a comparator.5. Explain magnitude comparator7485 IC.
6. What is 8-bit input Magnitude Comparator?
7. What is IC?
8. Explain the k-map simplification of A>B.
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9. Explain the k-map simplification of A=B.10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
12. What is the truth table of 1-bit magnitude comparator?
13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Aim:
To design, construct and study the performance of 4-bit different code converters
(i) Binary to gray code converter
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(ii) Gray to binary code converter(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
--- Content provided by FirstRanker.com ---
4. NOT gate IC 7404 15. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:The availability of large variety of codes for the same discrete elements of information results in
the use of different codes by different systems. A conversion circuit must be inserted between the two
systems if each uses different codes for same information. Thus, code converter is a circuit that makes the
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two systems compatible even though each uses different binary code. The bit combination assigned tobinary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a
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circuit that makes the two systems compatible even though each uses a different binary code. To convertfrom binary code to Excess-3 code, the input lines must supply the bit combination of elements as
specified by code and the output lines generate the corresponding bit combination of code. Each one of the
four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are
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various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output isC+D has been used to implement partially each of three outputs.
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Logic diagram:32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(i) Binary to gray code converter
Logic Diagram:
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K map for G3:
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G3 = B3K map for G2:
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K map for G1:33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for G0:Truth table:
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0
0
0
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00
0
0
0
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11
1
1
1
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11
1
0
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00
0
1
1
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11
0
0
0
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01
1
1
1
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0
0
1
1
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00
1
1
0
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01
1
0
0
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11
0
1
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01
0
1
0
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10
1
0
1
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01
0
1
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00
0
0
0
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00
0
1
1
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11
1
1
1
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10
0
0
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01
1
1
1
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11
1
1
0
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00
0
0
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01
1
1
1
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00
0
0
1
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11
1
0
0
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0
1
1
0
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01
1
0
0
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11
0
0
1
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10
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(ii) Gray to binary code converter
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34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:K map for B3:
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B3=G3
K map for B2:
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FirstRanker.com - FirstRanker's Choice
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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
III SEMESTER - R 2017CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________Register No : _______________________________________
Section : _______________________________________
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LABORATORY MANUAL
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2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
--- Content provided by FirstRanker.com ---
training.--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
--- Content provided by FirstRanker.com ---
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag onheart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
--- Content provided by FirstRanker.com ---
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering toprofessional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
--- Content provided by FirstRanker.com ---
VISION
MISSION
--- Content provided by FirstRanker.com ---
VISION
MISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
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1. FundamentalsTo provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
2. Core Competence
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To train the students to meet the needs of core industry with an attitude of learning newtechnologies.
3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
--- Content provided by FirstRanker.com ---
enable them to find solutions to problems in industry and research that contributes to the overalldevelopment of society.
4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
--- Content provided by FirstRanker.com ---
team and stand as a good decision maker to manage any constraint environment with goodprofessional ethics at all strategies.
5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
--- Content provided by FirstRanker.com ---
commitment and lifelong learning needed for successful professional career.--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM OUTCOMES (POs)
a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
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b. Graduates will be able to identify, formulate and solve electrical engineering problems.c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
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analyze problems.g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
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j. Graduates will develop confidence for self-education and ability for lifelong learning.k. Graduate who can participate and succeed in competitive examinations.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00SYLLABUS
--- Content provided by FirstRanker.com ---
Objectives:The student should be made to:
? Understand the various logic gates.
? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
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? Be exposed to sequential circuits? Learn to use HDL
List of experiments:
1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
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functions, code converters.3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
c. Magnitude Comparator
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d. Application using multiplexers4. Design and implementation of sequential circuits:
a. Shift ?registers
b. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
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6. Design and implementation of a simple digital system (Mini Project).Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
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? Analyze a given digital circuit ? combinational and sequential.? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Content
--- Content provided by FirstRanker.com ---
Sl.No. Name of the Experiment Page No.1.
Verification of Boolean Theorems using Digital Logic Gates
2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
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Functions, Code Converters3.
Implementation of half adder and full adder
4.
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Implementation of half subtractor and full subtractor5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
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6.Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
7.
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Design and Implementation of Magnitude Comparator.8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
Design and Implementation of Shift Registers.
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10.Design and Implementation of Synchronous and Asynchronous Counters.
11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
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12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.1: STUDY OF BASIC GATESAim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
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8. Connecting wires As requiredTheory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
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universal gates. Basic gates form these gates.AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
low.
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OR gateThe OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
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called an inverter. The output is high when the input is low. The output is low when the input is high.NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
NOR gate
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The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. Theoutput is low when one or both inputs are high.
EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
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OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NAND Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
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thpin is grounded and 14
th
pin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
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Result:
The truth tables of all the basic logic gates were verified.
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Outcome:
At the completion of an experiment student will able to verify the truth
table of all basic gates
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1. List out the basic gate.
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2. Mention the universal gate.3. How many gates presented in IC 7408?
4. What is IC?
5. What are the applications of gates?
6. Write the truth table of AND gate.
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7. Write the truth table of OR gate.8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
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12. What are the classifications of IC?13. What are types of linear integrated circuit?
14. What is meant by etching?
15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
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Viva ? Voce--- Content provided by FirstRanker.com ---
12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.2:
VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
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GATESAim: To verification of Boolean theorems using logic gates
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
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8. Connecting wires As requiredTheory:
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BASIC Boolean Laws1. Commutative Law
The binary operator OR, AND is said to be commutative if,
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1. A+B = B+A2. A.B=B.A
2. Associative Law
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The binary operator OR, AND is said to be associative if,1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
3. Distributive Law
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The binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
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4. Absorption Law1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
1. A+A = A
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2. A.A = A6. Complementary Law
1. A+A' = 1
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2. A.A' = 07. De Morgan ?s Theorem
1. The complement of the sum is equal to the sum of the product of the individual
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complements.A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design
1. Absorption Law
A+AB = A
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2. Involution (or) Double complement Law
A = A
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3. Idempotent Law
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1. A+A = A2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s LawA+B = A.B
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5. Distributive LawA+(B.C) = (A+B).(A+C)
Procedure:
1. Obtain the required IC along with the Digital trainer kit.
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2. Connect zero volts to GND pin and +5 volts to Vcc
.
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
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Result:
Thus the above stated Boolean laws are verified.
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Outcome:At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?
2. What is associative law?
3. What is mean by compliment gate?
4. Explain the basic laws in digital electronics
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5. What is double complement?Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.3: HALF ADDER AND FULL ADDER
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Aim:To design and verify the truth table of the Half Adder & Full Adder circuits
Apparatus required:
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S. No. Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. EX-OR gate IC 7486 16. Connecting wires As required
Theory:
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The most basic arithmetic operation is the addition of two binary digits. There are fourpossible elementary operations, namely,
0 + 0 = 0
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0 + 1 = 11 + 0 = 1
1 + 1 = 0 (with 1 as carry)
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The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
Half adder:
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A combinational circuit which performs the addition of two bits is called half adder. The input variablesdesignate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
Full adder:
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
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three input bits include two significant bits and a previous carry bit. A full adder circuit can be implementedwith two half adders and one OR gate.
From the truth table, the expression for sum and carry bits of the output can be obtained as,
SUM = A?B?C + A?BC? + AB?C? + ABC
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CARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Half Adder
Truth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
S = A B
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Carry, C = A . B
Circuit diagram:
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Full adder
Truth table:
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Sl.No. Input Output
A B C S C
1. 0 0 0 0 0
2. 0 0 1 1 0
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3. 0 1 0 1 04. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
7. 1 1 0 0 1
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8. 1 1 1 1 1Sl.No. Input Output
A B S C
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1. 0 0 0 02. 0 1 1 0
3. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
Carry:
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CARRY = AB + AC + BC
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Logic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Procedure:
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1. Connections are given as per the circuit diagrams.2. For all the IC?s 7
th
pin is grounded and 14
th
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pin is given +5 V supply.3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
Result:
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The design of the half adder and full adder circuits was done and their truth tables were verified.Outcome:
At the completion of an experiment student will able to design the half adder circuit and the
full adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
Aim:
To design and verify the truth table of the half subtractor & full subtractor circuits
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
subtrahend bit, hence 1 is borrowed.
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Half subtractor:A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
Full subtractor:
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A combinational circuit which performs the subtraction of three input bits is called full subtractor. Thethree input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
From the truth table the expression for difference and borrow bits of the output can be obtained
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as,Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
Borrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half subtractorTruth table:
Sl.No. Input Output
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A B Difference Borrow1. 0 0 0 0
2. 0 1 1 1
3. 1 0 1 0
4. 1 1 0 0
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From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A B
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Borrow, BORR = A?. BLogic diagram:
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2. Full subtractor
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Truth table:Sl.No.
Input Output
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A B C Difference Borrow1. 0 0 0 0 0
2. 0 0 1 1 1
3. 0 1 0 1 1
4. 0 1 1 0 1
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5. 1 0 0 1 06. 1 0 1 0 0
7. 1 1 0 0 0
8. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
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Borrow
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Borrow = A?B + A?C + BC
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Circuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
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Aim:
To design and implement 4-bit adder and subtractor using IC 7483
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. IC IC 7483 1
3. NOT gate IC 7404 1
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4. EX-OR gate IC 7486 15. Connecting wires As required
Theory:
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4 BIT Binary adder:A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected to
the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
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designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. Thecarries are connected in chain through full adder. The input carry to the adder is C
0
and it ripples through
the full adder to the output carry C
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4.
4 BIT Binary subtractor:
The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
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?B? and the corresponding input of full adder. The input carry C0
must be equal to 1 when performing
subtraction.
4 BIT Binary adder / subtractor:
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The addition and subtraction operation can be combined into one circuit with one common binary
adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
becomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PIN Diagram for IC 7483:
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Logic Diagram: 4-Bit Binary Diagram:
Logic diagram: 4-Bit Binary Subtractor:
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4-Bit Binary Adder /Subtractor:24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:
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Procedure:
1. Connections are given as per the circuit diagrams.
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2. Logical inputs were given as per circuit diagram.3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
.
Result:
The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
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verified.Outcome:
At the completion of an experiment student will able to design 4-bit binary adder and subtractor
Input Data A Input Data B Addition Subtraction
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A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D11 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
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1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 11 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?
2. Write the truth table for half adder.
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3. Write the truth table for full adder.4. Write the truth table for half subtrator.
5. Write the truth table for full subtrator.
6. Draw the logic diagram of full subtrator.
7. What is adder?
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8. List out the application of adders.9. Draw the full adder using two half adder circuits.
10. What is combinational circuit?
11. What is different between combinational and sequential circuit?
12. What are the gates involved for binary adder?
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13. List the properties of Ex-Nor gate?14. What is expression for sum and carry?
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.6: MAGNITUDE COMPARATOR
Aim:
To design, construct and study the performance of 2 bit magnitude comparator
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:The comparison of two numbers is an operator that determines one number is greater than, less
than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
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three binary variables that indicate whether A>B, A=B (or) ATruth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K-map--- Content provided by FirstRanker.com ---
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:Pin Diagram for IC 7485:
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:
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Procedure:
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1. Connections are given as per circuit diagram.2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
Result:
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Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
Outcome:
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At the completion of an experiment student will able to design the 2-bit and 8-bit magnitudecomparator using logic gates.
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A B A>B A=B A0 0 0 00 0 0 0
0 0 0 0
0 0 0 0
0 1 0
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0 0 0 10 0 0 1
0 0 0 0
0 0 0 0
1 0 0
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0 0 0 00 0 0 0
0 0 0 1
0 0 0 1
0 0 1
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Viva ? Voce--- Content provided by FirstRanker.com ---
30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
1. What is magnitude comparator?
2. What is most significant bit?
3. Explain operation of AND gate.
4. Explain truth table of a comparator.
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5. Explain magnitude comparator7485 IC.6. What is 8-bit input Magnitude Comparator?
7. What is IC?
8. Explain the k-map simplification of A>B.
9. Explain the k-map simplification of A=B.
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10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.12. What is the truth table of 1-bit magnitude comparator?
13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION
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31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Aim:
To design, construct and study the performance of 4-bit different code converters
(i) Binary to gray code converter
(ii) Gray to binary code converter
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(iii) BCD to excess-3 code converter(iv) Excess-3 to BCD code converter
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. Magnitude comparator IC 7485 26. EX-OR gate IC 7486 1
7. Connecting wires As required
Theory:
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The availability of large variety of codes for the same discrete elements of information results in
the use of different codes by different systems. A conversion circuit must be inserted between the two
systems if each uses different codes for same information. Thus, code converter is a circuit that makes the
two systems compatible even though each uses different binary code. The bit combination assigned to
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binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputsand four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a
circuit that makes the two systems compatible even though each uses a different binary code. To convert
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from binary code to Excess-3 code, the input lines must supply the bit combination of elements asspecified by code and the output lines generate the corresponding bit combination of code. Each one of the
four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are
various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is
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C+D has been used to implement partially each of three outputs.Logic diagram:
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32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(i) Binary to gray code converter
Logic Diagram:
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K map for G3:
G3 = B3
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K map for G2:--- Content provided by FirstRanker.com ---
K map for G1:
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33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for G0:
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Truth table:
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0
0
0
0
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00
0
0
1
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11
1
1
1
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11
0
0
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00
1
1
1
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10
0
0
0
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11
1
1
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00
1
1
0
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01
1
0
0
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11
0
0
1
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10
1
0
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10
1
0
1
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01
0
1
0
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10
1
0
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00
0
0
0
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00
1
1
1
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11
1
1
1
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0
0
0
0
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11
1
1
1
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11
1
0
0
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00
0
0
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11
1
1
0
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00
0
1
1
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11
0
0
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01
1
0
0
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11
0
0
1
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10
0
1
1
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0--- Content provided by FirstRanker.com ---
(ii) Gray to binary code converter
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34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Logic Diagram:
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K map for B3:
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B3=G3
K map for B2:
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
G3 G2 G1 G0 B3 B2 B1 B0
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00
0
0
0
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00
0
1
1
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11
1
1
1
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10
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0
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01
1
1
1
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11
1
1
0
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00
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0
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01
1
1
1
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00
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1
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11
1
0
0
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0
1
1
0
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01
1
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0
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11
0
0
1
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10
0
0
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00
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0
0
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01
1
1
1
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11
1
1
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00
0
0
1
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11
1
0
0
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00
1
1
1
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10
0
1
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10
0
1
1
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00
1
1
0
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01
1
0
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10
1
0
1
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01
0
1
0
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10
1
0
1
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K map for B1:
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K map for B0:Truth table:
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FirstRanker.com - FirstRanker's Choice
--- Content provided by FirstRanker.com ---
1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
--- Content provided by FirstRanker.com ---
DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
III SEMESTER - R 2017CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________Register No : _______________________________________
Section : _______________________________________
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LABORATORY MANUAL
--- Content provided by FirstRanker.com ---
2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
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training.--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
--- Content provided by FirstRanker.com ---
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag onheart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
--- Content provided by FirstRanker.com ---
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering toprofessional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
--- Content provided by FirstRanker.com ---
VISION
MISSION
--- Content provided by FirstRanker.com ---
VISION
MISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
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1. FundamentalsTo provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
2. Core Competence
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To train the students to meet the needs of core industry with an attitude of learning newtechnologies.
3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
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enable them to find solutions to problems in industry and research that contributes to the overalldevelopment of society.
4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
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team and stand as a good decision maker to manage any constraint environment with goodprofessional ethics at all strategies.
5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
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commitment and lifelong learning needed for successful professional career.--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM OUTCOMES (POs)
a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
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b. Graduates will be able to identify, formulate and solve electrical engineering problems.c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
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analyze problems.g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
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j. Graduates will develop confidence for self-education and ability for lifelong learning.k. Graduate who can participate and succeed in competitive examinations.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00SYLLABUS
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Objectives:The student should be made to:
? Understand the various logic gates.
? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
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? Be exposed to sequential circuits? Learn to use HDL
List of experiments:
1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
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functions, code converters.3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
c. Magnitude Comparator
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d. Application using multiplexers4. Design and implementation of sequential circuits:
a. Shift ?registers
b. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
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6. Design and implementation of a simple digital system (Mini Project).Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
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? Analyze a given digital circuit ? combinational and sequential.? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Content
--- Content provided by FirstRanker.com ---
Sl.No. Name of the Experiment Page No.1.
Verification of Boolean Theorems using Digital Logic Gates
2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
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Functions, Code Converters3.
Implementation of half adder and full adder
4.
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Implementation of half subtractor and full subtractor5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
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6.Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
7.
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Design and Implementation of Magnitude Comparator.8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
Design and Implementation of Shift Registers.
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10.Design and Implementation of Synchronous and Asynchronous Counters.
11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
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12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.1: STUDY OF BASIC GATESAim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
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8. Connecting wires As requiredTheory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
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universal gates. Basic gates form these gates.AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
low.
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OR gateThe OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
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called an inverter. The output is high when the input is low. The output is low when the input is high.NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
NOR gate
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The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. Theoutput is low when one or both inputs are high.
EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
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OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NAND Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
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thpin is grounded and 14
th
pin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
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Result:
The truth tables of all the basic logic gates were verified.
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Outcome:
At the completion of an experiment student will able to verify the truth
table of all basic gates
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1. List out the basic gate.
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2. Mention the universal gate.3. How many gates presented in IC 7408?
4. What is IC?
5. What are the applications of gates?
6. Write the truth table of AND gate.
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7. Write the truth table of OR gate.8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
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12. What are the classifications of IC?13. What are types of linear integrated circuit?
14. What is meant by etching?
15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
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Viva ? Voce--- Content provided by FirstRanker.com ---
12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.2:
VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
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GATESAim: To verification of Boolean theorems using logic gates
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
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8. Connecting wires As requiredTheory:
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BASIC Boolean Laws1. Commutative Law
The binary operator OR, AND is said to be commutative if,
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1. A+B = B+A2. A.B=B.A
2. Associative Law
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The binary operator OR, AND is said to be associative if,1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
3. Distributive Law
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The binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
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4. Absorption Law1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
1. A+A = A
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2. A.A = A6. Complementary Law
1. A+A' = 1
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2. A.A' = 07. De Morgan ?s Theorem
1. The complement of the sum is equal to the sum of the product of the individual
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complements.A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design
1. Absorption Law
A+AB = A
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2. Involution (or) Double complement Law
A = A
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3. Idempotent Law
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1. A+A = A2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s LawA+B = A.B
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5. Distributive LawA+(B.C) = (A+B).(A+C)
Procedure:
1. Obtain the required IC along with the Digital trainer kit.
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2. Connect zero volts to GND pin and +5 volts to Vcc
.
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
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Result:
Thus the above stated Boolean laws are verified.
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Outcome:At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?
2. What is associative law?
3. What is mean by compliment gate?
4. Explain the basic laws in digital electronics
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5. What is double complement?Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.3: HALF ADDER AND FULL ADDER
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Aim:To design and verify the truth table of the Half Adder & Full Adder circuits
Apparatus required:
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S. No. Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. EX-OR gate IC 7486 16. Connecting wires As required
Theory:
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The most basic arithmetic operation is the addition of two binary digits. There are fourpossible elementary operations, namely,
0 + 0 = 0
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0 + 1 = 11 + 0 = 1
1 + 1 = 0 (with 1 as carry)
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The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
Half adder:
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A combinational circuit which performs the addition of two bits is called half adder. The input variablesdesignate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
Full adder:
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
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three input bits include two significant bits and a previous carry bit. A full adder circuit can be implementedwith two half adders and one OR gate.
From the truth table, the expression for sum and carry bits of the output can be obtained as,
SUM = A?B?C + A?BC? + AB?C? + ABC
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CARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Half Adder
Truth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
S = A B
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Carry, C = A . B
Circuit diagram:
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Full adder
Truth table:
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Sl.No. Input Output
A B C S C
1. 0 0 0 0 0
2. 0 0 1 1 0
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3. 0 1 0 1 04. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
7. 1 1 0 0 1
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8. 1 1 1 1 1Sl.No. Input Output
A B S C
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1. 0 0 0 02. 0 1 1 0
3. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
Carry:
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CARRY = AB + AC + BC
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Logic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Procedure:
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1. Connections are given as per the circuit diagrams.2. For all the IC?s 7
th
pin is grounded and 14
th
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pin is given +5 V supply.3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
Result:
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The design of the half adder and full adder circuits was done and their truth tables were verified.Outcome:
At the completion of an experiment student will able to design the half adder circuit and the
full adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
Aim:
To design and verify the truth table of the half subtractor & full subtractor circuits
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
subtrahend bit, hence 1 is borrowed.
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Half subtractor:A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
Full subtractor:
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A combinational circuit which performs the subtraction of three input bits is called full subtractor. Thethree input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
From the truth table the expression for difference and borrow bits of the output can be obtained
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as,Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
Borrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half subtractorTruth table:
Sl.No. Input Output
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A B Difference Borrow1. 0 0 0 0
2. 0 1 1 1
3. 1 0 1 0
4. 1 1 0 0
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From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A B
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Borrow, BORR = A?. BLogic diagram:
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2. Full subtractor
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Truth table:Sl.No.
Input Output
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A B C Difference Borrow1. 0 0 0 0 0
2. 0 0 1 1 1
3. 0 1 0 1 1
4. 0 1 1 0 1
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5. 1 0 0 1 06. 1 0 1 0 0
7. 1 1 0 0 0
8. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
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Borrow
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Borrow = A?B + A?C + BC
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Circuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
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Aim:
To design and implement 4-bit adder and subtractor using IC 7483
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. IC IC 7483 1
3. NOT gate IC 7404 1
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4. EX-OR gate IC 7486 15. Connecting wires As required
Theory:
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4 BIT Binary adder:A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected to
the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
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designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. Thecarries are connected in chain through full adder. The input carry to the adder is C
0
and it ripples through
the full adder to the output carry C
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4.
4 BIT Binary subtractor:
The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
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?B? and the corresponding input of full adder. The input carry C0
must be equal to 1 when performing
subtraction.
4 BIT Binary adder / subtractor:
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The addition and subtraction operation can be combined into one circuit with one common binary
adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
becomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PIN Diagram for IC 7483:
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Logic Diagram: 4-Bit Binary Diagram:
Logic diagram: 4-Bit Binary Subtractor:
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4-Bit Binary Adder /Subtractor:24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:
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Procedure:
1. Connections are given as per the circuit diagrams.
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2. Logical inputs were given as per circuit diagram.3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
.
Result:
The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
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verified.Outcome:
At the completion of an experiment student will able to design 4-bit binary adder and subtractor
Input Data A Input Data B Addition Subtraction
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A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D11 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
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1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 11 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?
2. Write the truth table for half adder.
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3. Write the truth table for full adder.4. Write the truth table for half subtrator.
5. Write the truth table for full subtrator.
6. Draw the logic diagram of full subtrator.
7. What is adder?
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8. List out the application of adders.9. Draw the full adder using two half adder circuits.
10. What is combinational circuit?
11. What is different between combinational and sequential circuit?
12. What are the gates involved for binary adder?
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13. List the properties of Ex-Nor gate?14. What is expression for sum and carry?
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.6: MAGNITUDE COMPARATOR
Aim:
To design, construct and study the performance of 2 bit magnitude comparator
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:The comparison of two numbers is an operator that determines one number is greater than, less
than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
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three binary variables that indicate whether A>B, A=B (or) ATruth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K-map--- Content provided by FirstRanker.com ---
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:Pin Diagram for IC 7485:
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:
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Truth table:--- Content provided by FirstRanker.com ---
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Procedure:
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1. Connections are given as per circuit diagram.2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
Result:
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Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
Outcome:
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At the completion of an experiment student will able to design the 2-bit and 8-bit magnitudecomparator using logic gates.
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A B A>B A=B A0 0 0 00 0 0 0
0 0 0 0
0 0 0 0
0 1 0
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0 0 0 10 0 0 1
0 0 0 0
0 0 0 0
1 0 0
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0 0 0 00 0 0 0
0 0 0 1
0 0 0 1
0 0 1
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Viva ? Voce--- Content provided by FirstRanker.com ---
30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
1. What is magnitude comparator?
2. What is most significant bit?
3. Explain operation of AND gate.
4. Explain truth table of a comparator.
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5. Explain magnitude comparator7485 IC.6. What is 8-bit input Magnitude Comparator?
7. What is IC?
8. Explain the k-map simplification of A>B.
9. Explain the k-map simplification of A=B.
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10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.12. What is the truth table of 1-bit magnitude comparator?
13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION
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31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Aim:
To design, construct and study the performance of 4-bit different code converters
(i) Binary to gray code converter
(ii) Gray to binary code converter
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(iii) BCD to excess-3 code converter(iv) Excess-3 to BCD code converter
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. Magnitude comparator IC 7485 26. EX-OR gate IC 7486 1
7. Connecting wires As required
Theory:
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The availability of large variety of codes for the same discrete elements of information results in
the use of different codes by different systems. A conversion circuit must be inserted between the two
systems if each uses different codes for same information. Thus, code converter is a circuit that makes the
two systems compatible even though each uses different binary code. The bit combination assigned to
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binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputsand four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a
circuit that makes the two systems compatible even though each uses a different binary code. To convert
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from binary code to Excess-3 code, the input lines must supply the bit combination of elements asspecified by code and the output lines generate the corresponding bit combination of code. Each one of the
four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are
various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is
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C+D has been used to implement partially each of three outputs.Logic diagram:
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32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(i) Binary to gray code converter
Logic Diagram:
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K map for G3:
G3 = B3
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K map for G2:--- Content provided by FirstRanker.com ---
K map for G1:
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33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for G0:
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Truth table:
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0
0
0
0
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00
0
0
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
11
0
0
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00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
0
0
0
0
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11
1
1
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
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0--- Content provided by FirstRanker.com ---
(ii) Gray to binary code converter
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34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Logic Diagram:
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K map for B3:
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B3=G3
K map for B2:
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
G3 G2 G1 G0 B3 B2 B1 B0
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00
0
0
0
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00
0
1
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
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11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
0
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
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11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
0
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00
0
0
0
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01
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
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11
1
0
0
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00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
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10
1
0
1
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01
0
1
0
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10
1
0
1
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K map for B1:
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K map for B0:Truth table:
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
(iii) BCD to excess-3 code converter
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Logic Diagram:
K map for E3:
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E3 = B3 + B2 (B0 + B1)
K map for E2:
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FirstRanker.com - FirstRanker's Choice
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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
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CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
Name : _______________________________________
--- Content provided by FirstRanker.com ---
Register No : _______________________________________Section : _______________________________________
--- Content provided by FirstRanker.com ---
LABORATORY MANUAL
--- Content provided by FirstRanker.com ---
2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
training.
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? To provide competent technical manpower capable of meeting requirements of the industry
--- Content provided by FirstRanker.com ---
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
--- Content provided by FirstRanker.com ---
heart and soulDEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and ElectronicsEngineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
--- Content provided by FirstRanker.com ---
professional ethical code.? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
--- Content provided by FirstRanker.com ---
VISION
MISSION
--- Content provided by FirstRanker.com ---
VISIONMISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
1. Fundamentals
--- Content provided by FirstRanker.com ---
To provide students with a solid foundation in mathematics, science and fundamentals ofengineering enabling them to solve complex problems in order to develop real time applications.
2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
--- Content provided by FirstRanker.com ---
technologies.3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
--- Content provided by FirstRanker.com ---
development of society.4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
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professional ethics at all strategies.5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
--- Content provided by FirstRanker.com ---
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM OUTCOMES (POs)a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
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c. Graduates will be able to design and conduct experiments, analyze and interpret data.d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
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g. Graduates will demonstrate knowledge of professional and ethical responsibilities.h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
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k. Graduate who can participate and succeed in competitive examinations.--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
SYLLABUS
Objectives:
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The student should be made to:? Understand the various logic gates.
? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
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? Learn to use HDLList of experiments:
1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
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3. Design and implementation of combinational circuits using MSI devices:a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
c. Magnitude Comparator
d. Application using multiplexers
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4. Design and implementation of sequential circuits:a. Shift ?registers
b. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
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Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
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? Design the different functional units in a digital computer system.? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Content
Sl.No. Name of the Experiment Page No.
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1.Verification of Boolean Theorems using Digital Logic Gates
2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
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3.
Implementation of half adder and full adder
4.
Implementation of half subtractor and full subtractor
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5.Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
6.
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Design and Implementation of Parity Generator / Checker using Basic Gates and MSIDevices
7.
Design and Implementation of Magnitude Comparator.
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8.Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
Design and Implementation of Shift Registers.
10.
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Design and Implementation of Synchronous and Asynchronous Counters.11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
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12.Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.1: STUDY OF BASIC GATES
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Aim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. NAND gate IC 7400 1
6. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
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AND gateThe AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
low.
OR gate
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The OR gate performs a logical addition commonly known as OR function. The output ishigh when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
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NAND gateThe NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
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output is low when one or both inputs are high.EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
EXOR Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
th
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pin is grounded and 14th
pin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
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Result:
The truth tables of all the basic logic gates were verified.
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Outcome:At the completion of an experiment student will able to verify the truth
table of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
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3. How many gates presented in IC 7408?4. What is IC?
5. What are the applications of gates?
6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
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8. Write the truth table of NOT gate.9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
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13. What are types of linear integrated circuit?14. What is meant by etching?
15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.2:
VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gates
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. NAND gate IC 7400 1
6. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
BASIC Boolean Laws
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1. Commutative Law
The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
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2. A.B=B.A2. Associative Law
The binary operator OR, AND is said to be associative if,
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1. A+(B+C) = (A+B)+C2. A.(B.C) = (A.B).C
3. Distributive Law
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The binary operator OR, AND is said to be distributive if,1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
4. Absorption Law
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1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
1. A+A = A
2. A.A = A
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6. Complementary Law
1. A+A' = 1
2. A.A' = 0
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7. De Morgan ?s Theorem
1. The complement of the sum is equal to the sum of the product of the individual
complements.
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A+B = A.B2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design1. Absorption Law
A+AB = A
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2. Involution (or) Double complement Law
A = A
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3. Idempotent Law
1. A+A = A
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2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:004. Demorgan ?s Law
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A+B = A.B
5. Distributive Law
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A+(B.C) = (A+B).(A+C)Procedure:
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
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cc.
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
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Result:
Thus the above stated Boolean laws are verified.
Outcome:
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At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?2. What is associative law?
3. What is mean by compliment gate?
4. Explain the basic laws in digital electronics
5. What is double complement?
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Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
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To design and verify the truth table of the Half Adder & Full Adder circuitsApparatus required:
S. No. Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
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6. Connecting wires As requiredTheory:
The most basic arithmetic operation is the addition of two binary digits. There are four
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possible elementary operations, namely,0 + 0 = 0
0 + 1 = 1
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1 + 0 = 1
1 + 1 = 0 (with 1 as carry)
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The first three operations produce a sum of whose length is one digit, but when the last operation isperformed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
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designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.Full adder:
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
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with two half adders and one OR gate.From the truth table, the expression for sum and carry bits of the output can be obtained as,
SUM = A?B?C + A?BC? + AB?C? + ABC
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CARRY = A?BC + AB?C + ABC? +ABC16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half Adder
Truth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
S = A B
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Carry, C = A . BCircuit diagram:
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Full adder
Truth table:
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Sl.No. Input OutputA B C S C
1. 0 0 0 0 0
2. 0 0 1 1 0
3. 0 1 0 1 0
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4. 0 1 1 0 15. 1 0 0 1 0
6. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input Output
A B S C
1. 0 0 0 0
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2. 0 1 1 03. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Sum:--- Content provided by FirstRanker.com ---
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B CCarry:
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CARRY = AB + AC + BC
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Logic Diagram:18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections are given as per the circuit diagrams.
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2. For all the IC?s 7th
pin is grounded and 14
th
pin is given +5 V supply.
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3. Apply the inputs and verify the truth table for the half adder and full adder circuits.Result:
The design of the half adder and full adder circuits was done and their truth tables were verified.
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Outcome:At the completion of an experiment student will able to design the half adder circuit and the
full adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTORAim:
To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. EX-OR gate IC 7486 1
6. Connecting wires As required
Theory:
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The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bitis subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
subtrahend bit, hence 1 is borrowed.
Half subtractor:
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A combinational circuit which performs the subtraction of two bits is called half subtractor. The inputvariables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
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three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can beimplemented with two half subtractors and one OR gate.
From the truth table the expression for difference and borrow bits of the output can be obtained
as,
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Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
Borrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half subtractor
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Truth table:
Sl.No. Input Output
A B Difference Borrow
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1. 0 0 0 02. 0 1 1 1
3. 1 0 1 0
4. 1 1 0 0
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From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A B
Borrow, BORR = A?. B
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Logic diagram:
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2. Full subtractor
Truth table:
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Sl.No.
Input Output
A B C Difference Borrow
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1. 0 0 0 0 02. 0 0 1 1 1
3. 0 1 0 1 1
4. 0 1 1 0 1
5. 1 0 0 1 0
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6. 1 0 1 0 07. 1 1 0 0 0
8. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
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Borrow = A?B + A?C + BC
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Circuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
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Aim:To design and implement 4-bit adder and subtractor using IC 7483
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. IC IC 7483 1
3. NOT gate IC 7404 1
4. EX-OR gate IC 7486 1
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5. Connecting wires As requiredTheory:
4 BIT Binary adder:
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A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected to
the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
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carries are connected in chain through full adder. The input carry to the adder is C0
and it ripples through
the full adder to the output carry C
4
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.4 BIT Binary subtractor:
The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
?B? and the corresponding input of full adder. The input carry C
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0must be equal to 1 when performing
subtraction.
4 BIT Binary adder / subtractor:
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The addition and subtraction operation can be combined into one circuit with one common binaryadder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
becomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PIN Diagram for IC 7483:
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Logic Diagram: 4-Bit Binary Diagram:Logic diagram: 4-Bit Binary Subtractor:
4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:
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Procedure:
1. Connections are given as per the circuit diagrams.
2. Logical inputs were given as per circuit diagram.
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3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor..
Result:
The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
verified.
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Outcome:At the completion of an experiment student will able to design 4-bit binary adder and subtractor
Input Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
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1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 01 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
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1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 11 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
1. What is expression for difference and borrow?
2. Write the truth table for half adder.
3. Write the truth table for full adder.
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4. Write the truth table for half subtrator.5. Write the truth table for full subtrator.
6. Draw the logic diagram of full subtrator.
7. What is adder?
8. List out the application of adders.
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9. Draw the full adder using two half adder circuits.10. What is combinational circuit?
11. What is different between combinational and sequential circuit?
12. What are the gates involved for binary adder?
13. List the properties of Ex-Nor gate?
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.6: MAGNITUDE COMPARATORAim:
To design, construct and study the performance of 2 bit magnitude comparator
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. Magnitude comparator IC 7485 26. EX-OR gate IC 7486 1
7. Connecting wires As required
Theory:
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The comparison of two numbers is an operator that determines one number is greater than, less
than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
three binary variables that indicate whether A>B, A=B (or) A
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Truth table:--- Content provided by FirstRanker.com ---
27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Logic Diagram:
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Pin Diagram for IC 7485:
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
8 Bit Magnitude Comparator:
Truth table:
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Procedure:
1. Connections are given as per circuit diagram.
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2. Logical inputs are given as per circuit diagram.3. Observe the output and verify the truth table.
Result:
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Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.Outcome:
At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
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comparator using logic gates.--- Content provided by FirstRanker.com ---
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A B A>B A=B A0 0 0 0
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0 0 0 00 0 0 0
0 0 0 0
0 1 0
0 0 0 1
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0 0 0 10 0 0 0
0 0 0 0
1 0 0
0 0 0 0
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0 0 0 00 0 0 1
0 0 0 1
0 0 1
Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is magnitude comparator?2. What is most significant bit?
3. Explain operation of AND gate.
4. Explain truth table of a comparator.
5. Explain magnitude comparator7485 IC.
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6. What is 8-bit input Magnitude Comparator?7. What is IC?
8. Explain the k-map simplification of A>B.
9. Explain the k-map simplification of A=B.
10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
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12. What is the truth table of 1-bit magnitude comparator?13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION
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31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Aim:To design, construct and study the performance of 4-bit different code converters
(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
--- Content provided by FirstRanker.com ---
(iv) Excess-3 to BCD code converterApparatus required:
Sl.No Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
--- Content provided by FirstRanker.com ---
6. EX-OR gate IC 7486 17. Connecting wires As required
Theory:
--- Content provided by FirstRanker.com ---
The availability of large variety of codes for the same discrete elements of information results inthe use of different codes by different systems. A conversion circuit must be inserted between the two
systems if each uses different codes for same information. Thus, code converter is a circuit that makes the
two systems compatible even though each uses different binary code. The bit combination assigned to
binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
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and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a
circuit that makes the two systems compatible even though each uses a different binary code. To convert
from binary code to Excess-3 code, the input lines must supply the bit combination of elements as
--- Content provided by FirstRanker.com ---
specified by code and the output lines generate the corresponding bit combination of code. Each one of thefour maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are
various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is
C+D has been used to implement partially each of three outputs.
--- Content provided by FirstRanker.com ---
Logic diagram:
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32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
(i) Binary to gray code converterLogic Diagram:
--- Content provided by FirstRanker.com ---
K map for G3:G3 = B3
K map for G2:
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K map for G1:
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33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for G0:
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Truth table:
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00
0
0
0
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00
0
1
1
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11
1
1
1
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10
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
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00
0
0
1
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11
1
0
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01
1
0
0
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11
0
0
1
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10
0
1
1
--- Content provided by FirstRanker.com ---
0
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
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10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
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11
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
(ii) Gray to binary code converter
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34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Logic Diagram:
--- Content provided by FirstRanker.com ---
K map for B3:
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B3=G3
K map for B2:
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00G3 G2 G1 G0 B3 B2 B1 B0
0
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00
0
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
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11
1
1
1
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0
0
0
0
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11
1
1
1
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11
1
0
0
--- Content provided by FirstRanker.com ---
00
0
0
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11
1
1
0
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00
0
1
1
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11
0
0
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01
1
0
0
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11
0
0
1
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10
0
1
1
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00
0
0
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00
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
1
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11
1
0
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00
0
1
1
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11
0
0
0
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01
1
1
1
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0
0
1
1
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00
1
1
0
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01
1
0
0
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11
0
1
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01
0
1
0
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10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
--- Content provided by FirstRanker.com ---
K map for B1:K map for B0:
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Truth table:
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
(iii) BCD to excess-3 code converter
--- Content provided by FirstRanker.com ---
Logic Diagram:K map for E3:
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E3 = B3 + B2 (B0 + B1)
K map for E2:
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00K map for E1:
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K map for E0:
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Truth table:
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(iv) Excess-3 to
B3 B2 B1 B0 G3 G2 G1 G0
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0
0
0
0
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00
0
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1
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11
1
1
1
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11
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0
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00
1
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1
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10
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0
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11
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1
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00
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01
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1
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10
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11
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x
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1x
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x
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01
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01
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xx
x
x
x
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xFirstRanker.com - FirstRanker's Choice
--- Content provided by FirstRanker.com ---
1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
?DEPARTMENT OF
--- Content provided by FirstRanker.com ---
COMPUTER SCIENCE ENGINEERINGIII SEMESTER - R 2017
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
Section : _______________________________________
--- Content provided by FirstRanker.com ---
LABORATORY MANUAL
--- Content provided by FirstRanker.com ---
2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious andenterprising professionals conforming to global standards through value based quality education and
training.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
--- Content provided by FirstRanker.com ---
levels? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
--- Content provided by FirstRanker.com ---
Electrical and Electronics Engineers.--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?sneeds.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
--- Content provided by FirstRanker.com ---
concepts with strongly supported laboratory and prepare them to meet the global needs of theindustry by continuous assessment and training.
VISION
--- Content provided by FirstRanker.com ---
MISSION
VISION
--- Content provided by FirstRanker.com ---
MISSION--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
--- Content provided by FirstRanker.com ---
1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
--- Content provided by FirstRanker.com ---
2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
technologies.
--- Content provided by FirstRanker.com ---
3. BreadthTo provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
development of society.
--- Content provided by FirstRanker.com ---
4. ProfessionalismTo inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
--- Content provided by FirstRanker.com ---
5. Lifelong Learning/EthicsTo practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PROGRAM OUTCOMES (POs)
--- Content provided by FirstRanker.com ---
a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
--- Content provided by FirstRanker.com ---
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
--- Content provided by FirstRanker.com ---
i. Graduates will show the understanding of impact of engineering solutions on the society and alsowill be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
SYLLABUSObjectives:
The student should be made to:
? Understand the various logic gates.
--- Content provided by FirstRanker.com ---
? Be familiar with various combinational circuits.? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
? Learn to use HDL
List of experiments:
--- Content provided by FirstRanker.com ---
1. Verification of Boolean Theorems using basic gates.2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
--- Content provided by FirstRanker.com ---
b. Parity generator / checkerc. Magnitude Comparator
d. Application using multiplexers
4. Design and implementation of sequential circuits:
a. Shift ?registers
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b. Synchronous and asynchronous counters5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
Course Outcomes:
--- Content provided by FirstRanker.com ---
? Use Boolean simplification techniques to design a combinational hardware circuit.? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
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--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
ContentSl.No. Name of the Experiment Page No.
1.
Verification of Boolean Theorems using Digital Logic Gates
--- Content provided by FirstRanker.com ---
2.Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
3.
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Implementation of half adder and full adder4.
Implementation of half subtractor and full subtractor
5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
--- Content provided by FirstRanker.com ---
MSI Devices6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
--- Content provided by FirstRanker.com ---
7.
Design and Implementation of Magnitude Comparator.
8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
--- Content provided by FirstRanker.com ---
9.Design and Implementation of Shift Registers.
10.
Design and Implementation of Synchronous and Asynchronous Counters.
11.
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Simulation of Combinational Circuits using Hardware Description Language (VHDL / VerilogHDL Software Required).
12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.1: STUDY OF BASIC GATES
Aim:
--- Content provided by FirstRanker.com ---
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gatesApparatus required:
Sl.No Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
--- Content provided by FirstRanker.com ---
6. NOR gate IC 7402 17. EX-OR gate IC 7486 1
8. Connecting wires As required
Theory:
--- Content provided by FirstRanker.com ---
Circuit that takes the logical decision and the process are called logic gates. Each gate has one ormore input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
--- Content provided by FirstRanker.com ---
output is high when both the inputs are high. The output is low level when any one of the inputs islow.
OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
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NOT gateA NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
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and any one of the input is low .The output is low level when both inputs are high.NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
EX-OR gate
--- Content provided by FirstRanker.com ---
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It issimilar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
--- Content provided by FirstRanker.com ---
8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
AND Gate Symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
OR Gate:
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OR GATE:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
NOT Gate symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
NAND Gate symbol: PIN Diagram:
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NOR Gate:
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--- Content provided by FirstRanker.com ---
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
--- Content provided by FirstRanker.com ---
1. Connections are given as per the circuit diagram.2. For all the IC?s 7
th
pin is grounded and 14
th
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pin is given +5 supply.3. Apply the inputs and verify the truth table for all gates.
Result:
--- Content provided by FirstRanker.com ---
The truth tables of all the basic logic gates were verified.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to verify the truthtable of all basic gates
--- Content provided by FirstRanker.com ---
1. List out the basic gate.
2. Mention the universal gate.
3. How many gates presented in IC 7408?
4. What is IC?
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5. What are the applications of gates?6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
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10. Write the truth table of NOR gate.11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
13. What are types of linear integrated circuit?
14. What is meant by etching?
--- Content provided by FirstRanker.com ---
15. What are the advantages of IC?16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.2:
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VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
--- Content provided by FirstRanker.com ---
Aim: To verification of Boolean theorems using logic gatesApparatus required:
Sl.No Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
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6. NOR gate IC 7402 37. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:BASIC Boolean Laws
1. Commutative Law
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The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A
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2. Associative LawThe binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
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3. Distributive Law
The binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
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2. A.(B+C) = (A.B)+(A.C)4. Absorption Law
1. A+AB = A
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2. A+AB =A+B--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
13 Format No.FirstRanker/stud/LM/34/issue:00/revision:005. Idempotent Law
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1. A+A = A
2. A.A = A
6. Complementary Law
--- Content provided by FirstRanker.com ---
1. A+A' = 1
2. A.A' = 0
7. De Morgan ?s Theorem
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1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
--- Content provided by FirstRanker.com ---
A.B = A+BDesign
1. Absorption Law
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A+AB = A
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2. Involution (or) Double complement Law
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A = A
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3. Idempotent Law1. A+A = A
2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
4. Demorgan ?s Law
A+B = A.B
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5. Distributive Law
A+(B.C) = (A+B).(A+C)
--- Content provided by FirstRanker.com ---
Procedure:1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
cc
.
--- Content provided by FirstRanker.com ---
3. Apply the inputs to the respective input pins.4. Verify the output with the truth table.
Result:
--- Content provided by FirstRanker.com ---
Thus the above stated Boolean laws are verified.
Outcome:
At the completion of an experiment student will able to know the basic laws with their truth table.
--- Content provided by FirstRanker.com ---
1. What is Demorgan?s law?
2. What is associative law?
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3. What is mean by compliment gate?4. Explain the basic laws in digital electronics
5. What is double complement?
Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
To design and verify the truth table of the Half Adder & Full Adder circuits
--- Content provided by FirstRanker.com ---
Apparatus required:S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:
The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
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0 + 0 = 00 + 1 = 1
1 + 0 = 1
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1 + 1 = 0 (with 1 as carry)
The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
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significant bit is called the sum.Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
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Full adder:A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
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From the truth table, the expression for sum and carry bits of the output can be obtained as,SUM = A?B?C + A?BC? + AB?C? + ABC
CARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half AdderTruth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,S = A B
Carry, C = A . B
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Circuit diagram:
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Full adderTruth table:
Sl.No. Input Output
A B C S C
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1. 0 0 0 0 02. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
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6. 1 0 1 0 17. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input OutputA B S C
1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
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4. 1 1 1 117 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:
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CARRY = AB + AC + BCLogic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
th
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pin is grounded and 14th
pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
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Result:The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
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At the completion of an experiment student will able to design the half adder circuit and thefull adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
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Aim:To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
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6. Connecting wires As requiredTheory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
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subtrahend bit, hence 1 is borrowed.Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
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difference and borrow bits.Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
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From the truth table the expression for difference and borrow bits of the output can be obtained
as,
Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
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Borrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Half subtractor
Truth table:
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Sl.No. Input Output
A B Difference Borrow
1. 0 0 0 0
2. 0 1 1 1
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3. 1 0 1 04. 1 1 0 0
From the truth table the expression for difference and borrow bits of the output can be obtained as,
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Difference, DIFF = A BBorrow, BORR = A?. B
Logic diagram:
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2. Full subtractor
Truth table:
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Sl.No.Input Output
A B C Difference Borrow
1. 0 0 0 0 0
2. 0 0 1 1 1
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3. 0 1 0 1 14. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
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8. 1 1 1 1 1--- Content provided by FirstRanker.com ---
21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Difference--- Content provided by FirstRanker.com ---
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Difference = A?B?C + A?BC? + AB?C? + ABCBorrow
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Borrow = A?B + A?C + BC
Circuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.5: 4-BIT ADDER AND SUBTRACTORAim:
To design and implement 4-bit adder and subtractor using IC 7483
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. IC IC 7483 13. NOT gate IC 7404 1
4. EX-OR gate IC 7486 1
5. Connecting wires As required
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Theory:4 BIT Binary adder:
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
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constructed with full adders connected in cascade, with the output carry from each full adder connected tothe input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
0
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and it ripples throughthe full adder to the output carry C
4
.
4 BIT Binary subtractor:
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The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
?B? and the corresponding input of full adder. The input carry C
0
must be equal to 1 when performing
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subtraction.4 BIT Binary adder / subtractor:
The addition and subtraction operation can be combined into one circuit with one common binary
adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
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becomes subtractor.23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PIN Diagram for IC 7483:
Logic Diagram: 4-Bit Binary Diagram:
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Logic diagram: 4-Bit Binary Subtractor:4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:--- Content provided by FirstRanker.com ---
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Procedure:1. Connections are given as per the circuit diagrams.
2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
.
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Result:The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
verified.
Outcome:
At the completion of an experiment student will able to design 4-bit binary adder and subtractor
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Input Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
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0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 00 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?2. Write the truth table for half adder.
3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
5. Write the truth table for full subtrator.
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6. Draw the logic diagram of full subtrator.7. What is adder?
8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
10. What is combinational circuit?
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11. What is different between combinational and sequential circuit?12. What are the gates involved for binary adder?
13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.6: MAGNITUDE COMPARATOR
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Aim:To design, construct and study the performance of 2 bit magnitude comparator
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
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7. Connecting wires As requiredTheory:
The comparison of two numbers is an operator that determines one number is greater than, less
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than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares twonumbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
three binary variables that indicate whether A>B, A=B (or) A
Truth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Logic Diagram:
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Pin Diagram for IC 7485:
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:
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Truth table:
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Procedure:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
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Result:
Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
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Outcome:At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
comparator using logic gates.
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A B A>B A=B A0 0 0 0
0 0 0 0
0 0 0 0
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0 0 0 00 1 0
0 0 0 1
0 0 0 1
0 0 0 0
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0 0 0 01 0 0
0 0 0 0
0 0 0 0
0 0 0 1
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0 0 0 10 0 1
Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is magnitude comparator?
2. What is most significant bit?
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3. Explain operation of AND gate.4. Explain truth table of a comparator.
5. Explain magnitude comparator7485 IC.
6. What is 8-bit input Magnitude Comparator?
7. What is IC?
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8. Explain the k-map simplification of A>B.9. Explain the k-map simplification of A=B.
10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
12. What is the truth table of 1-bit magnitude comparator?
13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION
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31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Aim:
To design, construct and study the performance of 4-bit different code converters
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(i) Binary to gray code converter(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:
The availability of large variety of codes for the same discrete elements of information results in
the use of different codes by different systems. A conversion circuit must be inserted between the two
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systems if each uses different codes for same information. Thus, code converter is a circuit that makes thetwo systems compatible even though each uses different binary code. The bit combination assigned to
binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
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designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is acircuit that makes the two systems compatible even though each uses a different binary code. To convert
from binary code to Excess-3 code, the input lines must supply the bit combination of elements as
specified by code and the output lines generate the corresponding bit combination of code. Each one of the
four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
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level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These arevarious other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is
C+D has been used to implement partially each of three outputs.
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Logic diagram:
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32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00(i) Binary to gray code converter
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Logic Diagram:K map for G3:
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G3 = B3
K map for G2:
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K map for G1:
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33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
K map for G0:
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Truth table:0
0
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00
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
0
0
0
0
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00
0
0
1
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11
1
1
1
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11
0
0
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00
1
1
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
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11
1
1
0
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
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01
1
0
0
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11
0
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(ii) Gray to binary code converter
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34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:
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K map for B3:B3=G3
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K map for B2:--- Content provided by FirstRanker.com ---
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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G3 G2 G1 G0 B3 B2 B1 B00
0
0
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00
0
0
0
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11
1
1
1
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11
1
0
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00
0
1
1
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11
1
1
1
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10
0
0
0
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0
0
1
1
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11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
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00
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
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01
1
0
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00
0
0
0
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00
0
1
1
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11
1
1
1
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10
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0
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01
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1
1
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00
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0
1
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11
1
0
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01
1
0
0
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11
0
0
1
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10
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1
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0
1
0
1
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01
0
1
0
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10
1
0
1
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01
K map for B1:
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K map for B0:
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Truth table:--- Content provided by FirstRanker.com ---
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(iii) BCD to excess-3 code converter
Logic Diagram:
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K map for E3:
E3 = B3 + B2 (B0 + B1)
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K map for E2:
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for E1:
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K map for E0:
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Truth table:
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(iv) Excess-3 to
B3 B2 B1 B0 G3 G2 G1 G0
0
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00
0
0
0
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00
1
1
1
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11
1
1
1
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0
0
0
0
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11
1
1
0
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00
0
1
1
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11
0
0
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11
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1
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10
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1
1
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00
1
1
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01
0
1
0
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10
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1
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01
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10
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00
1
1
1
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11
x
x
x
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xx
x
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x
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xx
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x
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1
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0x
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01
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x
x
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xx
x
x
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38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
BCD code converter
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Logic Diagram:
K map for A:
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A = X1 X2 + X3 X4 X1
K map for B:
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FirstRanker.com - FirstRanker's Choice1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
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III SEMESTER - R 2017
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
Section : _______________________________________
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LABORATORY MANUAL
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2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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is committed to provide highly disciplined, conscientious and
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enterprising professionals conforming to global standards through value based quality education andtraining.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
--- Content provided by FirstRanker.com ---
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
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DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
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? To provide the students rigorous learning experience to produce creative solutions to society?s
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needs.? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
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industry by continuous assessment and training.VISION
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MISSIONVISION
MISSION
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3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
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1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
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2. Core CompetenceTo train the students to meet the needs of core industry with an attitude of learning new
technologies.
3. Breadth
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To provide relevant training and experience to bridge the gap between theory and practice whichenable them to find solutions to problems in industry and research that contributes to the overall
development of society.
4. Professionalism
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To inculcate professional and effective communication skills to the students to make them lead ateam and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
5. Lifelong Learning/Ethics
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To practice ethical and professional responsibilities in the organization and society withcommitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
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f. Graduates will demonstrate skills to use modern engineering tools, software and equipment toanalyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
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will be aware of contemporary issues.j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
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CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
SYLLABUS
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Objectives:
The student should be made to:
? Understand the various logic gates.
? Be familiar with various combinational circuits.
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? Understand the various components used in the design of digital computers.? Be exposed to sequential circuits
? Learn to use HDL
List of experiments:
1. Verification of Boolean Theorems using basic gates.
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2. Design and implementation of combinational circuits using basic gates for arbitraryfunctions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
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c. Magnitude Comparatord. Application using multiplexers
4. Design and implementation of sequential circuits:
a. Shift ?registers
b. Synchronous and asynchronous counters
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5. Coding combinational / sequential circuits using HDL.6. Design and implementation of a simple digital system (Mini Project).
Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
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? Design and Implement combinational and sequential circuits.? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Content
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Sl.No. Name of the Experiment Page No.
1.
Verification of Boolean Theorems using Digital Logic Gates
2.
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Design and Implementation of Combinational Circuits using Basic Gates for ArbitraryFunctions, Code Converters
3.
Implementation of half adder and full adder
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4.Implementation of half subtractor and full subtractor
5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
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6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
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7.Design and Implementation of Magnitude Comparator.
8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
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Design and Implementation of Shift Registers.10.
Design and Implementation of Synchronous and Asynchronous Counters.
11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
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HDL Software Required).12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.1: STUDY OF BASIC GATES
Aim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
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7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
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more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known asuniversal gates. Basic gates form these gates.
AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
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low.OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
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A NOT gate is the physical realization of the complementation operation. The NOT gate iscalled an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
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NOR gateThe NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
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similar to OR gate but excludes the combination of both A and B being equal to one. The exclusiveOR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Procedure:
1. Connections are given as per the circuit diagram.
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2. For all the IC?s 7th
pin is grounded and 14
th
pin is given +5 supply.
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3. Apply the inputs and verify the truth table for all gates.Result:
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The truth tables of all the basic logic gates were verified.Outcome:
At the completion of an experiment student will able to verify the truth
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table of all basic gates--- Content provided by FirstRanker.com ---
1. List out the basic gate.2. Mention the universal gate.
3. How many gates presented in IC 7408?
4. What is IC?
5. What are the applications of gates?
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6. Write the truth table of AND gate.7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
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11. Write the truth table of EX- OR gate.12. What are the classifications of IC?
13. What are types of linear integrated circuit?
14. What is meant by etching?
15. What are the advantages of IC?
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16. Write the truth table of EX- NOR gate.Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.2:
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VERIFICATION OF BOOLEAN THEOREMS USING LOGICGATES
Aim: To verification of Boolean theorems using logic gates
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 3
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7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
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BASIC Boolean Laws
1. Commutative Law
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The binary operator OR, AND is said to be commutative if,1. A+B = B+A
2. A.B=B.A
2. Associative Law
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The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
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3. Distributive LawThe binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
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4. Absorption Law
1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
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1. A+A = A2. A.A = A
6. Complementary Law
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1. A+A' = 12. A.A' = 0
7. De Morgan ?s Theorem
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1. The complement of the sum is equal to the sum of the product of the individualcomplements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design
1. Absorption Law
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A+AB = A--- Content provided by FirstRanker.com ---
2. Involution (or) Double complement Law
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A = A--- Content provided by FirstRanker.com ---
3. Idempotent Law
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1. A+A = A
2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
A+B = A.B
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5. Distributive Law
A+(B.C) = (A+B).(A+C)
Procedure:
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1. Obtain the required IC along with the Digital trainer kit.2. Connect zero volts to GND pin and +5 volts to V
cc
.
3. Apply the inputs to the respective input pins.
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4. Verify the output with the truth table.Result:
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Thus the above stated Boolean laws are verified.Outcome:
At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?
2. What is associative law?
3. What is mean by compliment gate?
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4. Explain the basic laws in digital electronics5. What is double complement?
Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.3: HALF ADDER AND FULL ADDERAim:
To design and verify the truth table of the Half Adder & Full Adder circuits
Apparatus required:
--- Content provided by FirstRanker.com ---
S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
0 + 0 = 0
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0 + 1 = 1
1 + 0 = 1
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1 + 1 = 0 (with 1 as carry)The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
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Half adder:A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
Full adder:
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A combinational circuit which performs the arithmetic sum of three input bits is called full adder. Thethree input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
From the truth table, the expression for sum and carry bits of the output can be obtained as,
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SUM = A?B?C + A?BC? + AB?C? + ABCCARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half Adder
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Truth table:--- Content provided by FirstRanker.com ---
From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
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S = A BCarry, C = A . B
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Circuit diagram:--- Content provided by FirstRanker.com ---
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Full adder
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Truth table:Sl.No. Input Output
A B C S C
1. 0 0 0 0 0
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2. 0 0 1 1 03. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
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7. 1 1 0 0 18. 1 1 1 1 1
Sl.No. Input Output
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A B S C1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:--- Content provided by FirstRanker.com ---
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CARRY = AB + AC + BC
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Logic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
--- Content provided by FirstRanker.com ---
1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
th
pin is grounded and 14
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thpin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
Result:
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The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
At the completion of an experiment student will able to design the half adder circuit and the
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full adder circuit.--- Content provided by FirstRanker.com ---
19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
Aim:
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To design and verify the truth table of the half subtractor & full subtractor circuitsApparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
--- Content provided by FirstRanker.com ---
2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
subtrahend bit, hence 1 is borrowed.
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Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
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Full subtractor:A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
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From the truth table the expression for difference and borrow bits of the output can be obtainedas,
Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
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Borrow, BORR = A?BC + AB?C + ABC? +ABC--- Content provided by FirstRanker.com ---
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half subtractor
Truth table:
--- Content provided by FirstRanker.com ---
Sl.No. Input OutputA B Difference Borrow
1. 0 0 0 0
2. 0 1 1 1
3. 1 0 1 0
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4. 1 1 0 0From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A B
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Borrow, BORR = A?. B
Logic diagram:
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2. Full subtractorTruth table:
Sl.No.
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Input OutputA B C Difference Borrow
1. 0 0 0 0 0
2. 0 0 1 1 1
3. 0 1 0 1 1
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4. 0 1 1 0 15. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
8. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
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Borrow
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Borrow = A?B + A?C + BCCircuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
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Aim:
To design and implement 4-bit adder and subtractor using IC 7483
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. IC IC 7483 1
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3. NOT gate IC 7404 14. EX-OR gate IC 7486 1
5. Connecting wires As required
Theory:
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4 BIT Binary adder:
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected to
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the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? aredesignated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
0
and it ripples through
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the full adder to the output carry C4
.
4 BIT Binary subtractor:
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The circuit for subtracting A-B consists of an adder with inverters, placed between each data input?B? and the corresponding input of full adder. The input carry C
0
must be equal to 1 when performing
subtraction.
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4 BIT Binary adder / subtractor:The addition and subtraction operation can be combined into one circuit with one common binary
adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
becomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PIN Diagram for IC 7483:Logic Diagram: 4-Bit Binary Diagram:
Logic diagram: 4-Bit Binary Subtractor:
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4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Truth table:
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Procedure:
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1. Connections are given as per the circuit diagrams.2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
.
Result:
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The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table wasverified.
Outcome:
At the completion of an experiment student will able to design 4-bit binary adder and subtractor
--- Content provided by FirstRanker.com ---
Input Data A Input Data B Addition SubtractionA4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
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0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 01 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?
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2. Write the truth table for half adder.3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
5. Write the truth table for full subtrator.
6. Draw the logic diagram of full subtrator.
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7. What is adder?8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
10. What is combinational circuit?
11. What is different between combinational and sequential circuit?
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12. What are the gates involved for binary adder?13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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Viva ? Voce--- Content provided by FirstRanker.com ---
26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.6: MAGNITUDE COMPARATOR
Aim:
--- Content provided by FirstRanker.com ---
To design, construct and study the performance of 2 bit magnitude comparatorApparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
--- Content provided by FirstRanker.com ---
3. OR gate IC 7432 14. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:
The comparison of two numbers is an operator that determines one number is greater than, less
than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
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numbers A and B and determines their relative magnitude. The outcome of the comparator is specified bythree binary variables that indicate whether A>B, A=B (or) A
Truth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:
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Pin Diagram for IC 7485:--- Content provided by FirstRanker.com ---
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:
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Truth table:
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Procedure:1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
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Result:Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
comparator using logic gates.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
A B A>B A=B A0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
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0 1 00 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
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1 0 00 0 0 0
0 0 0 0
0 0 0 1
0 0 0 1
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0 0 1Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
1. What is magnitude comparator?
2. What is most significant bit?
3. Explain operation of AND gate.
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4. Explain truth table of a comparator.5. Explain magnitude comparator7485 IC.
6. What is 8-bit input Magnitude Comparator?
7. What is IC?
8. Explain the k-map simplification of A>B.
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9. Explain the k-map simplification of A=B.10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
12. What is the truth table of 1-bit magnitude comparator?
13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Aim:
To design, construct and study the performance of 4-bit different code converters
(i) Binary to gray code converter
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(ii) Gray to binary code converter(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:The availability of large variety of codes for the same discrete elements of information results in
the use of different codes by different systems. A conversion circuit must be inserted between the two
systems if each uses different codes for same information. Thus, code converter is a circuit that makes the
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two systems compatible even though each uses different binary code. The bit combination assigned tobinary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a
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circuit that makes the two systems compatible even though each uses a different binary code. To convertfrom binary code to Excess-3 code, the input lines must supply the bit combination of elements as
specified by code and the output lines generate the corresponding bit combination of code. Each one of the
four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are
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various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output isC+D has been used to implement partially each of three outputs.
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Logic diagram:32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(i) Binary to gray code converter
Logic Diagram:
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K map for G3:
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G3 = B3K map for G2:
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K map for G1:33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for G0:Truth table:
--- Content provided by FirstRanker.com ---
0
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
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11
1
1
1
--- Content provided by FirstRanker.com ---
11
1
0
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00
0
1
1
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11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
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0
0
1
1
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00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
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11
0
1
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01
0
1
0
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10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
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00
0
0
0
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00
0
1
1
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11
1
1
1
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10
0
0
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01
1
1
1
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11
1
1
0
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00
0
0
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01
1
1
1
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00
0
0
1
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11
1
0
0
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0
1
1
0
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01
1
0
0
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11
0
0
1
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10
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(ii) Gray to binary code converter
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34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:K map for B3:
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B3=G3
K map for B2:
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
G3 G2 G1 G0 B3 B2 B1 B0
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0
0
0
0
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00
0
0
1
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11
1
1
1
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11
0
0
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00
1
1
1
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11
1
1
1
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00
0
0
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00
1
1
1
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10
0
0
0
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11
1
1
0
--- Content provided by FirstRanker.com ---
00
1
1
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00
1
1
0
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01
1
0
0
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11
0
0
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00
0
0
0
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00
1
1
1
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11
1
1
1
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0
0
0
0
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11
1
1
0
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00
0
1
1
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11
0
0
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11
0
0
1
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10
0
1
1
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00
1
1
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01
0
1
0
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10
1
0
1
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01
0
1
0
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1K map for B1:
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K map for B0:
Truth table:
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(iii) BCD to excess-3 code converterLogic Diagram:
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K map for E3:E3 = B3 + B2 (B0 + B1)
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K map for E2:--- Content provided by FirstRanker.com ---
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
K map for E1:--- Content provided by FirstRanker.com ---
K map for E0:--- Content provided by FirstRanker.com ---
Truth table:
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(iv) Excess-3 toB3 B2 B1 B0 G3 G2 G1 G0
0
0
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00
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
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11
1
1
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00
0
0
1
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11
1
0
0
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00
1
1
1
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10
0
1
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10
0
1
1
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00
1
1
0
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01
1
0
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10
1
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1
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01
0
1
0
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10
1
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1
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0
0
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01
1
1
1
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1x
x
x
x
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xx
0
1
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11
1
0
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00
1
x
x
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xx
x
x
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10
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00
1
1
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xx
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x
x
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x1
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01
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10
x
x
x
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xx
x
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38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
BCD code converter
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Logic Diagram:K map for A:
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A = X1 X2 + X3 X4 X1
K map for B:
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39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for C:--- Content provided by FirstRanker.com ---
K map for D:--- Content provided by FirstRanker.com ---
Truth table:--- Content provided by FirstRanker.com ---
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--- Content provided by FirstRanker.com ---
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B3 B2 B1 B0 G3 G2 G1 G0
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00
0
0
0
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11
1
1
1
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0
1
1
1
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10
0
0
0
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11
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11
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1
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10
1
0
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10
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0
1
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01
0
0
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00
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0
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00
1
1
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00
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11
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0
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00
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10
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01
FirstRanker.com - FirstRanker's Choice
--- Content provided by FirstRanker.com ---
1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
?
--- Content provided by FirstRanker.com ---
DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
III SEMESTER - R 2017CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________Register No : _______________________________________
Section : _______________________________________
--- Content provided by FirstRanker.com ---
LABORATORY MANUAL
--- Content provided by FirstRanker.com ---
2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
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training.--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
--- Content provided by FirstRanker.com ---
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag onheart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
--- Content provided by FirstRanker.com ---
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering toprofessional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
--- Content provided by FirstRanker.com ---
VISION
MISSION
--- Content provided by FirstRanker.com ---
VISION
MISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
--- Content provided by FirstRanker.com ---
1. FundamentalsTo provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
2. Core Competence
--- Content provided by FirstRanker.com ---
To train the students to meet the needs of core industry with an attitude of learning newtechnologies.
3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
--- Content provided by FirstRanker.com ---
enable them to find solutions to problems in industry and research that contributes to the overalldevelopment of society.
4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
--- Content provided by FirstRanker.com ---
team and stand as a good decision maker to manage any constraint environment with goodprofessional ethics at all strategies.
5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
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commitment and lifelong learning needed for successful professional career.--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM OUTCOMES (POs)
a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
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b. Graduates will be able to identify, formulate and solve electrical engineering problems.c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
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analyze problems.g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
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j. Graduates will develop confidence for self-education and ability for lifelong learning.k. Graduate who can participate and succeed in competitive examinations.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00SYLLABUS
--- Content provided by FirstRanker.com ---
Objectives:The student should be made to:
? Understand the various logic gates.
? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
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? Be exposed to sequential circuits? Learn to use HDL
List of experiments:
1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
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functions, code converters.3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
c. Magnitude Comparator
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d. Application using multiplexers4. Design and implementation of sequential circuits:
a. Shift ?registers
b. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
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6. Design and implementation of a simple digital system (Mini Project).Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
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? Analyze a given digital circuit ? combinational and sequential.? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
--- Content provided by FirstRanker.com ---
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--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Content
--- Content provided by FirstRanker.com ---
Sl.No. Name of the Experiment Page No.1.
Verification of Boolean Theorems using Digital Logic Gates
2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
--- Content provided by FirstRanker.com ---
Functions, Code Converters3.
Implementation of half adder and full adder
4.
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Implementation of half subtractor and full subtractor5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
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6.Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
7.
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Design and Implementation of Magnitude Comparator.8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
Design and Implementation of Shift Registers.
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10.Design and Implementation of Synchronous and Asynchronous Counters.
11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
--- Content provided by FirstRanker.com ---
12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
--- Content provided by FirstRanker.com ---
7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Expt.No.1: STUDY OF BASIC GATESAim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
--- Content provided by FirstRanker.com ---
Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
--- Content provided by FirstRanker.com ---
3. OR gate IC 7432 14. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
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8. Connecting wires As requiredTheory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
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universal gates. Basic gates form these gates.AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
low.
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OR gateThe OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
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called an inverter. The output is high when the input is low. The output is low when the input is high.NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
NOR gate
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The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. Theoutput is low when one or both inputs are high.
EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
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OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NAND Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
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thpin is grounded and 14
th
pin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
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Result:
The truth tables of all the basic logic gates were verified.
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Outcome:
At the completion of an experiment student will able to verify the truth
table of all basic gates
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1. List out the basic gate.
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2. Mention the universal gate.3. How many gates presented in IC 7408?
4. What is IC?
5. What are the applications of gates?
6. Write the truth table of AND gate.
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7. Write the truth table of OR gate.8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
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12. What are the classifications of IC?13. What are types of linear integrated circuit?
14. What is meant by etching?
15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
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Viva ? Voce--- Content provided by FirstRanker.com ---
12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.2:
VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
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GATESAim: To verification of Boolean theorems using logic gates
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
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8. Connecting wires As requiredTheory:
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BASIC Boolean Laws1. Commutative Law
The binary operator OR, AND is said to be commutative if,
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1. A+B = B+A2. A.B=B.A
2. Associative Law
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The binary operator OR, AND is said to be associative if,1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
3. Distributive Law
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The binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
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4. Absorption Law1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
1. A+A = A
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2. A.A = A6. Complementary Law
1. A+A' = 1
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2. A.A' = 07. De Morgan ?s Theorem
1. The complement of the sum is equal to the sum of the product of the individual
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complements.A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design
1. Absorption Law
A+AB = A
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2. Involution (or) Double complement Law
A = A
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3. Idempotent Law
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1. A+A = A2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s LawA+B = A.B
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5. Distributive LawA+(B.C) = (A+B).(A+C)
Procedure:
1. Obtain the required IC along with the Digital trainer kit.
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2. Connect zero volts to GND pin and +5 volts to Vcc
.
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
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Result:
Thus the above stated Boolean laws are verified.
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Outcome:At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?
2. What is associative law?
3. What is mean by compliment gate?
4. Explain the basic laws in digital electronics
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5. What is double complement?Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.3: HALF ADDER AND FULL ADDER
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Aim:To design and verify the truth table of the Half Adder & Full Adder circuits
Apparatus required:
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S. No. Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. EX-OR gate IC 7486 16. Connecting wires As required
Theory:
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The most basic arithmetic operation is the addition of two binary digits. There are fourpossible elementary operations, namely,
0 + 0 = 0
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0 + 1 = 11 + 0 = 1
1 + 1 = 0 (with 1 as carry)
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The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
Half adder:
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A combinational circuit which performs the addition of two bits is called half adder. The input variablesdesignate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
Full adder:
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
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three input bits include two significant bits and a previous carry bit. A full adder circuit can be implementedwith two half adders and one OR gate.
From the truth table, the expression for sum and carry bits of the output can be obtained as,
SUM = A?B?C + A?BC? + AB?C? + ABC
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CARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Half Adder
Truth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
S = A B
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Carry, C = A . B
Circuit diagram:
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Full adder
Truth table:
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Sl.No. Input Output
A B C S C
1. 0 0 0 0 0
2. 0 0 1 1 0
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3. 0 1 0 1 04. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
7. 1 1 0 0 1
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8. 1 1 1 1 1Sl.No. Input Output
A B S C
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1. 0 0 0 02. 0 1 1 0
3. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
Carry:
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CARRY = AB + AC + BC
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Logic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Procedure:
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1. Connections are given as per the circuit diagrams.2. For all the IC?s 7
th
pin is grounded and 14
th
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pin is given +5 V supply.3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
Result:
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The design of the half adder and full adder circuits was done and their truth tables were verified.Outcome:
At the completion of an experiment student will able to design the half adder circuit and the
full adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
Aim:
To design and verify the truth table of the half subtractor & full subtractor circuits
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
subtrahend bit, hence 1 is borrowed.
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Half subtractor:A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
Full subtractor:
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A combinational circuit which performs the subtraction of three input bits is called full subtractor. Thethree input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
From the truth table the expression for difference and borrow bits of the output can be obtained
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as,Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
Borrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half subtractorTruth table:
Sl.No. Input Output
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A B Difference Borrow1. 0 0 0 0
2. 0 1 1 1
3. 1 0 1 0
4. 1 1 0 0
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From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A B
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Borrow, BORR = A?. BLogic diagram:
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2. Full subtractor
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Truth table:Sl.No.
Input Output
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A B C Difference Borrow1. 0 0 0 0 0
2. 0 0 1 1 1
3. 0 1 0 1 1
4. 0 1 1 0 1
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5. 1 0 0 1 06. 1 0 1 0 0
7. 1 1 0 0 0
8. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
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Borrow
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Borrow = A?B + A?C + BC
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Circuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
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Aim:
To design and implement 4-bit adder and subtractor using IC 7483
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. IC IC 7483 1
3. NOT gate IC 7404 1
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4. EX-OR gate IC 7486 15. Connecting wires As required
Theory:
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4 BIT Binary adder:A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected to
the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
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designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. Thecarries are connected in chain through full adder. The input carry to the adder is C
0
and it ripples through
the full adder to the output carry C
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4.
4 BIT Binary subtractor:
The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
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?B? and the corresponding input of full adder. The input carry C0
must be equal to 1 when performing
subtraction.
4 BIT Binary adder / subtractor:
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The addition and subtraction operation can be combined into one circuit with one common binary
adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
becomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PIN Diagram for IC 7483:
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Logic Diagram: 4-Bit Binary Diagram:
Logic diagram: 4-Bit Binary Subtractor:
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4-Bit Binary Adder /Subtractor:24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:
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Procedure:
1. Connections are given as per the circuit diagrams.
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2. Logical inputs were given as per circuit diagram.3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
.
Result:
The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
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verified.Outcome:
At the completion of an experiment student will able to design 4-bit binary adder and subtractor
Input Data A Input Data B Addition Subtraction
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A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D11 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
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1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 11 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?
2. Write the truth table for half adder.
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3. Write the truth table for full adder.4. Write the truth table for half subtrator.
5. Write the truth table for full subtrator.
6. Draw the logic diagram of full subtrator.
7. What is adder?
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8. List out the application of adders.9. Draw the full adder using two half adder circuits.
10. What is combinational circuit?
11. What is different between combinational and sequential circuit?
12. What are the gates involved for binary adder?
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13. List the properties of Ex-Nor gate?14. What is expression for sum and carry?
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.6: MAGNITUDE COMPARATOR
Aim:
To design, construct and study the performance of 2 bit magnitude comparator
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:The comparison of two numbers is an operator that determines one number is greater than, less
than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
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three binary variables that indicate whether A>B, A=B (or) ATruth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:Pin Diagram for IC 7485:
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:
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Procedure:
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1. Connections are given as per circuit diagram.2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
Result:
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Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
Outcome:
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At the completion of an experiment student will able to design the 2-bit and 8-bit magnitudecomparator using logic gates.
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A B A>B A=B A0 0 0 00 0 0 0
0 0 0 0
0 0 0 0
0 1 0
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0 0 0 10 0 0 1
0 0 0 0
0 0 0 0
1 0 0
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0 0 0 00 0 0 0
0 0 0 1
0 0 0 1
0 0 1
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
1. What is magnitude comparator?
2. What is most significant bit?
3. Explain operation of AND gate.
4. Explain truth table of a comparator.
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5. Explain magnitude comparator7485 IC.6. What is 8-bit input Magnitude Comparator?
7. What is IC?
8. Explain the k-map simplification of A>B.
9. Explain the k-map simplification of A=B.
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10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.12. What is the truth table of 1-bit magnitude comparator?
13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION
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31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Aim:
To design, construct and study the performance of 4-bit different code converters
(i) Binary to gray code converter
(ii) Gray to binary code converter
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(iii) BCD to excess-3 code converter(iv) Excess-3 to BCD code converter
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. Magnitude comparator IC 7485 26. EX-OR gate IC 7486 1
7. Connecting wires As required
Theory:
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The availability of large variety of codes for the same discrete elements of information results in
the use of different codes by different systems. A conversion circuit must be inserted between the two
systems if each uses different codes for same information. Thus, code converter is a circuit that makes the
two systems compatible even though each uses different binary code. The bit combination assigned to
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binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputsand four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a
circuit that makes the two systems compatible even though each uses a different binary code. To convert
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from binary code to Excess-3 code, the input lines must supply the bit combination of elements asspecified by code and the output lines generate the corresponding bit combination of code. Each one of the
four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are
various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is
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C+D has been used to implement partially each of three outputs.Logic diagram:
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32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(i) Binary to gray code converter
Logic Diagram:
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K map for G3:
G3 = B3
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K map for G2:--- Content provided by FirstRanker.com ---
K map for G1:
--- Content provided by FirstRanker.com ---
33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
K map for G0:
--- Content provided by FirstRanker.com ---
Truth table:
--- Content provided by FirstRanker.com ---
0
0
0
0
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
0
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
0--- Content provided by FirstRanker.com ---
(ii) Gray to binary code converter
--- Content provided by FirstRanker.com ---
34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Logic Diagram:
--- Content provided by FirstRanker.com ---
K map for B3:
--- Content provided by FirstRanker.com ---
B3=G3
K map for B2:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
G3 G2 G1 G0 B3 B2 B1 B0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
0
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
K map for B1:
--- Content provided by FirstRanker.com ---
K map for B0:Truth table:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
(iii) BCD to excess-3 code converter
--- Content provided by FirstRanker.com ---
Logic Diagram:
K map for E3:
--- Content provided by FirstRanker.com ---
E3 = B3 + B2 (B0 + B1)
K map for E2:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
K map for E1:
--- Content provided by FirstRanker.com ---
K map for E0:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Truth table:--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
(iv) Excess-3 to
--- Content provided by FirstRanker.com ---
B3 B2 B1 B0 G3 G2 G1 G00
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
0
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
xx
x
x
x
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x0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
01
x
x
x
--- Content provided by FirstRanker.com ---
xx
x
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
x
--- Content provided by FirstRanker.com ---
xx
x
x
x
--- Content provided by FirstRanker.com ---
1
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
0x
x
x
x
--- Content provided by FirstRanker.com ---
xx
--- Content provided by FirstRanker.com ---
38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00BCD code converter
Logic Diagram:
--- Content provided by FirstRanker.com ---
K map for A:
--- Content provided by FirstRanker.com ---
A = X1 X2 + X3 X4 X1K map for B:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
K map for C:
--- Content provided by FirstRanker.com ---
K map for D:
--- Content provided by FirstRanker.com ---
Truth table:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
B3 B2 B1 B0 G3 G2 G1 G0
0
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
1
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
01
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
01
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
0
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
1--- Content provided by FirstRanker.com ---
40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Procedure:1. Connections were given as per circuit diagram.
2. Logical inputs were given as per truth table
3. Observe the logical output and verify with the truth tables.
--- Content provided by FirstRanker.com ---
Result:Thus the code converters were designed and verified using the corresponding truth table.
Outcome:
At the completion of an experiment student will able to design the binary to gray converter.
--- Content provided by FirstRanker.com ---
1. What is binary code?
2. What is gray code?
3. What are the advantages of gray code?
--- Content provided by FirstRanker.com ---
4. What is unit distance code?5. What is sequential code?
6. How to convert binary to gray code?
7. How to convert gray to binary code?
8. What is reflective code?
--- Content provided by FirstRanker.com ---
9. What are the advantages of EX ? 3 code?10. Which code is used to arithmetic operation in digital circuits?
11. Explain the operation of EX ? OR.
12. What is K ? Map?
13. Draw the truth table of EX- OR gate.
--- Content provided by FirstRanker.com ---
14. What is SOP?15. What is POS?
16. What is minterm?
--- Content provided by FirstRanker.com ---
Viva ? Voce
--- Content provided by FirstRanker.com ---
FirstRanker.com - FirstRanker's Choice
--- Content provided by FirstRanker.com ---
1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
?DEPARTMENT OF
--- Content provided by FirstRanker.com ---
COMPUTER SCIENCE ENGINEERINGIII SEMESTER - R 2017
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
Section : _______________________________________
--- Content provided by FirstRanker.com ---
LABORATORY MANUAL
--- Content provided by FirstRanker.com ---
2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious andenterprising professionals conforming to global standards through value based quality education and
training.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
--- Content provided by FirstRanker.com ---
levels? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
--- Content provided by FirstRanker.com ---
Electrical and Electronics Engineers.--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?sneeds.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
--- Content provided by FirstRanker.com ---
concepts with strongly supported laboratory and prepare them to meet the global needs of theindustry by continuous assessment and training.
VISION
--- Content provided by FirstRanker.com ---
MISSION
VISION
--- Content provided by FirstRanker.com ---
MISSION--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
--- Content provided by FirstRanker.com ---
1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
--- Content provided by FirstRanker.com ---
2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
technologies.
--- Content provided by FirstRanker.com ---
3. BreadthTo provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
development of society.
--- Content provided by FirstRanker.com ---
4. ProfessionalismTo inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
--- Content provided by FirstRanker.com ---
5. Lifelong Learning/EthicsTo practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PROGRAM OUTCOMES (POs)
--- Content provided by FirstRanker.com ---
a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
--- Content provided by FirstRanker.com ---
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
--- Content provided by FirstRanker.com ---
i. Graduates will show the understanding of impact of engineering solutions on the society and alsowill be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
SYLLABUSObjectives:
The student should be made to:
? Understand the various logic gates.
--- Content provided by FirstRanker.com ---
? Be familiar with various combinational circuits.? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
? Learn to use HDL
List of experiments:
--- Content provided by FirstRanker.com ---
1. Verification of Boolean Theorems using basic gates.2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
--- Content provided by FirstRanker.com ---
b. Parity generator / checkerc. Magnitude Comparator
d. Application using multiplexers
4. Design and implementation of sequential circuits:
a. Shift ?registers
--- Content provided by FirstRanker.com ---
b. Synchronous and asynchronous counters5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
Course Outcomes:
--- Content provided by FirstRanker.com ---
? Use Boolean simplification techniques to design a combinational hardware circuit.? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
ContentSl.No. Name of the Experiment Page No.
1.
Verification of Boolean Theorems using Digital Logic Gates
--- Content provided by FirstRanker.com ---
2.Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
3.
--- Content provided by FirstRanker.com ---
Implementation of half adder and full adder4.
Implementation of half subtractor and full subtractor
5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
--- Content provided by FirstRanker.com ---
MSI Devices6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
--- Content provided by FirstRanker.com ---
7.
Design and Implementation of Magnitude Comparator.
8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
--- Content provided by FirstRanker.com ---
9.Design and Implementation of Shift Registers.
10.
Design and Implementation of Synchronous and Asynchronous Counters.
11.
--- Content provided by FirstRanker.com ---
Simulation of Combinational Circuits using Hardware Description Language (VHDL / VerilogHDL Software Required).
12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.1: STUDY OF BASIC GATES
Aim:
--- Content provided by FirstRanker.com ---
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gatesApparatus required:
Sl.No Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
--- Content provided by FirstRanker.com ---
6. NOR gate IC 7402 17. EX-OR gate IC 7486 1
8. Connecting wires As required
Theory:
--- Content provided by FirstRanker.com ---
Circuit that takes the logical decision and the process are called logic gates. Each gate has one ormore input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
--- Content provided by FirstRanker.com ---
output is high when both the inputs are high. The output is low level when any one of the inputs islow.
OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
--- Content provided by FirstRanker.com ---
NOT gateA NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
--- Content provided by FirstRanker.com ---
and any one of the input is low .The output is low level when both inputs are high.NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
EX-OR gate
--- Content provided by FirstRanker.com ---
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It issimilar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
--- Content provided by FirstRanker.com ---
8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
AND Gate Symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
OR Gate:
--- Content provided by FirstRanker.com ---
OR GATE:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
NOT Gate symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
EXOR Gate symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
NAND Gate symbol: PIN Diagram:
--- Content provided by FirstRanker.com ---
NOR Gate:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
--- Content provided by FirstRanker.com ---
1. Connections are given as per the circuit diagram.2. For all the IC?s 7
th
pin is grounded and 14
th
--- Content provided by FirstRanker.com ---
pin is given +5 supply.3. Apply the inputs and verify the truth table for all gates.
Result:
--- Content provided by FirstRanker.com ---
The truth tables of all the basic logic gates were verified.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to verify the truthtable of all basic gates
--- Content provided by FirstRanker.com ---
1. List out the basic gate.
2. Mention the universal gate.
3. How many gates presented in IC 7408?
4. What is IC?
--- Content provided by FirstRanker.com ---
5. What are the applications of gates?6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
--- Content provided by FirstRanker.com ---
10. Write the truth table of NOR gate.11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
13. What are types of linear integrated circuit?
14. What is meant by etching?
--- Content provided by FirstRanker.com ---
15. What are the advantages of IC?16. Write the truth table of EX- NOR gate.
Viva ? Voce
--- Content provided by FirstRanker.com ---
12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.2:
--- Content provided by FirstRanker.com ---
VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
--- Content provided by FirstRanker.com ---
Aim: To verification of Boolean theorems using logic gatesApparatus required:
Sl.No Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
--- Content provided by FirstRanker.com ---
6. NOR gate IC 7402 37. EX-OR gate IC 7486 1
8. Connecting wires As required
--- Content provided by FirstRanker.com ---
Theory:BASIC Boolean Laws
1. Commutative Law
--- Content provided by FirstRanker.com ---
The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A
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2. Associative LawThe binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
--- Content provided by FirstRanker.com ---
3. Distributive Law
The binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
--- Content provided by FirstRanker.com ---
2. A.(B+C) = (A.B)+(A.C)4. Absorption Law
1. A+AB = A
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2. A+AB =A+B--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
13 Format No.FirstRanker/stud/LM/34/issue:00/revision:005. Idempotent Law
--- Content provided by FirstRanker.com ---
1. A+A = A
2. A.A = A
6. Complementary Law
--- Content provided by FirstRanker.com ---
1. A+A' = 1
2. A.A' = 0
7. De Morgan ?s Theorem
--- Content provided by FirstRanker.com ---
1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
--- Content provided by FirstRanker.com ---
A.B = A+BDesign
1. Absorption Law
--- Content provided by FirstRanker.com ---
A+AB = A
--- Content provided by FirstRanker.com ---
2. Involution (or) Double complement Law
--- Content provided by FirstRanker.com ---
A = A
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
3. Idempotent Law1. A+A = A
2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
A+B = A.B
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5. Distributive Law
A+(B.C) = (A+B).(A+C)
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Procedure:1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
cc
.
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3. Apply the inputs to the respective input pins.4. Verify the output with the truth table.
Result:
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Thus the above stated Boolean laws are verified.
Outcome:
At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?
2. What is associative law?
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3. What is mean by compliment gate?4. Explain the basic laws in digital electronics
5. What is double complement?
Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
To design and verify the truth table of the Half Adder & Full Adder circuits
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Apparatus required:S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:
The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
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0 + 0 = 00 + 1 = 1
1 + 0 = 1
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1 + 1 = 0 (with 1 as carry)
The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
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significant bit is called the sum.Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
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Full adder:A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
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From the truth table, the expression for sum and carry bits of the output can be obtained as,SUM = A?B?C + A?BC? + AB?C? + ABC
CARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half AdderTruth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,S = A B
Carry, C = A . B
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Circuit diagram:
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Full adderTruth table:
Sl.No. Input Output
A B C S C
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1. 0 0 0 0 02. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
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6. 1 0 1 0 17. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input OutputA B S C
1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
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4. 1 1 1 117 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:
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CARRY = AB + AC + BCLogic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
th
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pin is grounded and 14th
pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
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Result:The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
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At the completion of an experiment student will able to design the half adder circuit and thefull adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
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Aim:To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
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6. Connecting wires As requiredTheory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
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subtrahend bit, hence 1 is borrowed.Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
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difference and borrow bits.Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
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From the truth table the expression for difference and borrow bits of the output can be obtained
as,
Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
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Borrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Half subtractor
Truth table:
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Sl.No. Input Output
A B Difference Borrow
1. 0 0 0 0
2. 0 1 1 1
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3. 1 0 1 04. 1 1 0 0
From the truth table the expression for difference and borrow bits of the output can be obtained as,
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Difference, DIFF = A BBorrow, BORR = A?. B
Logic diagram:
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2. Full subtractor
Truth table:
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Sl.No.Input Output
A B C Difference Borrow
1. 0 0 0 0 0
2. 0 0 1 1 1
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3. 0 1 0 1 14. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
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8. 1 1 1 1 1--- Content provided by FirstRanker.com ---
21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Difference--- Content provided by FirstRanker.com ---
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Difference = A?B?C + A?BC? + AB?C? + ABCBorrow
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Borrow = A?B + A?C + BC
Circuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.5: 4-BIT ADDER AND SUBTRACTORAim:
To design and implement 4-bit adder and subtractor using IC 7483
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. IC IC 7483 13. NOT gate IC 7404 1
4. EX-OR gate IC 7486 1
5. Connecting wires As required
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Theory:4 BIT Binary adder:
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
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constructed with full adders connected in cascade, with the output carry from each full adder connected tothe input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
0
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and it ripples throughthe full adder to the output carry C
4
.
4 BIT Binary subtractor:
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The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
?B? and the corresponding input of full adder. The input carry C
0
must be equal to 1 when performing
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subtraction.4 BIT Binary adder / subtractor:
The addition and subtraction operation can be combined into one circuit with one common binary
adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
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becomes subtractor.23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PIN Diagram for IC 7483:
Logic Diagram: 4-Bit Binary Diagram:
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Logic diagram: 4-Bit Binary Subtractor:4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:--- Content provided by FirstRanker.com ---
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Procedure:1. Connections are given as per the circuit diagrams.
2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
.
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Result:The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
verified.
Outcome:
At the completion of an experiment student will able to design 4-bit binary adder and subtractor
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Input Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
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0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 00 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?2. Write the truth table for half adder.
3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
5. Write the truth table for full subtrator.
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6. Draw the logic diagram of full subtrator.7. What is adder?
8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
10. What is combinational circuit?
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11. What is different between combinational and sequential circuit?12. What are the gates involved for binary adder?
13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.6: MAGNITUDE COMPARATOR
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Aim:To design, construct and study the performance of 2 bit magnitude comparator
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
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7. Connecting wires As requiredTheory:
The comparison of two numbers is an operator that determines one number is greater than, less
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than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares twonumbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
three binary variables that indicate whether A>B, A=B (or) A
Truth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Logic Diagram:
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Pin Diagram for IC 7485:
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:
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Truth table:
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Procedure:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
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Result:
Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
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Outcome:At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
comparator using logic gates.
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A B A>B A=B A0 0 0 0
0 0 0 0
0 0 0 0
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0 0 0 00 1 0
0 0 0 1
0 0 0 1
0 0 0 0
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0 0 0 01 0 0
0 0 0 0
0 0 0 0
0 0 0 1
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0 0 0 10 0 1
Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is magnitude comparator?
2. What is most significant bit?
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3. Explain operation of AND gate.4. Explain truth table of a comparator.
5. Explain magnitude comparator7485 IC.
6. What is 8-bit input Magnitude Comparator?
7. What is IC?
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8. Explain the k-map simplification of A>B.9. Explain the k-map simplification of A=B.
10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
12. What is the truth table of 1-bit magnitude comparator?
13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION
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31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Aim:
To design, construct and study the performance of 4-bit different code converters
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(i) Binary to gray code converter(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:
The availability of large variety of codes for the same discrete elements of information results in
the use of different codes by different systems. A conversion circuit must be inserted between the two
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systems if each uses different codes for same information. Thus, code converter is a circuit that makes thetwo systems compatible even though each uses different binary code. The bit combination assigned to
binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
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designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is acircuit that makes the two systems compatible even though each uses a different binary code. To convert
from binary code to Excess-3 code, the input lines must supply the bit combination of elements as
specified by code and the output lines generate the corresponding bit combination of code. Each one of the
four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
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level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These arevarious other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is
C+D has been used to implement partially each of three outputs.
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Logic diagram:
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32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00(i) Binary to gray code converter
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Logic Diagram:K map for G3:
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G3 = B3
K map for G2:
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K map for G1:
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33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
K map for G0:
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Truth table:0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
0
0
0
0
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
1
1
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11
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
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11
0
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(ii) Gray to binary code converter
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34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:
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K map for B3:B3=G3
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K map for B2:--- Content provided by FirstRanker.com ---
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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G3 G2 G1 G0 B3 B2 B1 B00
0
0
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00
0
0
0
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11
1
1
1
--- Content provided by FirstRanker.com ---
11
1
0
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00
0
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
0
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
--- Content provided by FirstRanker.com ---
00
0
0
0
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00
0
1
1
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11
1
1
1
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10
0
0
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01
1
1
1
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00
0
0
1
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11
1
0
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01
1
0
0
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11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
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0
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
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10
1
0
1
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01
K map for B1:
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K map for B0:
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Truth table:--- Content provided by FirstRanker.com ---
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(iii) BCD to excess-3 code converter
Logic Diagram:
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K map for E3:
E3 = B3 + B2 (B0 + B1)
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K map for E2:
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for E1:
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K map for E0:
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Truth table:
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(iv) Excess-3 to
B3 B2 B1 B0 G3 G2 G1 G0
0
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00
0
0
0
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00
1
1
1
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11
1
1
1
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0
0
0
0
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11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
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11
0
0
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11
0
0
1
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10
0
1
1
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00
1
1
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01
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0
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10
1
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1
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01
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1
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00
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1
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11
x
x
x
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xx
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0
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11
1
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00
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x
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xx
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1
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10
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1
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0x
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x
x
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xx
1
0
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10
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1
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01
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x
x
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xx
x
x
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38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
BCD code converter
--- Content provided by FirstRanker.com ---
Logic Diagram:
K map for A:
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A = X1 X2 + X3 X4 X1
K map for B:
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--- Content provided by FirstRanker.com ---
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39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for C:
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K map for D:
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Truth table:
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B3 B2 B1 B0 G3 G2 G1 G0
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0
0
0
0
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01
1
1
1
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10
1
1
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11
0
0
0
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01
1
0
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01
1
0
0
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11
0
1
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01
0
1
0
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10
1
0
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00
0
0
0
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00
0
1
1
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0
0
0
0
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11
1
1
0
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00
0
1
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10
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1
1
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00
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
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40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Procedure:
1. Connections were given as per circuit diagram.
2. Logical inputs were given as per truth table
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3. Observe the logical output and verify with the truth tables.Result:
Thus the code converters were designed and verified using the corresponding truth table.
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Outcome:At the completion of an experiment student will able to design the binary to gray converter.
1. What is binary code?
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2. What is gray code?3. What are the advantages of gray code?
4. What is unit distance code?
5. What is sequential code?
6. How to convert binary to gray code?
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7. How to convert gray to binary code?8. What is reflective code?
9. What are the advantages of EX ? 3 code?
10. Which code is used to arithmetic operation in digital circuits?
11. Explain the operation of EX ? OR.
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12. What is K ? Map?13. Draw the truth table of EX- OR gate.
14. What is SOP?
15. What is POS?
16. What is minterm?
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Viva ? Voce
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41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.8: PARITY GENERATORS AND CHECKERS
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Aim:To implement the odd and even parity checkers using the logic gates and also to generate the odd parity
and even parity numbers using the generators
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl. No Component Type Quantity
1 Trainer Kit - 1
2 EX-OR IC7486 1
3 NOT gate IC 7404 1
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4 Connecting wires - RequiredTheory:
Parity checking is used for error detection in data transmission.
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Odd parity checkers:It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
odd.
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Even parity checker:It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
even.
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Odd parity generators:It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also
the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bits
which is an odd parity number.
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Even parity generator:It generates an even parity number. The even parity checker circuit is used with the inverted output and
also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5
bits which is an even parity number.
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FirstRanker.com - FirstRanker's Choice
--- Content provided by FirstRanker.com ---
1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
?
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DEPARTMENT OFCOMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
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CS8382 DIGITAL SYSTEMS LABORATORY--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
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Section : _______________________________________--- Content provided by FirstRanker.com ---
LABORATORY MANUAL2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
training.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
--- Content provided by FirstRanker.com ---
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at differentlevels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
--- Content provided by FirstRanker.com ---
Engineering and thereby produce extremely well trained employable, socially responsible and innovativeElectrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
--- Content provided by FirstRanker.com ---
? To provide highest quality learning environment for the students emphasizing fundamentalconcepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
--- Content provided by FirstRanker.com ---
VISIONMISSION
VISION
--- Content provided by FirstRanker.com ---
MISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
--- Content provided by FirstRanker.com ---
engineering enabling them to solve complex problems in order to develop real time applications.2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
technologies.
--- Content provided by FirstRanker.com ---
3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
development of society.
--- Content provided by FirstRanker.com ---
4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
--- Content provided by FirstRanker.com ---
5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
--- Content provided by FirstRanker.com ---
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
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d. Graduates will be able to design a system, component or process as per needs and specifications.e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
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h. Graduates will be able to communicate effectively by both verbal and written form.i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
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CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
SYLLABUS
Objectives:
The student should be made to:
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? Understand the various logic gates.? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
? Learn to use HDL
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List of experiments:1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
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a. 4 ? bit binary adder / subtractorb. Parity generator / checker
c. Magnitude Comparator
d. Application using multiplexers
4. Design and implementation of sequential circuits:
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a. Shift ?registersb. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
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Course Outcomes:? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
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? Design and Implement a simple digital system.--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Content
Sl.No. Name of the Experiment Page No.
1.
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Verification of Boolean Theorems using Digital Logic Gates2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
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3.Implementation of half adder and full adder
4.
Implementation of half subtractor and full subtractor
5.
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Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates andMSI Devices
6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
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Devices7.
Design and Implementation of Magnitude Comparator.
8.
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Design and Implementation of Application using Multiplexers / Demultiplexers.9.
Design and Implementation of Shift Registers.
10.
Design and Implementation of Synchronous and Asynchronous Counters.
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11.Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
12.
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Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).--- Content provided by FirstRanker.com ---
7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.1: STUDY OF BASIC GATES
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Aim:To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. NAND gate IC 7400 16. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND gate
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The AND gate performs a logical multiplication commonly known as AND function. Theoutput is high when both the inputs are high. The output is low level when any one of the inputs is
low.
OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
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high when any one of the inputs is high. The output is low level when both the inputs are low.NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
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The NAND gate is a contraction of AND-NOT. The output is high when both inputs are lowand any one of the input is low .The output is low level when both inputs are high.
NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
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EX-OR gateAn Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
AND Gate Symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
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OR Gate:--- Content provided by FirstRanker.com ---
OR GATE:--- Content provided by FirstRanker.com ---
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00NAND Gate symbol: PIN Diagram:
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NOR Gate:--- Content provided by FirstRanker.com ---
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
--- Content provided by FirstRanker.com ---
1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
th
pin is grounded and 14
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thpin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
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Result:The truth tables of all the basic logic gates were verified.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to verify the truth
table of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
3. How many gates presented in IC 7408?
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4. What is IC?5. What are the applications of gates?
6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
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9. Write the truth table of NAND gate.10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
13. What are types of linear integrated circuit?
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14. What is meant by etching?15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Expt.No.2:VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gates
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
--- Content provided by FirstRanker.com ---
5. NAND gate IC 7400 16. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
BASIC Boolean Laws
--- Content provided by FirstRanker.com ---
1. Commutative LawThe binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A
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2. Associative Law
The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
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2. A.(B.C) = (A.B).C3. Distributive Law
The binary operator OR, AND is said to be distributive if,
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1. A+(B.C) = (A+B).(A+C)2. A.(B+C) = (A.B)+(A.C)
4. Absorption Law
--- Content provided by FirstRanker.com ---
1. A+AB = A2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
5. Idempotent Law1. A+A = A
2. A.A = A
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6. Complementary Law1. A+A' = 1
2. A.A' = 0
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7. De Morgan ?s Theorem1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
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2. The complement of the product is equal to the sum of the individual complements.A.B = A+B
Design
--- Content provided by FirstRanker.com ---
1. Absorption LawA+AB = A
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
2. Involution (or) Double complement LawA = A
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
3. Idempotent Law
1. A+A = A
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2. A.A = A--- Content provided by FirstRanker.com ---
14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
4. Demorgan ?s Law
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A+B = A.B5. Distributive Law
A+(B.C) = (A+B).(A+C)
--- Content provided by FirstRanker.com ---
Procedure:
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
cc
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.3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
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Result:Thus the above stated Boolean laws are verified.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to know the basic laws with their truth table.1. What is Demorgan?s law?
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2. What is associative law?3. What is mean by compliment gate?
4. Explain the basic laws in digital electronics
5. What is double complement?
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Viva ? Voce--- Content provided by FirstRanker.com ---
15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
To design and verify the truth table of the Half Adder & Full Adder circuits
--- Content provided by FirstRanker.com ---
Apparatus required:
S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
--- Content provided by FirstRanker.com ---
2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
--- Content provided by FirstRanker.com ---
Theory:
The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
--- Content provided by FirstRanker.com ---
0 + 0 = 0
0 + 1 = 1
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1 + 0 = 11 + 1 = 0 (with 1 as carry)
The first three operations produce a sum of whose length is one digit, but when the last operation is
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performed the sum is two digits. The higher significant bit of this result is called a carry and lowersignificant bit is called the sum.
Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
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Full adder:
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
--- Content provided by FirstRanker.com ---
From the truth table, the expression for sum and carry bits of the output can be obtained as,
SUM = A?B?C + A?BC? + AB?C? + ABC
CARRY = A?BC + AB?C + ABC? +ABC
--- Content provided by FirstRanker.com ---
16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Half Adder
Truth table:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
S = A B
Carry, C = A . B
--- Content provided by FirstRanker.com ---
Circuit diagram:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Full adder
Truth table:
Sl.No. Input Output
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A B C S C1. 0 0 0 0 0
2. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
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5. 1 0 0 1 06. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input Output
A B S C
1. 0 0 0 0
2. 0 1 1 0
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3. 1 0 1 04. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Sum:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
--- Content provided by FirstRanker.com ---
Carry:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CARRY = AB + AC + BC
Logic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Procedure:
1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
--- Content provided by FirstRanker.com ---
thpin is grounded and 14
th
pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
--- Content provided by FirstRanker.com ---
Result:
The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to design the half adder circuit and the
full adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
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Aim:
To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. EX-OR gate IC 7486 16. Connecting wires As required
Theory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
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is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than thesubtrahend bit, hence 1 is borrowed.
Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
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variables designate the minuend and the subtrahend bit, whereas the output variables produce thedifference and borrow bits.
Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
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implemented with two half subtractors and one OR gate.From the truth table the expression for difference and borrow bits of the output can be obtained
as,
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Difference, DIFF= A?B?C + A?BC? + AB?C? + ABCBorrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half subtractor
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Truth table:Sl.No. Input Output
A B Difference Borrow
1. 0 0 0 0
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2. 0 1 1 13. 1 0 1 0
4. 1 1 0 0
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From the truth table the expression for difference and borrow bits of the output can be obtained as,Difference, DIFF = A B
Borrow, BORR = A?. B
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Logic diagram:--- Content provided by FirstRanker.com ---
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2. Full subtractor
Truth table:
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Sl.No.
Input Output
A B C Difference Borrow
1. 0 0 0 0 0
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2. 0 0 1 1 13. 0 1 0 1 1
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 0
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7. 1 1 0 0 08. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
Borrow
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Borrow = A?B + A?C + BC
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Circuit diagram:--- Content provided by FirstRanker.com ---
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
Aim:
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To design and implement 4-bit adder and subtractor using IC 7483Apparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. IC IC 7483 1
3. NOT gate IC 7404 1
4. EX-OR gate IC 7486 1
5. Connecting wires As required
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Theory:
4 BIT Binary adder:
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A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can beconstructed with full adders connected in cascade, with the output carry from each full adder connected to
the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
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0and it ripples through
the full adder to the output carry C
4
.
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4 BIT Binary subtractor:The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
?B? and the corresponding input of full adder. The input carry C
0
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must be equal to 1 when performingsubtraction.
4 BIT Binary adder / subtractor:
The addition and subtraction operation can be combined into one circuit with one common binary
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adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, itbecomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PIN Diagram for IC 7483:
Logic Diagram: 4-Bit Binary Diagram:
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Logic diagram: 4-Bit Binary Subtractor:
4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:
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Procedure:
1. Connections are given as per the circuit diagrams.
2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
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.Result:
The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
verified.
Outcome:
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At the completion of an experiment student will able to design 4-bit binary adder and subtractorInput Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
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1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 00 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
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1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 125 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?
2. Write the truth table for half adder.
3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
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5. Write the truth table for full subtrator.6. Draw the logic diagram of full subtrator.
7. What is adder?
8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
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10. What is combinational circuit?11. What is different between combinational and sequential circuit?
12. What are the gates involved for binary adder?
13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.6: MAGNITUDE COMPARATOR
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Aim:
To design, construct and study the performance of 2 bit magnitude comparator
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
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6. EX-OR gate IC 7486 17. Connecting wires As required
Theory:
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The comparison of two numbers is an operator that determines one number is greater than, lessthan (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
three binary variables that indicate whether A>B, A=B (or) A
Truth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Logic Diagram:
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Pin Diagram for IC 7485:
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Logic Diagram:29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:Truth table:
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Procedure:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
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3. Observe the output and verify the truth table.Result:
Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
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Outcome:
At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
comparator using logic gates.
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A B A>B A=B A0 0 0 0
0 0 0 0
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0 0 0 00 0 0 0
0 1 0
0 0 0 1
0 0 0 1
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0 0 0 00 0 0 0
1 0 0
0 0 0 0
0 0 0 0
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0 0 0 10 0 0 1
0 0 1
Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is magnitude comparator?
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2. What is most significant bit?3. Explain operation of AND gate.
4. Explain truth table of a comparator.
5. Explain magnitude comparator7485 IC.
6. What is 8-bit input Magnitude Comparator?
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7. What is IC?8. Explain the k-map simplification of A>B.
9. Explain the k-map simplification of A=B.
10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
12. What is the truth table of 1-bit magnitude comparator?
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13. What is the use of magnitude comparator?--- Content provided by FirstRanker.com ---
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Expt.No.7: CODE CONVERSION
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31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Aim:
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To design, construct and study the performance of 4-bit different code converters(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
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7. Connecting wires As requiredTheory:
The availability of large variety of codes for the same discrete elements of information results in
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the use of different codes by different systems. A conversion circuit must be inserted between the twosystems if each uses different codes for same information. Thus, code converter is a circuit that makes the
two systems compatible even though each uses different binary code. The bit combination assigned to
binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
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and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit isdesigned. The Boolean functions are obtained from K-Map for each output variable. A code converter is a
circuit that makes the two systems compatible even though each uses a different binary code. To convert
from binary code to Excess-3 code, the input lines must supply the bit combination of elements as
specified by code and the output lines generate the corresponding bit combination of code. Each one of the
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four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are
various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is
C+D has been used to implement partially each of three outputs.
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Logic diagram:
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32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
(i) Binary to gray code converter
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Logic Diagram:
K map for G3:
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G3 = B3
K map for G2:
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K map for G1:
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33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for G0:
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Truth table:
0
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00
0
0
0
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00
1
1
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
0
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
0
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
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(ii) Gray to binary code converter34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:
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K map for B3:
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B3=G3K map for B2:
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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G3 G2 G1 G0 B3 B2 B1 B0
0
0
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00
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
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0
0
0
0
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00
0
0
1
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11
1
1
1
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11
0
0
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00
1
1
1
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10
0
0
0
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11
1
1
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00
1
1
0
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01
1
0
0
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11
0
0
1
--- Content provided by FirstRanker.com ---
10
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
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01
0
1
0
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10
1
K map for B1:
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K map for B0:
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Truth table:
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00(iii) BCD to excess-3 code converter
Logic Diagram:
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K map for E3:
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E3 = B3 + B2 (B0 + B1)K map for E2:
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for E1:
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K map for E0:
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Truth table:
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(iv) Excess-3 to
B3 B2 B1 B0 G3 G2 G1 G0
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00
0
0
0
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00
0
1
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
0
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
1
x
x
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xx
x
x
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
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xx
x
x
x
--- Content provided by FirstRanker.com ---
x1
0
0
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11
0
0
1
--- Content provided by FirstRanker.com ---
10
x
x
x
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xx
x
1
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01
0
1
0
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10
1
0
x
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xx
x
x
x
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38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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BCD code converterLogic Diagram:
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K map for A:A = X1 X2 + X3 X4 X1
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K map for B:--- Content provided by FirstRanker.com ---
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39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for C:
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K map for D:
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Truth table:
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B3 B2 B1 B0 G3 G2 G1 G00
0
0
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00
1
1
1
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11
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
0
0
0
0
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
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40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections were given as per circuit diagram.
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2. Logical inputs were given as per truth table3. Observe the logical output and verify with the truth tables.
Result:
Thus the code converters were designed and verified using the corresponding truth table.
--- Content provided by FirstRanker.com ---
Outcome:
At the completion of an experiment student will able to design the binary to gray converter.
--- Content provided by FirstRanker.com ---
1. What is binary code?2. What is gray code?
3. What are the advantages of gray code?
4. What is unit distance code?
5. What is sequential code?
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6. How to convert binary to gray code?7. How to convert gray to binary code?
8. What is reflective code?
9. What are the advantages of EX ? 3 code?
10. Which code is used to arithmetic operation in digital circuits?
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11. Explain the operation of EX ? OR.12. What is K ? Map?
13. Draw the truth table of EX- OR gate.
14. What is SOP?
15. What is POS?
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16. What is minterm?--- Content provided by FirstRanker.com ---
Viva ? Voce
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41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.8: PARITY GENERATORS AND CHECKERS
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Aim:
To implement the odd and even parity checkers using the logic gates and also to generate the odd parity
and even parity numbers using the generators
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Apparatus required:Sl. No Component Type Quantity
1 Trainer Kit - 1
2 EX-OR IC7486 1
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3 NOT gate IC 7404 14 Connecting wires - Required
Theory:
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Parity checking is used for error detection in data transmission.Odd parity checkers:
It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
odd.
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Even parity checker:
It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
even.
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Odd parity generators:
It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also
the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bits
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which is an odd parity number.Even parity generator:
It generates an even parity number. The even parity checker circuit is used with the inverted output and
also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5
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bits which is an even parity number.--- Content provided by FirstRanker.com ---
42 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Truth table:
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Input Checker output Generator outputA B C D D odd even odd even
0 0 0 1 1 0 00010 00011
0 0 1 0 1 0 00100 00101
0 0 1 1 0 1 00111 00110
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0 1 0 0 1 0 01000 010010 1 0 1 0 1 01011 01010
0 1 1 0 0 1 01101 01100
0 1 1 1 1 0 01110 01111
1 0 0 0 1 0 10000 10001
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1 0 0 1 0 1 10011 100101 0 1 0 0 1 10101 10100
1 0 1 1 1 0 10110 10111
1 1 0 0 0 1 11001 11000
1 1 0 1 1 0 11010 11011
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1 1 1 0 1 0 11100 111011 1 1 1 0 1 11111 11110
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Procedure:1. The circuit is implemented using logic gates.
2. The inputs are given as per the truth table.
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3. The corresponding outputs are noted.4. The theoretical and practical values were verified.
Result:
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The odd and even parity checkers are implemented using the logic gates and the odd parity andeven parity numbers are generated using the corresponding generators.
Outcome:
At the completion of an experiment student will able to verify the odd and even parity checker
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using logic gates.--- Content provided by FirstRanker.com ---
FirstRanker.com - FirstRanker's Choice
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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
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CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
Name : _______________________________________
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Register No : _______________________________________Section : _______________________________________
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LABORATORY MANUAL
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2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
training.
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? To provide competent technical manpower capable of meeting requirements of the industry
--- Content provided by FirstRanker.com ---
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
--- Content provided by FirstRanker.com ---
heart and soulDEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
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To provide candidates with knowledge and skill in the field of Electrical and ElectronicsEngineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
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? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
--- Content provided by FirstRanker.com ---
professional ethical code.? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
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VISION
MISSION
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VISIONMISSION
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3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
1. Fundamentals
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To provide students with a solid foundation in mathematics, science and fundamentals ofengineering enabling them to solve complex problems in order to develop real time applications.
2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
--- Content provided by FirstRanker.com ---
technologies.3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
--- Content provided by FirstRanker.com ---
development of society.4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
--- Content provided by FirstRanker.com ---
professional ethics at all strategies.5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM OUTCOMES (POs)a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
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c. Graduates will be able to design and conduct experiments, analyze and interpret data.d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
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g. Graduates will demonstrate knowledge of professional and ethical responsibilities.h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
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k. Graduate who can participate and succeed in competitive examinations.--- Content provided by FirstRanker.com ---
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CS8381 DIGITAL SYSTEMS LABORATORY5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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SYLLABUS
Objectives:
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The student should be made to:? Understand the various logic gates.
? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
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? Learn to use HDLList of experiments:
1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
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3. Design and implementation of combinational circuits using MSI devices:a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
c. Magnitude Comparator
d. Application using multiplexers
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4. Design and implementation of sequential circuits:a. Shift ?registers
b. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
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Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
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? Design the different functional units in a digital computer system.? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Content
Sl.No. Name of the Experiment Page No.
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1.Verification of Boolean Theorems using Digital Logic Gates
2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
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3.
Implementation of half adder and full adder
4.
Implementation of half subtractor and full subtractor
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5.Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
6.
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Design and Implementation of Parity Generator / Checker using Basic Gates and MSIDevices
7.
Design and Implementation of Magnitude Comparator.
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8.Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
Design and Implementation of Shift Registers.
10.
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Design and Implementation of Synchronous and Asynchronous Counters.11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
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12.Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.1: STUDY OF BASIC GATES
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Aim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. NAND gate IC 7400 1
6. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
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AND gateThe AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
low.
OR gate
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The OR gate performs a logical addition commonly known as OR function. The output ishigh when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
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NAND gateThe NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
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output is low when one or both inputs are high.EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
EXOR Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
th
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pin is grounded and 14th
pin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
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Result:
The truth tables of all the basic logic gates were verified.
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Outcome:At the completion of an experiment student will able to verify the truth
table of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
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3. How many gates presented in IC 7408?4. What is IC?
5. What are the applications of gates?
6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
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8. Write the truth table of NOT gate.9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
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13. What are types of linear integrated circuit?14. What is meant by etching?
15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.2:
VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gates
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. NAND gate IC 7400 1
6. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
BASIC Boolean Laws
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1. Commutative Law
The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
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2. A.B=B.A2. Associative Law
The binary operator OR, AND is said to be associative if,
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1. A+(B+C) = (A+B)+C2. A.(B.C) = (A.B).C
3. Distributive Law
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The binary operator OR, AND is said to be distributive if,1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
4. Absorption Law
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1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
1. A+A = A
2. A.A = A
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6. Complementary Law
1. A+A' = 1
2. A.A' = 0
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7. De Morgan ?s Theorem
1. The complement of the sum is equal to the sum of the product of the individual
complements.
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A+B = A.B2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design1. Absorption Law
A+AB = A
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2. Involution (or) Double complement Law
A = A
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3. Idempotent Law
1. A+A = A
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2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:004. Demorgan ?s Law
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A+B = A.B
5. Distributive Law
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A+(B.C) = (A+B).(A+C)Procedure:
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
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cc.
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
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Result:
Thus the above stated Boolean laws are verified.
Outcome:
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At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?2. What is associative law?
3. What is mean by compliment gate?
4. Explain the basic laws in digital electronics
5. What is double complement?
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Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
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To design and verify the truth table of the Half Adder & Full Adder circuitsApparatus required:
S. No. Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
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6. Connecting wires As requiredTheory:
The most basic arithmetic operation is the addition of two binary digits. There are four
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possible elementary operations, namely,0 + 0 = 0
0 + 1 = 1
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1 + 0 = 1
1 + 1 = 0 (with 1 as carry)
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The first three operations produce a sum of whose length is one digit, but when the last operation isperformed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
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designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.Full adder:
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
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with two half adders and one OR gate.From the truth table, the expression for sum and carry bits of the output can be obtained as,
SUM = A?B?C + A?BC? + AB?C? + ABC
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CARRY = A?BC + AB?C + ABC? +ABC16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half Adder
Truth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
S = A B
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Carry, C = A . BCircuit diagram:
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Full adder
Truth table:
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Sl.No. Input OutputA B C S C
1. 0 0 0 0 0
2. 0 0 1 1 0
3. 0 1 0 1 0
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4. 0 1 1 0 15. 1 0 0 1 0
6. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input Output
A B S C
1. 0 0 0 0
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2. 0 1 1 03. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Sum:--- Content provided by FirstRanker.com ---
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B CCarry:
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CARRY = AB + AC + BC
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Logic Diagram:18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections are given as per the circuit diagrams.
--- Content provided by FirstRanker.com ---
2. For all the IC?s 7th
pin is grounded and 14
th
pin is given +5 V supply.
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3. Apply the inputs and verify the truth table for the half adder and full adder circuits.Result:
The design of the half adder and full adder circuits was done and their truth tables were verified.
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Outcome:At the completion of an experiment student will able to design the half adder circuit and the
full adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTORAim:
To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. EX-OR gate IC 7486 1
6. Connecting wires As required
Theory:
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The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bitis subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
subtrahend bit, hence 1 is borrowed.
Half subtractor:
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A combinational circuit which performs the subtraction of two bits is called half subtractor. The inputvariables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
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three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can beimplemented with two half subtractors and one OR gate.
From the truth table the expression for difference and borrow bits of the output can be obtained
as,
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Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
Borrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half subtractor
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Truth table:
Sl.No. Input Output
A B Difference Borrow
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1. 0 0 0 02. 0 1 1 1
3. 1 0 1 0
4. 1 1 0 0
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From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A B
Borrow, BORR = A?. B
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Logic diagram:
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2. Full subtractor
Truth table:
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Sl.No.
Input Output
A B C Difference Borrow
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1. 0 0 0 0 02. 0 0 1 1 1
3. 0 1 0 1 1
4. 0 1 1 0 1
5. 1 0 0 1 0
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6. 1 0 1 0 07. 1 1 0 0 0
8. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
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Borrow--- Content provided by FirstRanker.com ---
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Borrow = A?B + A?C + BC
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Circuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
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Aim:To design and implement 4-bit adder and subtractor using IC 7483
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. IC IC 7483 1
3. NOT gate IC 7404 1
4. EX-OR gate IC 7486 1
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5. Connecting wires As requiredTheory:
4 BIT Binary adder:
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A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected to
the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
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carries are connected in chain through full adder. The input carry to the adder is C0
and it ripples through
the full adder to the output carry C
4
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.4 BIT Binary subtractor:
The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
?B? and the corresponding input of full adder. The input carry C
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0must be equal to 1 when performing
subtraction.
4 BIT Binary adder / subtractor:
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The addition and subtraction operation can be combined into one circuit with one common binaryadder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
becomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PIN Diagram for IC 7483:
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Logic Diagram: 4-Bit Binary Diagram:Logic diagram: 4-Bit Binary Subtractor:
4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:
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Procedure:
1. Connections are given as per the circuit diagrams.
2. Logical inputs were given as per circuit diagram.
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3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor..
Result:
The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
verified.
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Outcome:At the completion of an experiment student will able to design 4-bit binary adder and subtractor
Input Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
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1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 01 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
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1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 11 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
1. What is expression for difference and borrow?
2. Write the truth table for half adder.
3. Write the truth table for full adder.
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4. Write the truth table for half subtrator.5. Write the truth table for full subtrator.
6. Draw the logic diagram of full subtrator.
7. What is adder?
8. List out the application of adders.
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9. Draw the full adder using two half adder circuits.10. What is combinational circuit?
11. What is different between combinational and sequential circuit?
12. What are the gates involved for binary adder?
13. List the properties of Ex-Nor gate?
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14. What is expression for sum and carry?--- Content provided by FirstRanker.com ---
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.6: MAGNITUDE COMPARATORAim:
To design, construct and study the performance of 2 bit magnitude comparator
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. Magnitude comparator IC 7485 26. EX-OR gate IC 7486 1
7. Connecting wires As required
Theory:
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The comparison of two numbers is an operator that determines one number is greater than, less
than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
three binary variables that indicate whether A>B, A=B (or) A
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Truth table:--- Content provided by FirstRanker.com ---
27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Logic Diagram:
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Pin Diagram for IC 7485:
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
8 Bit Magnitude Comparator:
Truth table:
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Procedure:
1. Connections are given as per circuit diagram.
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2. Logical inputs are given as per circuit diagram.3. Observe the output and verify the truth table.
Result:
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Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.Outcome:
At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
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comparator using logic gates.--- Content provided by FirstRanker.com ---
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A B A>B A=B A0 0 0 0
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0 0 0 00 0 0 0
0 0 0 0
0 1 0
0 0 0 1
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0 0 0 10 0 0 0
0 0 0 0
1 0 0
0 0 0 0
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0 0 0 00 0 0 1
0 0 0 1
0 0 1
Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is magnitude comparator?2. What is most significant bit?
3. Explain operation of AND gate.
4. Explain truth table of a comparator.
5. Explain magnitude comparator7485 IC.
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6. What is 8-bit input Magnitude Comparator?7. What is IC?
8. Explain the k-map simplification of A>B.
9. Explain the k-map simplification of A=B.
10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
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12. What is the truth table of 1-bit magnitude comparator?13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION
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31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Aim:To design, construct and study the performance of 4-bit different code converters
(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
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(iv) Excess-3 to BCD code converterApparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
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6. EX-OR gate IC 7486 17. Connecting wires As required
Theory:
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The availability of large variety of codes for the same discrete elements of information results inthe use of different codes by different systems. A conversion circuit must be inserted between the two
systems if each uses different codes for same information. Thus, code converter is a circuit that makes the
two systems compatible even though each uses different binary code. The bit combination assigned to
binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
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and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a
circuit that makes the two systems compatible even though each uses a different binary code. To convert
from binary code to Excess-3 code, the input lines must supply the bit combination of elements as
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specified by code and the output lines generate the corresponding bit combination of code. Each one of thefour maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are
various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is
C+D has been used to implement partially each of three outputs.
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Logic diagram:
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32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(i) Binary to gray code converterLogic Diagram:
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K map for G3:G3 = B3
K map for G2:
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K map for G1:
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33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for G0:
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Truth table:
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00
0
0
0
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00
0
1
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
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00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
0
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
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10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
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00
1
1
0
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(ii) Gray to binary code converter
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34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Logic Diagram:
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K map for B3:
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B3=G3
K map for B2:
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00G3 G2 G1 G0 B3 B2 B1 B0
0
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00
0
0
0
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00
1
1
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
0
0
0
0
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11
1
1
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
00
0
0
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11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
0
0
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00
0
0
0
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11
1
1
1
--- Content provided by FirstRanker.com ---
11
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
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11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
0
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
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11
0
1
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01
0
1
0
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10
1
0
1
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01
0
1
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K map for B1:K map for B0:
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Truth table:
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
(iii) BCD to excess-3 code converter
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Logic Diagram:K map for E3:
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E3 = B3 + B2 (B0 + B1)
K map for E2:
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00K map for E1:
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K map for E0:
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Truth table:
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(iv) Excess-3 to
B3 B2 B1 B0 G3 G2 G1 G0
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0
0
0
0
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00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
--- Content provided by FirstRanker.com ---
00
0
0
1
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11
1
1
x
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xx
x
x
x
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0
1
1
1
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10
0
0
0
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1x
x
x
x
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xx
1
0
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01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
x
x
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xx
x
x
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10
1
0
1
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01
0
1
0
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xx
x
x
x
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x38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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BCD code converter
Logic Diagram:
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K map for A:
A = X1 X2 + X3 X4 X1
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K map for B:
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39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00K map for C:
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K map for D:
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Truth table:
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B3 B2 B1 B0 G3 G2 G1 G0
0
0
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00
0
1
1
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11
1
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
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00
1
1
0
--- Content provided by FirstRanker.com ---
1
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
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40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Procedure:
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1. Connections were given as per circuit diagram.2. Logical inputs were given as per truth table
3. Observe the logical output and verify with the truth tables.
Result:
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Thus the code converters were designed and verified using the corresponding truth table.Outcome:
At the completion of an experiment student will able to design the binary to gray converter.
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1. What is binary code?
2. What is gray code?
3. What are the advantages of gray code?
4. What is unit distance code?
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5. What is sequential code?6. How to convert binary to gray code?
7. How to convert gray to binary code?
8. What is reflective code?
9. What are the advantages of EX ? 3 code?
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10. Which code is used to arithmetic operation in digital circuits?11. Explain the operation of EX ? OR.
12. What is K ? Map?
13. Draw the truth table of EX- OR gate.
14. What is SOP?
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15. What is POS?16. What is minterm?
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Viva ? Voce
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41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.8: PARITY GENERATORS AND CHECKERSAim:
To implement the odd and even parity checkers using the logic gates and also to generate the odd parity
and even parity numbers using the generators
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Apparatus required:
Sl. No Component Type Quantity
1 Trainer Kit - 1
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2 EX-OR IC7486 13 NOT gate IC 7404 1
4 Connecting wires - Required
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Theory:Parity checking is used for error detection in data transmission.
Odd parity checkers:
It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
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odd.Even parity checker:
It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
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even.Odd parity generators:
It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also
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the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bitswhich is an odd parity number.
Even parity generator:
It generates an even parity number. The even parity checker circuit is used with the inverted output and
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also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5bits which is an even parity number.
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42 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Truth table:
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Input Checker output Generator output
A B C D D odd even odd even
0 0 0 1 1 0 00010 00011
0 0 1 0 1 0 00100 00101
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0 0 1 1 0 1 00111 001100 1 0 0 1 0 01000 01001
0 1 0 1 0 1 01011 01010
0 1 1 0 0 1 01101 01100
0 1 1 1 1 0 01110 01111
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1 0 0 0 1 0 10000 100011 0 0 1 0 1 10011 10010
1 0 1 0 0 1 10101 10100
1 0 1 1 1 0 10110 10111
1 1 0 0 0 1 11001 11000
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1 1 0 1 1 0 11010 110111 1 1 0 1 0 11100 11101
1 1 1 1 0 1 11111 11110
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Procedure:
1. The circuit is implemented using logic gates.
2. The inputs are given as per the truth table.
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3. The corresponding outputs are noted.
4. The theoretical and practical values were verified.
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Result:The odd and even parity checkers are implemented using the logic gates and the odd parity and
even parity numbers are generated using the corresponding generators.
Outcome:
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At the completion of an experiment student will able to verify the odd and even parity checkerusing logic gates.
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43 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is parity bit?
2. Why parity bit is added to message?
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3. What is parity checker?4. What is odd parity?
5. What is even parity?
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6. What are the gates involved for parity generator?7. List the procedures to convert gray code into binary.
8. Why weighted code is called as reflective codes?
9. What is a sequential code?
10. What is error deducting code?
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11. What is ASCII code?12. What is hamming code?
13. List the binary weighted code.
14. List the binary non weighted code.
15. Write the hamming code equation
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16. List the procedures to convert binary code into gray17. What are the applications of gray code?
18. What are the applications of Excess- 3 code?
Viva ? Voce
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FirstRanker.com - FirstRanker's Choice1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
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III SEMESTER - R 2017
CS8382 DIGITAL SYSTEMS LABORATORY
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Name : _______________________________________
Register No : _______________________________________
Section : _______________________________________
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LABORATORY MANUAL
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2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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is committed to provide highly disciplined, conscientious and
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enterprising professionals conforming to global standards through value based quality education andtraining.
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? To provide competent technical manpower capable of meeting requirements of the industry
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
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? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
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DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
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To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
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? To provide the students rigorous learning experience to produce creative solutions to society?s
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needs.? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
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industry by continuous assessment and training.VISION
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MISSIONVISION
MISSION
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3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
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1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
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2. Core CompetenceTo train the students to meet the needs of core industry with an attitude of learning new
technologies.
3. Breadth
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To provide relevant training and experience to bridge the gap between theory and practice whichenable them to find solutions to problems in industry and research that contributes to the overall
development of society.
4. Professionalism
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To inculcate professional and effective communication skills to the students to make them lead ateam and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
5. Lifelong Learning/Ethics
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To practice ethical and professional responsibilities in the organization and society withcommitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
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f. Graduates will demonstrate skills to use modern engineering tools, software and equipment toanalyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
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will be aware of contemporary issues.j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
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CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
SYLLABUS
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Objectives:
The student should be made to:
? Understand the various logic gates.
? Be familiar with various combinational circuits.
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? Understand the various components used in the design of digital computers.? Be exposed to sequential circuits
? Learn to use HDL
List of experiments:
1. Verification of Boolean Theorems using basic gates.
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2. Design and implementation of combinational circuits using basic gates for arbitraryfunctions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
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c. Magnitude Comparatord. Application using multiplexers
4. Design and implementation of sequential circuits:
a. Shift ?registers
b. Synchronous and asynchronous counters
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5. Coding combinational / sequential circuits using HDL.6. Design and implementation of a simple digital system (Mini Project).
Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
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? Design and Implement combinational and sequential circuits.? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Content
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Sl.No. Name of the Experiment Page No.
1.
Verification of Boolean Theorems using Digital Logic Gates
2.
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Design and Implementation of Combinational Circuits using Basic Gates for ArbitraryFunctions, Code Converters
3.
Implementation of half adder and full adder
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4.Implementation of half subtractor and full subtractor
5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
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6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
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7.Design and Implementation of Magnitude Comparator.
8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
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Design and Implementation of Shift Registers.10.
Design and Implementation of Synchronous and Asynchronous Counters.
11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
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HDL Software Required).12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.1: STUDY OF BASIC GATES
Aim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
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7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
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more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known asuniversal gates. Basic gates form these gates.
AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
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low.OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
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A NOT gate is the physical realization of the complementation operation. The NOT gate iscalled an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
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NOR gateThe NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
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similar to OR gate but excludes the combination of both A and B being equal to one. The exclusiveOR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Procedure:
1. Connections are given as per the circuit diagram.
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2. For all the IC?s 7th
pin is grounded and 14
th
pin is given +5 supply.
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3. Apply the inputs and verify the truth table for all gates.Result:
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The truth tables of all the basic logic gates were verified.Outcome:
At the completion of an experiment student will able to verify the truth
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table of all basic gates--- Content provided by FirstRanker.com ---
1. List out the basic gate.2. Mention the universal gate.
3. How many gates presented in IC 7408?
4. What is IC?
5. What are the applications of gates?
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6. Write the truth table of AND gate.7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
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11. Write the truth table of EX- OR gate.12. What are the classifications of IC?
13. What are types of linear integrated circuit?
14. What is meant by etching?
15. What are the advantages of IC?
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16. Write the truth table of EX- NOR gate.Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.2:
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VERIFICATION OF BOOLEAN THEOREMS USING LOGICGATES
Aim: To verification of Boolean theorems using logic gates
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 3
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7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
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BASIC Boolean Laws
1. Commutative Law
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The binary operator OR, AND is said to be commutative if,1. A+B = B+A
2. A.B=B.A
2. Associative Law
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The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
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3. Distributive LawThe binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
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4. Absorption Law
1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
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1. A+A = A2. A.A = A
6. Complementary Law
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1. A+A' = 12. A.A' = 0
7. De Morgan ?s Theorem
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1. The complement of the sum is equal to the sum of the product of the individualcomplements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design
1. Absorption Law
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A+AB = A--- Content provided by FirstRanker.com ---
2. Involution (or) Double complement Law
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A = A--- Content provided by FirstRanker.com ---
3. Idempotent Law
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1. A+A = A
2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
A+B = A.B
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5. Distributive Law
A+(B.C) = (A+B).(A+C)
Procedure:
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1. Obtain the required IC along with the Digital trainer kit.2. Connect zero volts to GND pin and +5 volts to V
cc
.
3. Apply the inputs to the respective input pins.
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4. Verify the output with the truth table.Result:
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Thus the above stated Boolean laws are verified.Outcome:
At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?
2. What is associative law?
3. What is mean by compliment gate?
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4. Explain the basic laws in digital electronics5. What is double complement?
Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.3: HALF ADDER AND FULL ADDERAim:
To design and verify the truth table of the Half Adder & Full Adder circuits
Apparatus required:
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S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
0 + 0 = 0
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0 + 1 = 1
1 + 0 = 1
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1 + 1 = 0 (with 1 as carry)The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
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Half adder:A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
Full adder:
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A combinational circuit which performs the arithmetic sum of three input bits is called full adder. Thethree input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
From the truth table, the expression for sum and carry bits of the output can be obtained as,
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SUM = A?B?C + A?BC? + AB?C? + ABCCARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half Adder
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Truth table:--- Content provided by FirstRanker.com ---
From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
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S = A BCarry, C = A . B
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Circuit diagram:--- Content provided by FirstRanker.com ---
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Full adder
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Truth table:Sl.No. Input Output
A B C S C
1. 0 0 0 0 0
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2. 0 0 1 1 03. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
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7. 1 1 0 0 18. 1 1 1 1 1
Sl.No. Input Output
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A B S C1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:--- Content provided by FirstRanker.com ---
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CARRY = AB + AC + BC
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Logic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
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1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
th
pin is grounded and 14
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thpin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
Result:
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The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
At the completion of an experiment student will able to design the half adder circuit and the
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full adder circuit.--- Content provided by FirstRanker.com ---
19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
Aim:
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To design and verify the truth table of the half subtractor & full subtractor circuitsApparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
subtrahend bit, hence 1 is borrowed.
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Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
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Full subtractor:A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
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From the truth table the expression for difference and borrow bits of the output can be obtainedas,
Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
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Borrow, BORR = A?BC + AB?C + ABC? +ABC--- Content provided by FirstRanker.com ---
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half subtractor
Truth table:
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Sl.No. Input OutputA B Difference Borrow
1. 0 0 0 0
2. 0 1 1 1
3. 1 0 1 0
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4. 1 1 0 0From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A B
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Borrow, BORR = A?. B
Logic diagram:
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2. Full subtractorTruth table:
Sl.No.
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Input OutputA B C Difference Borrow
1. 0 0 0 0 0
2. 0 0 1 1 1
3. 0 1 0 1 1
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4. 0 1 1 0 15. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
8. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
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Borrow
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Borrow = A?B + A?C + BCCircuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
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Aim:
To design and implement 4-bit adder and subtractor using IC 7483
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. IC IC 7483 1
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3. NOT gate IC 7404 14. EX-OR gate IC 7486 1
5. Connecting wires As required
Theory:
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4 BIT Binary adder:
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected to
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the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? aredesignated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
0
and it ripples through
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the full adder to the output carry C4
.
4 BIT Binary subtractor:
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The circuit for subtracting A-B consists of an adder with inverters, placed between each data input?B? and the corresponding input of full adder. The input carry C
0
must be equal to 1 when performing
subtraction.
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4 BIT Binary adder / subtractor:The addition and subtraction operation can be combined into one circuit with one common binary
adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
becomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PIN Diagram for IC 7483:Logic Diagram: 4-Bit Binary Diagram:
Logic diagram: 4-Bit Binary Subtractor:
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4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Truth table:
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Procedure:
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1. Connections are given as per the circuit diagrams.2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
.
Result:
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The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table wasverified.
Outcome:
At the completion of an experiment student will able to design 4-bit binary adder and subtractor
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Input Data A Input Data B Addition SubtractionA4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
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0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 01 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?
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2. Write the truth table for half adder.3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
5. Write the truth table for full subtrator.
6. Draw the logic diagram of full subtrator.
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7. What is adder?8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
10. What is combinational circuit?
11. What is different between combinational and sequential circuit?
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12. What are the gates involved for binary adder?13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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Viva ? Voce--- Content provided by FirstRanker.com ---
26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.6: MAGNITUDE COMPARATOR
Aim:
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To design, construct and study the performance of 2 bit magnitude comparatorApparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:
The comparison of two numbers is an operator that determines one number is greater than, less
than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
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numbers A and B and determines their relative magnitude. The outcome of the comparator is specified bythree binary variables that indicate whether A>B, A=B (or) A
Truth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:
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Pin Diagram for IC 7485:--- Content provided by FirstRanker.com ---
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:
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Truth table:
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Procedure:1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
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Result:Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
Outcome:
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At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
comparator using logic gates.
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A B A>B A=B A0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
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0 1 00 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
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1 0 00 0 0 0
0 0 0 0
0 0 0 1
0 0 0 1
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0 0 1Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is magnitude comparator?
2. What is most significant bit?
3. Explain operation of AND gate.
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4. Explain truth table of a comparator.5. Explain magnitude comparator7485 IC.
6. What is 8-bit input Magnitude Comparator?
7. What is IC?
8. Explain the k-map simplification of A>B.
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9. Explain the k-map simplification of A=B.10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
12. What is the truth table of 1-bit magnitude comparator?
13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Aim:
To design, construct and study the performance of 4-bit different code converters
(i) Binary to gray code converter
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(ii) Gray to binary code converter(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:The availability of large variety of codes for the same discrete elements of information results in
the use of different codes by different systems. A conversion circuit must be inserted between the two
systems if each uses different codes for same information. Thus, code converter is a circuit that makes the
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two systems compatible even though each uses different binary code. The bit combination assigned tobinary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a
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circuit that makes the two systems compatible even though each uses a different binary code. To convertfrom binary code to Excess-3 code, the input lines must supply the bit combination of elements as
specified by code and the output lines generate the corresponding bit combination of code. Each one of the
four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are
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various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output isC+D has been used to implement partially each of three outputs.
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Logic diagram:32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(i) Binary to gray code converter
Logic Diagram:
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K map for G3:
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G3 = B3K map for G2:
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K map for G1:33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for G0:Truth table:
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0
0
0
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00
0
0
0
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11
1
1
1
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11
1
0
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00
0
1
1
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11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
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0
0
1
1
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00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
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11
0
1
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01
0
1
0
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10
1
0
1
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01
0
1
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00
0
0
0
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00
0
1
1
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11
1
1
1
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10
0
0
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01
1
1
1
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11
1
1
0
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00
0
0
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01
1
1
1
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00
0
0
1
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11
1
0
0
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0
1
1
0
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01
1
0
0
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11
0
0
1
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10
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(ii) Gray to binary code converter
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34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:K map for B3:
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B3=G3
K map for B2:
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
G3 G2 G1 G0 B3 B2 B1 B0
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0
0
0
0
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00
0
0
1
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11
1
1
1
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11
0
0
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00
1
1
1
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11
1
1
1
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00
0
0
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00
1
1
1
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10
0
0
0
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11
1
1
0
--- Content provided by FirstRanker.com ---
00
1
1
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00
1
1
0
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01
1
0
0
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11
0
0
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00
0
0
0
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00
1
1
1
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11
1
1
1
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0
0
0
0
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11
1
1
0
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00
0
1
1
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11
0
0
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11
0
0
1
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10
0
1
1
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00
1
1
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01
0
1
0
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10
1
0
1
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01
0
1
0
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1K map for B1:
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K map for B0:
Truth table:
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(iii) BCD to excess-3 code converterLogic Diagram:
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K map for E3:E3 = B3 + B2 (B0 + B1)
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K map for E2:--- Content provided by FirstRanker.com ---
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for E1:--- Content provided by FirstRanker.com ---
K map for E0:--- Content provided by FirstRanker.com ---
Truth table:
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(iv) Excess-3 toB3 B2 B1 B0 G3 G2 G1 G0
0
0
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00
0
0
0
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01
1
1
1
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11
1
1
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00
0
0
1
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11
1
0
0
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00
1
1
1
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10
0
1
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10
0
1
1
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00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
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10
1
0
1
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01
0
1
0
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10
1
0
1
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0
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
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1x
x
x
x
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xx
0
1
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11
1
0
0
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00
1
x
x
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xx
x
x
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10
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1
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00
1
1
0
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xx
x
x
x
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x1
0
1
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01
0
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0
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10
x
x
x
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xx
x
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38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
BCD code converter
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Logic Diagram:K map for A:
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A = X1 X2 + X3 X4 X1
K map for B:
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39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for C:--- Content provided by FirstRanker.com ---
K map for D:--- Content provided by FirstRanker.com ---
Truth table:--- Content provided by FirstRanker.com ---
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B3 B2 B1 B0 G3 G2 G1 G0
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00
0
0
0
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11
1
1
1
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0
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
11
0
0
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11
0
0
1
--- Content provided by FirstRanker.com ---
10
1
0
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10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
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11
1
0
0
--- Content provided by FirstRanker.com ---
0
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
00
1
0
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10
1
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1
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01
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40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections were given as per circuit diagram.
2. Logical inputs were given as per truth table
3. Observe the logical output and verify with the truth tables.
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Result:
Thus the code converters were designed and verified using the corresponding truth table.
Outcome:
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At the completion of an experiment student will able to design the binary to gray converter.1. What is binary code?
2. What is gray code?
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3. What are the advantages of gray code?4. What is unit distance code?
5. What is sequential code?
6. How to convert binary to gray code?
7. How to convert gray to binary code?
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8. What is reflective code?9. What are the advantages of EX ? 3 code?
10. Which code is used to arithmetic operation in digital circuits?
11. Explain the operation of EX ? OR.
12. What is K ? Map?
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13. Draw the truth table of EX- OR gate.14. What is SOP?
15. What is POS?
16. What is minterm?
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Viva ? Voce--- Content provided by FirstRanker.com ---
41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.8: PARITY GENERATORS AND CHECKERS
Aim:
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To implement the odd and even parity checkers using the logic gates and also to generate the odd parityand even parity numbers using the generators
Apparatus required:
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Sl. No Component Type Quantity1 Trainer Kit - 1
2 EX-OR IC7486 1
3 NOT gate IC 7404 1
4 Connecting wires - Required
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Theory:
Parity checking is used for error detection in data transmission.
Odd parity checkers:
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It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
odd.
Even parity checker:
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It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
even.
Odd parity generators:
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It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also
the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bits
which is an odd parity number.
Even parity generator:
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It generates an even parity number. The even parity checker circuit is used with the inverted output and
also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5
bits which is an even parity number.
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42 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:
Input Checker output Generator output
A B C D D odd even odd even
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0 0 0 1 1 0 00010 000110 0 1 0 1 0 00100 00101
0 0 1 1 0 1 00111 00110
0 1 0 0 1 0 01000 01001
0 1 0 1 0 1 01011 01010
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0 1 1 0 0 1 01101 011000 1 1 1 1 0 01110 01111
1 0 0 0 1 0 10000 10001
1 0 0 1 0 1 10011 10010
1 0 1 0 0 1 10101 10100
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1 0 1 1 1 0 10110 101111 1 0 0 0 1 11001 11000
1 1 0 1 1 0 11010 11011
1 1 1 0 1 0 11100 11101
1 1 1 1 0 1 11111 11110
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Procedure:
1. The circuit is implemented using logic gates.
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2. The inputs are given as per the truth table.
3. The corresponding outputs are noted.
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4. The theoretical and practical values were verified.Result:
The odd and even parity checkers are implemented using the logic gates and the odd parity and
even parity numbers are generated using the corresponding generators.
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Outcome:
At the completion of an experiment student will able to verify the odd and even parity checker
using logic gates.
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43 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
1. What is parity bit?
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2. Why parity bit is added to message?3. What is parity checker?
4. What is odd parity?
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5. What is even parity?6. What are the gates involved for parity generator?
7. List the procedures to convert gray code into binary.
8. Why weighted code is called as reflective codes?
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9. What is a sequential code?10. What is error deducting code?
11. What is ASCII code?
12. What is hamming code?
13. List the binary weighted code.
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14. List the binary non weighted code.15. Write the hamming code equation
16. List the procedures to convert binary code into gray
17. What are the applications of gray code?
18. What are the applications of Excess- 3 code?
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Viva ? Voce--- Content provided by FirstRanker.com ---
44 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.9: MULTIPLEXER AND DEMULTIPLEXER
Aim:
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To design and verify the truth table of a 4X1 multiplexer & 1X4 demultiplexerApparatus required:
Sl. No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. OR gate IC 7432 13. NOT gate IC 7404 1
4. AND gate ( three input ) IC 7411 1
5. Connecting wires As required
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Theory:Multiplexing means transmitting a large number of information units over a smaller number of channels or
lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input
lines and directs it to a single output line. The selection of particular input line is controlled by a set of
selection lines. Normally, there are 2
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ninput lines and n selection lines whose bit combinations determines
which input is selected. A multiplexer is called a data selector, since it selects one of many inputs and
steers the binary information to the output line. A Strobe is also provided to allow the designer to disable all
output data until a specified time. Then, by allowing the STROBE to go low, the proper lead can be
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selected. This feature is very useful where data might be changing the same time DATA SELECT leadschange. It is a very useful Medium Scale Integration (MSI) function and has a multitude of applications. It is
used for connecting two or more sources to a single destination among the computer units and it is useful
for constructing a common bus system. A decoder with an enable input can function as a demultiplexer. A
Demultiplexer is a circuit that receives information on a single line and transmits this information on one of
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2n
possible output lines. The selection of specific output line is controlled by the bit values of n selection
lines. The decoder and demultiplexer operations are obtained from the same circuit; a decoder with an
enable input is referred to as a decoder / de-multiplexer. The Strobe lead can be used to active or de-
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active the entire IC, allowing time for the address lines to change the information is fed to the output.Demultiplexers are useful anytime information from one source must be fed several places.
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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
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CS8382 DIGITAL SYSTEMS LABORATORY
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Register No : _______________________________________Section : _______________________________________
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2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
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? To provide competent technical manpower capable of meeting requirements of the industry
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? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
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heart and soulDEPARTMENT OF COMPUTER SCIENCE ENGINEERING
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To provide candidates with knowledge and skill in the field of Electrical and ElectronicsEngineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
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? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
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professional ethical code.? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
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VISION
MISSION
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VISIONMISSION
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3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
1. Fundamentals
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To provide students with a solid foundation in mathematics, science and fundamentals ofengineering enabling them to solve complex problems in order to develop real time applications.
2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
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technologies.3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
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development of society.4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
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professional ethics at all strategies.5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM OUTCOMES (POs)a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
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c. Graduates will be able to design and conduct experiments, analyze and interpret data.d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
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g. Graduates will demonstrate knowledge of professional and ethical responsibilities.h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
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k. Graduate who can participate and succeed in competitive examinations.--- Content provided by FirstRanker.com ---
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CS8381 DIGITAL SYSTEMS LABORATORY5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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SYLLABUS
Objectives:
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The student should be made to:? Understand the various logic gates.
? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
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? Learn to use HDLList of experiments:
1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
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3. Design and implementation of combinational circuits using MSI devices:a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
c. Magnitude Comparator
d. Application using multiplexers
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4. Design and implementation of sequential circuits:a. Shift ?registers
b. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
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Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
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? Design the different functional units in a digital computer system.? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Content
Sl.No. Name of the Experiment Page No.
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1.Verification of Boolean Theorems using Digital Logic Gates
2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
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3.
Implementation of half adder and full adder
4.
Implementation of half subtractor and full subtractor
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5.Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
6.
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Design and Implementation of Parity Generator / Checker using Basic Gates and MSIDevices
7.
Design and Implementation of Magnitude Comparator.
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8.Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
Design and Implementation of Shift Registers.
10.
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Design and Implementation of Synchronous and Asynchronous Counters.11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
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12.Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.1: STUDY OF BASIC GATES
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Aim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. NAND gate IC 7400 1
6. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
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AND gateThe AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
low.
OR gate
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The OR gate performs a logical addition commonly known as OR function. The output ishigh when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
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NAND gateThe NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
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output is low when one or both inputs are high.EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
EXOR Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
th
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pin is grounded and 14th
pin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
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Result:
The truth tables of all the basic logic gates were verified.
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Outcome:At the completion of an experiment student will able to verify the truth
table of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
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3. How many gates presented in IC 7408?4. What is IC?
5. What are the applications of gates?
6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
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8. Write the truth table of NOT gate.9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
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13. What are types of linear integrated circuit?14. What is meant by etching?
15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.2:
VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gates
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. NAND gate IC 7400 1
6. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
BASIC Boolean Laws
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1. Commutative Law
The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
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2. A.B=B.A2. Associative Law
The binary operator OR, AND is said to be associative if,
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1. A+(B+C) = (A+B)+C2. A.(B.C) = (A.B).C
3. Distributive Law
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The binary operator OR, AND is said to be distributive if,1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
4. Absorption Law
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1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
1. A+A = A
2. A.A = A
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6. Complementary Law
1. A+A' = 1
2. A.A' = 0
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7. De Morgan ?s Theorem
1. The complement of the sum is equal to the sum of the product of the individual
complements.
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A+B = A.B2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design1. Absorption Law
A+AB = A
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2. Involution (or) Double complement Law
A = A
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3. Idempotent Law
1. A+A = A
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2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:004. Demorgan ?s Law
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A+B = A.B
5. Distributive Law
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A+(B.C) = (A+B).(A+C)Procedure:
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
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cc.
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
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Result:
Thus the above stated Boolean laws are verified.
Outcome:
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At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?2. What is associative law?
3. What is mean by compliment gate?
4. Explain the basic laws in digital electronics
5. What is double complement?
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Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
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To design and verify the truth table of the Half Adder & Full Adder circuitsApparatus required:
S. No. Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
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6. Connecting wires As requiredTheory:
The most basic arithmetic operation is the addition of two binary digits. There are four
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possible elementary operations, namely,0 + 0 = 0
0 + 1 = 1
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1 + 0 = 1
1 + 1 = 0 (with 1 as carry)
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The first three operations produce a sum of whose length is one digit, but when the last operation isperformed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
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designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.Full adder:
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
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with two half adders and one OR gate.From the truth table, the expression for sum and carry bits of the output can be obtained as,
SUM = A?B?C + A?BC? + AB?C? + ABC
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CARRY = A?BC + AB?C + ABC? +ABC16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half Adder
Truth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
S = A B
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Carry, C = A . BCircuit diagram:
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Full adder
Truth table:
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Sl.No. Input OutputA B C S C
1. 0 0 0 0 0
2. 0 0 1 1 0
3. 0 1 0 1 0
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4. 0 1 1 0 15. 1 0 0 1 0
6. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input Output
A B S C
1. 0 0 0 0
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2. 0 1 1 03. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Sum:--- Content provided by FirstRanker.com ---
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B CCarry:
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CARRY = AB + AC + BC
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Logic Diagram:18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections are given as per the circuit diagrams.
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2. For all the IC?s 7th
pin is grounded and 14
th
pin is given +5 V supply.
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3. Apply the inputs and verify the truth table for the half adder and full adder circuits.Result:
The design of the half adder and full adder circuits was done and their truth tables were verified.
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Outcome:At the completion of an experiment student will able to design the half adder circuit and the
full adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTORAim:
To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. EX-OR gate IC 7486 1
6. Connecting wires As required
Theory:
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The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bitis subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
subtrahend bit, hence 1 is borrowed.
Half subtractor:
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A combinational circuit which performs the subtraction of two bits is called half subtractor. The inputvariables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
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three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can beimplemented with two half subtractors and one OR gate.
From the truth table the expression for difference and borrow bits of the output can be obtained
as,
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Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
Borrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half subtractor
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Truth table:
Sl.No. Input Output
A B Difference Borrow
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1. 0 0 0 02. 0 1 1 1
3. 1 0 1 0
4. 1 1 0 0
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From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A B
Borrow, BORR = A?. B
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Logic diagram:
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2. Full subtractor
Truth table:
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Sl.No.
Input Output
A B C Difference Borrow
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1. 0 0 0 0 02. 0 0 1 1 1
3. 0 1 0 1 1
4. 0 1 1 0 1
5. 1 0 0 1 0
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6. 1 0 1 0 07. 1 1 0 0 0
8. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
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Borrow--- Content provided by FirstRanker.com ---
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Borrow = A?B + A?C + BC
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Circuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
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Aim:To design and implement 4-bit adder and subtractor using IC 7483
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. IC IC 7483 1
3. NOT gate IC 7404 1
4. EX-OR gate IC 7486 1
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5. Connecting wires As requiredTheory:
4 BIT Binary adder:
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A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected to
the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
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carries are connected in chain through full adder. The input carry to the adder is C0
and it ripples through
the full adder to the output carry C
4
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.4 BIT Binary subtractor:
The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
?B? and the corresponding input of full adder. The input carry C
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0must be equal to 1 when performing
subtraction.
4 BIT Binary adder / subtractor:
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The addition and subtraction operation can be combined into one circuit with one common binaryadder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
becomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PIN Diagram for IC 7483:
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Logic Diagram: 4-Bit Binary Diagram:Logic diagram: 4-Bit Binary Subtractor:
4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:
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Procedure:
1. Connections are given as per the circuit diagrams.
2. Logical inputs were given as per circuit diagram.
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3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor..
Result:
The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
verified.
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Outcome:At the completion of an experiment student will able to design 4-bit binary adder and subtractor
Input Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
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1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 01 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
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1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 11 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
1. What is expression for difference and borrow?
2. Write the truth table for half adder.
3. Write the truth table for full adder.
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4. Write the truth table for half subtrator.5. Write the truth table for full subtrator.
6. Draw the logic diagram of full subtrator.
7. What is adder?
8. List out the application of adders.
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9. Draw the full adder using two half adder circuits.10. What is combinational circuit?
11. What is different between combinational and sequential circuit?
12. What are the gates involved for binary adder?
13. List the properties of Ex-Nor gate?
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14. What is expression for sum and carry?--- Content provided by FirstRanker.com ---
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.6: MAGNITUDE COMPARATORAim:
To design, construct and study the performance of 2 bit magnitude comparator
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
--- Content provided by FirstRanker.com ---
5. Magnitude comparator IC 7485 26. EX-OR gate IC 7486 1
7. Connecting wires As required
Theory:
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The comparison of two numbers is an operator that determines one number is greater than, less
than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
three binary variables that indicate whether A>B, A=B (or) A
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Truth table:--- Content provided by FirstRanker.com ---
27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Logic Diagram:
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Pin Diagram for IC 7485:
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
8 Bit Magnitude Comparator:
Truth table:
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Procedure:
1. Connections are given as per circuit diagram.
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2. Logical inputs are given as per circuit diagram.3. Observe the output and verify the truth table.
Result:
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Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.Outcome:
At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
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comparator using logic gates.--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
A B A>B A=B A0 0 0 0
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0 0 0 00 0 0 0
0 0 0 0
0 1 0
0 0 0 1
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0 0 0 10 0 0 0
0 0 0 0
1 0 0
0 0 0 0
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0 0 0 00 0 0 1
0 0 0 1
0 0 1
Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
1. What is magnitude comparator?2. What is most significant bit?
3. Explain operation of AND gate.
4. Explain truth table of a comparator.
5. Explain magnitude comparator7485 IC.
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6. What is 8-bit input Magnitude Comparator?7. What is IC?
8. Explain the k-map simplification of A>B.
9. Explain the k-map simplification of A=B.
10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
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12. What is the truth table of 1-bit magnitude comparator?13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION
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31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Aim:To design, construct and study the performance of 4-bit different code converters
(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
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(iv) Excess-3 to BCD code converterApparatus required:
Sl.No Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
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6. EX-OR gate IC 7486 17. Connecting wires As required
Theory:
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The availability of large variety of codes for the same discrete elements of information results inthe use of different codes by different systems. A conversion circuit must be inserted between the two
systems if each uses different codes for same information. Thus, code converter is a circuit that makes the
two systems compatible even though each uses different binary code. The bit combination assigned to
binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
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and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a
circuit that makes the two systems compatible even though each uses a different binary code. To convert
from binary code to Excess-3 code, the input lines must supply the bit combination of elements as
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specified by code and the output lines generate the corresponding bit combination of code. Each one of thefour maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are
various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is
C+D has been used to implement partially each of three outputs.
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Logic diagram:
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32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(i) Binary to gray code converterLogic Diagram:
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K map for G3:G3 = B3
K map for G2:
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K map for G1:
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33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for G0:
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Truth table:
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00
0
0
0
--- Content provided by FirstRanker.com ---
00
0
1
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
0
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
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(ii) Gray to binary code converter
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34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Logic Diagram:
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K map for B3:
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B3=G3
K map for B2:
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00G3 G2 G1 G0 B3 B2 B1 B0
0
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00
0
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
0
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
0
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
--- Content provided by FirstRanker.com ---
K map for B1:K map for B0:
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Truth table:
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
(iii) BCD to excess-3 code converter
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Logic Diagram:K map for E3:
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E3 = B3 + B2 (B0 + B1)
K map for E2:
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00K map for E1:
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K map for E0:
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Truth table:
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(iv) Excess-3 to
B3 B2 B1 B0 G3 G2 G1 G0
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0
0
0
0
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
1
x
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xx
x
x
x
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0
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
1x
x
x
x
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xx
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
x
x
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xx
x
x
--- Content provided by FirstRanker.com ---
10
1
0
1
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01
0
1
0
--- Content provided by FirstRanker.com ---
xx
x
x
x
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x38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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BCD code converter
Logic Diagram:
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K map for A:
A = X1 X2 + X3 X4 X1
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K map for B:
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39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00K map for C:
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K map for D:
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Truth table:
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B3 B2 B1 B0 G3 G2 G1 G0
0
0
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00
0
1
1
--- Content provided by FirstRanker.com ---
11
1
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
1
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
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40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Procedure:
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1. Connections were given as per circuit diagram.2. Logical inputs were given as per truth table
3. Observe the logical output and verify with the truth tables.
Result:
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Thus the code converters were designed and verified using the corresponding truth table.Outcome:
At the completion of an experiment student will able to design the binary to gray converter.
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1. What is binary code?
2. What is gray code?
3. What are the advantages of gray code?
4. What is unit distance code?
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5. What is sequential code?6. How to convert binary to gray code?
7. How to convert gray to binary code?
8. What is reflective code?
9. What are the advantages of EX ? 3 code?
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10. Which code is used to arithmetic operation in digital circuits?11. Explain the operation of EX ? OR.
12. What is K ? Map?
13. Draw the truth table of EX- OR gate.
14. What is SOP?
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15. What is POS?16. What is minterm?
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Viva ? Voce
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41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.8: PARITY GENERATORS AND CHECKERSAim:
To implement the odd and even parity checkers using the logic gates and also to generate the odd parity
and even parity numbers using the generators
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Apparatus required:
Sl. No Component Type Quantity
1 Trainer Kit - 1
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2 EX-OR IC7486 13 NOT gate IC 7404 1
4 Connecting wires - Required
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Theory:Parity checking is used for error detection in data transmission.
Odd parity checkers:
It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
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odd.Even parity checker:
It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
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even.Odd parity generators:
It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also
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the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bitswhich is an odd parity number.
Even parity generator:
It generates an even parity number. The even parity checker circuit is used with the inverted output and
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also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5bits which is an even parity number.
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42 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Truth table:
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Input Checker output Generator output
A B C D D odd even odd even
0 0 0 1 1 0 00010 00011
0 0 1 0 1 0 00100 00101
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0 0 1 1 0 1 00111 001100 1 0 0 1 0 01000 01001
0 1 0 1 0 1 01011 01010
0 1 1 0 0 1 01101 01100
0 1 1 1 1 0 01110 01111
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1 0 0 0 1 0 10000 100011 0 0 1 0 1 10011 10010
1 0 1 0 0 1 10101 10100
1 0 1 1 1 0 10110 10111
1 1 0 0 0 1 11001 11000
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1 1 0 1 1 0 11010 110111 1 1 0 1 0 11100 11101
1 1 1 1 0 1 11111 11110
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Procedure:
1. The circuit is implemented using logic gates.
2. The inputs are given as per the truth table.
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3. The corresponding outputs are noted.
4. The theoretical and practical values were verified.
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Result:The odd and even parity checkers are implemented using the logic gates and the odd parity and
even parity numbers are generated using the corresponding generators.
Outcome:
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At the completion of an experiment student will able to verify the odd and even parity checkerusing logic gates.
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43 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
1. What is parity bit?
2. Why parity bit is added to message?
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3. What is parity checker?4. What is odd parity?
5. What is even parity?
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6. What are the gates involved for parity generator?7. List the procedures to convert gray code into binary.
8. Why weighted code is called as reflective codes?
9. What is a sequential code?
10. What is error deducting code?
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11. What is ASCII code?12. What is hamming code?
13. List the binary weighted code.
14. List the binary non weighted code.
15. Write the hamming code equation
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16. List the procedures to convert binary code into gray17. What are the applications of gray code?
18. What are the applications of Excess- 3 code?
Viva ? Voce
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44 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Expt.No.9: MULTIPLEXER AND DEMULTIPLEXERAim:
To design and verify the truth table of a 4X1 multiplexer & 1X4 demultiplexer
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl. No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. OR gate IC 7432 1
3. NOT gate IC 7404 1
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4. AND gate ( three input ) IC 7411 15. Connecting wires As required
Theory:
Multiplexing means transmitting a large number of information units over a smaller number of channels or
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lines. A digital multiplexer is a combinational circuit that selects binary information from one of many inputlines and directs it to a single output line. The selection of particular input line is controlled by a set of
selection lines. Normally, there are 2
n
input lines and n selection lines whose bit combinations determines
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which input is selected. A multiplexer is called a data selector, since it selects one of many inputs andsteers the binary information to the output line. A Strobe is also provided to allow the designer to disable all
output data until a specified time. Then, by allowing the STROBE to go low, the proper lead can be
selected. This feature is very useful where data might be changing the same time DATA SELECT leads
change. It is a very useful Medium Scale Integration (MSI) function and has a multitude of applications. It is
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used for connecting two or more sources to a single destination among the computer units and it is usefulfor constructing a common bus system. A decoder with an enable input can function as a demultiplexer. A
Demultiplexer is a circuit that receives information on a single line and transmits this information on one of
2
n
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possible output lines. The selection of specific output line is controlled by the bit values of n selectionlines. The decoder and demultiplexer operations are obtained from the same circuit; a decoder with an
enable input is referred to as a decoder / de-multiplexer. The Strobe lead can be used to active or de-
active the entire IC, allowing time for the address lines to change the information is fed to the output.
Demultiplexers are useful anytime information from one source must be fed several places.
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45 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4 X 1 MULTIPLEXER
CIRCUIT DIAGRAM:
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FirstRanker.com - FirstRanker's Choice
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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OFCOMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
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CS8382 DIGITAL SYSTEMS LABORATORY--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
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Section : _______________________________________--- Content provided by FirstRanker.com ---
LABORATORY MANUAL2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
training.
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? To provide competent technical manpower capable of meeting requirements of the industry
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? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at differentlevels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
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DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
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To provide candidates with knowledge and skill in the field of Electrical and Electronics
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Engineering and thereby produce extremely well trained employable, socially responsible and innovativeElectrical and Electronics Engineers.
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? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
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? To provide highest quality learning environment for the students emphasizing fundamentalconcepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
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VISIONMISSION
VISION
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MISSION
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3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM EDUCATIONAL OBJECTIVES (PEOs)1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
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engineering enabling them to solve complex problems in order to develop real time applications.2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
technologies.
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3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
development of society.
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4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
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5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
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d. Graduates will be able to design a system, component or process as per needs and specifications.e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
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h. Graduates will be able to communicate effectively by both verbal and written form.i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
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CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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SYLLABUS
Objectives:
The student should be made to:
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? Understand the various logic gates.? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
? Learn to use HDL
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List of experiments:1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
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a. 4 ? bit binary adder / subtractorb. Parity generator / checker
c. Magnitude Comparator
d. Application using multiplexers
4. Design and implementation of sequential circuits:
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a. Shift ?registersb. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
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Course Outcomes:? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
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? Design and Implement a simple digital system.--- Content provided by FirstRanker.com ---
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Content
Sl.No. Name of the Experiment Page No.
1.
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Verification of Boolean Theorems using Digital Logic Gates2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
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3.Implementation of half adder and full adder
4.
Implementation of half subtractor and full subtractor
5.
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Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates andMSI Devices
6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
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Devices7.
Design and Implementation of Magnitude Comparator.
8.
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Design and Implementation of Application using Multiplexers / Demultiplexers.9.
Design and Implementation of Shift Registers.
10.
Design and Implementation of Synchronous and Asynchronous Counters.
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11.Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
12.
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Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).--- Content provided by FirstRanker.com ---
7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.1: STUDY OF BASIC GATES
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Aim:To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. NAND gate IC 7400 16. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND gate
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The AND gate performs a logical multiplication commonly known as AND function. Theoutput is high when both the inputs are high. The output is low level when any one of the inputs is
low.
OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
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high when any one of the inputs is high. The output is low level when both the inputs are low.NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
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The NAND gate is a contraction of AND-NOT. The output is high when both inputs are lowand any one of the input is low .The output is low level when both inputs are high.
NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
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EX-OR gateAn Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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AND Gate Symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
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OR Gate:--- Content provided by FirstRanker.com ---
OR GATE:--- Content provided by FirstRanker.com ---
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00NAND Gate symbol: PIN Diagram:
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NOR Gate:--- Content provided by FirstRanker.com ---
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
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1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
th
pin is grounded and 14
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thpin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
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Result:The truth tables of all the basic logic gates were verified.
Outcome:
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At the completion of an experiment student will able to verify the truth
table of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
3. How many gates presented in IC 7408?
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4. What is IC?5. What are the applications of gates?
6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
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9. Write the truth table of NAND gate.10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
13. What are types of linear integrated circuit?
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14. What is meant by etching?15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.2:VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gates
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. NAND gate IC 7400 16. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
BASIC Boolean Laws
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1. Commutative LawThe binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A
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2. Associative Law
The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
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2. A.(B.C) = (A.B).C3. Distributive Law
The binary operator OR, AND is said to be distributive if,
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1. A+(B.C) = (A+B).(A+C)2. A.(B+C) = (A.B)+(A.C)
4. Absorption Law
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1. A+AB = A2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law1. A+A = A
2. A.A = A
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6. Complementary Law1. A+A' = 1
2. A.A' = 0
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7. De Morgan ?s Theorem1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
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2. The complement of the product is equal to the sum of the individual complements.A.B = A+B
Design
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1. Absorption LawA+AB = A
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2. Involution (or) Double complement LawA = A
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3. Idempotent Law
1. A+A = A
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2. A.A = A--- Content provided by FirstRanker.com ---
14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
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A+B = A.B5. Distributive Law
A+(B.C) = (A+B).(A+C)
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Procedure:
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
cc
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.3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
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Result:Thus the above stated Boolean laws are verified.
Outcome:
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At the completion of an experiment student will able to know the basic laws with their truth table.1. What is Demorgan?s law?
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2. What is associative law?3. What is mean by compliment gate?
4. Explain the basic laws in digital electronics
5. What is double complement?
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Viva ? Voce--- Content provided by FirstRanker.com ---
15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
To design and verify the truth table of the Half Adder & Full Adder circuits
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Apparatus required:
S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:
The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
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0 + 0 = 0
0 + 1 = 1
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1 + 0 = 11 + 1 = 0 (with 1 as carry)
The first three operations produce a sum of whose length is one digit, but when the last operation is
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performed the sum is two digits. The higher significant bit of this result is called a carry and lowersignificant bit is called the sum.
Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
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Full adder:
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
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From the truth table, the expression for sum and carry bits of the output can be obtained as,
SUM = A?B?C + A?BC? + AB?C? + ABC
CARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half Adder
Truth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
S = A B
Carry, C = A . B
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Circuit diagram:
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Full adder
Truth table:
Sl.No. Input Output
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A B C S C1. 0 0 0 0 0
2. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
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5. 1 0 0 1 06. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input Output
A B S C
1. 0 0 0 0
2. 0 1 1 0
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3. 1 0 1 04. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:
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CARRY = AB + AC + BC
Logic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
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thpin is grounded and 14
th
pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
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Result:
The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
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At the completion of an experiment student will able to design the half adder circuit and the
full adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
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Aim:
To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. EX-OR gate IC 7486 16. Connecting wires As required
Theory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
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is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than thesubtrahend bit, hence 1 is borrowed.
Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
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variables designate the minuend and the subtrahend bit, whereas the output variables produce thedifference and borrow bits.
Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
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implemented with two half subtractors and one OR gate.From the truth table the expression for difference and borrow bits of the output can be obtained
as,
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Difference, DIFF= A?B?C + A?BC? + AB?C? + ABCBorrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half subtractor
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Truth table:Sl.No. Input Output
A B Difference Borrow
1. 0 0 0 0
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2. 0 1 1 13. 1 0 1 0
4. 1 1 0 0
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From the truth table the expression for difference and borrow bits of the output can be obtained as,Difference, DIFF = A B
Borrow, BORR = A?. B
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Logic diagram:--- Content provided by FirstRanker.com ---
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2. Full subtractor
Truth table:
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Sl.No.
Input Output
A B C Difference Borrow
1. 0 0 0 0 0
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2. 0 0 1 1 13. 0 1 0 1 1
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 0
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7. 1 1 0 0 08. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
Borrow
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Borrow = A?B + A?C + BC
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Circuit diagram:--- Content provided by FirstRanker.com ---
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
Aim:
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To design and implement 4-bit adder and subtractor using IC 7483Apparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. IC IC 7483 1
3. NOT gate IC 7404 1
4. EX-OR gate IC 7486 1
5. Connecting wires As required
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Theory:
4 BIT Binary adder:
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A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can beconstructed with full adders connected in cascade, with the output carry from each full adder connected to
the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
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0and it ripples through
the full adder to the output carry C
4
.
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4 BIT Binary subtractor:The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
?B? and the corresponding input of full adder. The input carry C
0
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must be equal to 1 when performingsubtraction.
4 BIT Binary adder / subtractor:
The addition and subtraction operation can be combined into one circuit with one common binary
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adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, itbecomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PIN Diagram for IC 7483:
Logic Diagram: 4-Bit Binary Diagram:
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Logic diagram: 4-Bit Binary Subtractor:
4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:
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Procedure:
1. Connections are given as per the circuit diagrams.
2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
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.Result:
The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
verified.
Outcome:
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At the completion of an experiment student will able to design 4-bit binary adder and subtractorInput Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
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1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 00 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
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1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 125 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?
2. Write the truth table for half adder.
3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
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5. Write the truth table for full subtrator.6. Draw the logic diagram of full subtrator.
7. What is adder?
8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
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10. What is combinational circuit?11. What is different between combinational and sequential circuit?
12. What are the gates involved for binary adder?
13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.6: MAGNITUDE COMPARATOR
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Aim:
To design, construct and study the performance of 2 bit magnitude comparator
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
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6. EX-OR gate IC 7486 17. Connecting wires As required
Theory:
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The comparison of two numbers is an operator that determines one number is greater than, lessthan (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
three binary variables that indicate whether A>B, A=B (or) A
Truth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Logic Diagram:
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Pin Diagram for IC 7485:
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Logic Diagram:29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:Truth table:
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Procedure:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
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3. Observe the output and verify the truth table.Result:
Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
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Outcome:
At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
comparator using logic gates.
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A B A>B A=B A0 0 0 0
0 0 0 0
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0 0 0 00 0 0 0
0 1 0
0 0 0 1
0 0 0 1
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0 0 0 00 0 0 0
1 0 0
0 0 0 0
0 0 0 0
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0 0 0 10 0 0 1
0 0 1
Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
1. What is magnitude comparator?
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2. What is most significant bit?3. Explain operation of AND gate.
4. Explain truth table of a comparator.
5. Explain magnitude comparator7485 IC.
6. What is 8-bit input Magnitude Comparator?
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7. What is IC?8. Explain the k-map simplification of A>B.
9. Explain the k-map simplification of A=B.
10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
12. What is the truth table of 1-bit magnitude comparator?
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13. What is the use of magnitude comparator?--- Content provided by FirstRanker.com ---
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Expt.No.7: CODE CONVERSION
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31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Aim:
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To design, construct and study the performance of 4-bit different code converters(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
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7. Connecting wires As requiredTheory:
The availability of large variety of codes for the same discrete elements of information results in
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the use of different codes by different systems. A conversion circuit must be inserted between the twosystems if each uses different codes for same information. Thus, code converter is a circuit that makes the
two systems compatible even though each uses different binary code. The bit combination assigned to
binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
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and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit isdesigned. The Boolean functions are obtained from K-Map for each output variable. A code converter is a
circuit that makes the two systems compatible even though each uses a different binary code. To convert
from binary code to Excess-3 code, the input lines must supply the bit combination of elements as
specified by code and the output lines generate the corresponding bit combination of code. Each one of the
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four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are
various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is
C+D has been used to implement partially each of three outputs.
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Logic diagram:
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32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
(i) Binary to gray code converter
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Logic Diagram:
K map for G3:
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G3 = B3
K map for G2:
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K map for G1:
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33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for G0:
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Truth table:
0
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00
0
0
0
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00
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
0
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
0
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
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(ii) Gray to binary code converter34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:
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K map for B3:
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B3=G3K map for B2:
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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G3 G2 G1 G0 B3 B2 B1 B0
0
0
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00
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
00
0
1
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11
1
0
0
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00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
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11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
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0
0
0
0
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00
0
0
1
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11
1
1
1
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11
0
0
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00
1
1
1
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10
0
0
0
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11
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
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01
1
0
0
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11
0
0
1
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10
1
0
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10
1
0
1
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01
0
1
0
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10
1
K map for B1:
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K map for B0:
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Truth table:
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00(iii) BCD to excess-3 code converter
Logic Diagram:
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K map for E3:
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E3 = B3 + B2 (B0 + B1)K map for E2:
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for E1:
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K map for E0:
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Truth table:
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(iv) Excess-3 to
B3 B2 B1 B0 G3 G2 G1 G0
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00
0
0
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
0
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
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10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
1
x
x
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xx
x
x
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
xx
x
x
x
--- Content provided by FirstRanker.com ---
x1
0
0
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11
0
0
1
--- Content provided by FirstRanker.com ---
10
x
x
x
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xx
x
1
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01
0
1
0
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10
1
0
x
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xx
x
x
x
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38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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BCD code converterLogic Diagram:
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K map for A:A = X1 X2 + X3 X4 X1
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K map for B:--- Content provided by FirstRanker.com ---
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39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for C:
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K map for D:
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Truth table:
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B3 B2 B1 B0 G3 G2 G1 G00
0
0
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00
1
1
1
--- Content provided by FirstRanker.com ---
11
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
0
0
0
0
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
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40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections were given as per circuit diagram.
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2. Logical inputs were given as per truth table3. Observe the logical output and verify with the truth tables.
Result:
Thus the code converters were designed and verified using the corresponding truth table.
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Outcome:
At the completion of an experiment student will able to design the binary to gray converter.
--- Content provided by FirstRanker.com ---
1. What is binary code?2. What is gray code?
3. What are the advantages of gray code?
4. What is unit distance code?
5. What is sequential code?
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6. How to convert binary to gray code?7. How to convert gray to binary code?
8. What is reflective code?
9. What are the advantages of EX ? 3 code?
10. Which code is used to arithmetic operation in digital circuits?
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11. Explain the operation of EX ? OR.12. What is K ? Map?
13. Draw the truth table of EX- OR gate.
14. What is SOP?
15. What is POS?
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16. What is minterm?--- Content provided by FirstRanker.com ---
Viva ? Voce
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41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.8: PARITY GENERATORS AND CHECKERS
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Aim:
To implement the odd and even parity checkers using the logic gates and also to generate the odd parity
and even parity numbers using the generators
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Apparatus required:Sl. No Component Type Quantity
1 Trainer Kit - 1
2 EX-OR IC7486 1
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3 NOT gate IC 7404 14 Connecting wires - Required
Theory:
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Parity checking is used for error detection in data transmission.Odd parity checkers:
It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
odd.
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Even parity checker:
It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
even.
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Odd parity generators:
It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also
the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bits
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which is an odd parity number.Even parity generator:
It generates an even parity number. The even parity checker circuit is used with the inverted output and
also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5
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bits which is an even parity number.--- Content provided by FirstRanker.com ---
42 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Truth table:
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Input Checker output Generator outputA B C D D odd even odd even
0 0 0 1 1 0 00010 00011
0 0 1 0 1 0 00100 00101
0 0 1 1 0 1 00111 00110
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0 1 0 0 1 0 01000 010010 1 0 1 0 1 01011 01010
0 1 1 0 0 1 01101 01100
0 1 1 1 1 0 01110 01111
1 0 0 0 1 0 10000 10001
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1 0 0 1 0 1 10011 100101 0 1 0 0 1 10101 10100
1 0 1 1 1 0 10110 10111
1 1 0 0 0 1 11001 11000
1 1 0 1 1 0 11010 11011
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1 1 1 0 1 0 11100 111011 1 1 1 0 1 11111 11110
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Procedure:1. The circuit is implemented using logic gates.
2. The inputs are given as per the truth table.
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3. The corresponding outputs are noted.4. The theoretical and practical values were verified.
Result:
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The odd and even parity checkers are implemented using the logic gates and the odd parity andeven parity numbers are generated using the corresponding generators.
Outcome:
At the completion of an experiment student will able to verify the odd and even parity checker
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using logic gates.--- Content provided by FirstRanker.com ---
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43 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
1. What is parity bit?2. Why parity bit is added to message?
3. What is parity checker?
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4. What is odd parity?
5. What is even parity?
6. What are the gates involved for parity generator?
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7. List the procedures to convert gray code into binary.8. Why weighted code is called as reflective codes?
9. What is a sequential code?
10. What is error deducting code?
11. What is ASCII code?
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12. What is hamming code?13. List the binary weighted code.
14. List the binary non weighted code.
15. Write the hamming code equation
16. List the procedures to convert binary code into gray
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17. What are the applications of gray code?18. What are the applications of Excess- 3 code?
Viva ? Voce
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44 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.9: MULTIPLEXER AND DEMULTIPLEXER
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Aim:
To design and verify the truth table of a 4X1 multiplexer & 1X4 demultiplexer
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl. No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. OR gate IC 7432 1
3. NOT gate IC 7404 1
4. AND gate ( three input ) IC 7411 1
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5. Connecting wires As requiredTheory:
Multiplexing means transmitting a large number of information units over a smaller number of channels or
lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input
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lines and directs it to a single output line. The selection of particular input line is controlled by a set ofselection lines. Normally, there are 2
n
input lines and n selection lines whose bit combinations determines
which input is selected. A multiplexer is called a data selector, since it selects one of many inputs and
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steers the binary information to the output line. A Strobe is also provided to allow the designer to disable alloutput data until a specified time. Then, by allowing the STROBE to go low, the proper lead can be
selected. This feature is very useful where data might be changing the same time DATA SELECT leads
change. It is a very useful Medium Scale Integration (MSI) function and has a multitude of applications. It is
used for connecting two or more sources to a single destination among the computer units and it is useful
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for constructing a common bus system. A decoder with an enable input can function as a demultiplexer. ADemultiplexer is a circuit that receives information on a single line and transmits this information on one of
2
n
possible output lines. The selection of specific output line is controlled by the bit values of n selection
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lines. The decoder and demultiplexer operations are obtained from the same circuit; a decoder with anenable input is referred to as a decoder / de-multiplexer. The Strobe lead can be used to active or de-
active the entire IC, allowing time for the address lines to change the information is fed to the output.
Demultiplexers are useful anytime information from one source must be fed several places.
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45 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4 X 1 MULTIPLEXERCIRCUIT DIAGRAM:
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46 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1X4 DEMULTIPLEXER
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CIRCUIT DIAGRAM:
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FirstRanker.com - FirstRanker's Choice
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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
?DEPARTMENT OF
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COMPUTER SCIENCE ENGINEERINGIII SEMESTER - R 2017
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
Section : _______________________________________
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LABORATORY MANUAL
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2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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training.
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? To provide competent technical manpower capable of meeting requirements of the industry
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
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heart and soul
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DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
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To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
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? To provide the students rigorous learning experience to produce creative solutions to society?sneeds.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
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concepts with strongly supported laboratory and prepare them to meet the global needs of theindustry by continuous assessment and training.
VISION
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MISSION
VISION
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MISSION--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
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1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
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2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
technologies.
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3. BreadthTo provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
development of society.
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4. ProfessionalismTo inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
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5. Lifelong Learning/EthicsTo practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
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e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
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i. Graduates will show the understanding of impact of engineering solutions on the society and alsowill be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
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CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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SYLLABUSObjectives:
The student should be made to:
? Understand the various logic gates.
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? Be familiar with various combinational circuits.? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
? Learn to use HDL
List of experiments:
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1. Verification of Boolean Theorems using basic gates.2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
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b. Parity generator / checkerc. Magnitude Comparator
d. Application using multiplexers
4. Design and implementation of sequential circuits:
a. Shift ?registers
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b. Synchronous and asynchronous counters5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
Course Outcomes:
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? Use Boolean simplification techniques to design a combinational hardware circuit.? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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ContentSl.No. Name of the Experiment Page No.
1.
Verification of Boolean Theorems using Digital Logic Gates
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2.Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
3.
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Implementation of half adder and full adder4.
Implementation of half subtractor and full subtractor
5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
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MSI Devices6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
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7.
Design and Implementation of Magnitude Comparator.
8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
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9.Design and Implementation of Shift Registers.
10.
Design and Implementation of Synchronous and Asynchronous Counters.
11.
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Simulation of Combinational Circuits using Hardware Description Language (VHDL / VerilogHDL Software Required).
12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.1: STUDY OF BASIC GATES
Aim:
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To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gatesApparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
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6. NOR gate IC 7402 17. EX-OR gate IC 7486 1
8. Connecting wires As required
Theory:
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Circuit that takes the logical decision and the process are called logic gates. Each gate has one ormore input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
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output is high when both the inputs are high. The output is low level when any one of the inputs islow.
OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
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NOT gateA NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
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and any one of the input is low .The output is low level when both inputs are high.NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
EX-OR gate
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An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It issimilar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
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1. Connections are given as per the circuit diagram.2. For all the IC?s 7
th
pin is grounded and 14
th
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pin is given +5 supply.3. Apply the inputs and verify the truth table for all gates.
Result:
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The truth tables of all the basic logic gates were verified.
Outcome:
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At the completion of an experiment student will able to verify the truthtable of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
3. How many gates presented in IC 7408?
4. What is IC?
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5. What are the applications of gates?6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
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10. Write the truth table of NOR gate.11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
13. What are types of linear integrated circuit?
14. What is meant by etching?
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15. What are the advantages of IC?16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.2:
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VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gatesApparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
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6. NOR gate IC 7402 37. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:BASIC Boolean Laws
1. Commutative Law
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The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A
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2. Associative LawThe binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
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3. Distributive Law
The binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
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2. A.(B+C) = (A.B)+(A.C)4. Absorption Law
1. A+AB = A
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2. A+AB =A+B--- Content provided by FirstRanker.com ---
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:005. Idempotent Law
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1. A+A = A
2. A.A = A
6. Complementary Law
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1. A+A' = 1
2. A.A' = 0
7. De Morgan ?s Theorem
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1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
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A.B = A+BDesign
1. Absorption Law
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A+AB = A
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2. Involution (or) Double complement Law
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A = A
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3. Idempotent Law1. A+A = A
2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
A+B = A.B
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5. Distributive Law
A+(B.C) = (A+B).(A+C)
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Procedure:1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
cc
.
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3. Apply the inputs to the respective input pins.4. Verify the output with the truth table.
Result:
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Thus the above stated Boolean laws are verified.
Outcome:
At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?
2. What is associative law?
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3. What is mean by compliment gate?4. Explain the basic laws in digital electronics
5. What is double complement?
Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
To design and verify the truth table of the Half Adder & Full Adder circuits
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Apparatus required:S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:
The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
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0 + 0 = 00 + 1 = 1
1 + 0 = 1
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1 + 1 = 0 (with 1 as carry)
The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
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significant bit is called the sum.Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
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Full adder:A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
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From the truth table, the expression for sum and carry bits of the output can be obtained as,SUM = A?B?C + A?BC? + AB?C? + ABC
CARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half AdderTruth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,S = A B
Carry, C = A . B
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Circuit diagram:
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Full adderTruth table:
Sl.No. Input Output
A B C S C
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1. 0 0 0 0 02. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
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6. 1 0 1 0 17. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input OutputA B S C
1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
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4. 1 1 1 117 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:
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CARRY = AB + AC + BCLogic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
th
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pin is grounded and 14th
pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
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Result:The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
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At the completion of an experiment student will able to design the half adder circuit and thefull adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
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Aim:To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
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6. Connecting wires As requiredTheory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
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subtrahend bit, hence 1 is borrowed.Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
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difference and borrow bits.Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
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From the truth table the expression for difference and borrow bits of the output can be obtained
as,
Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
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Borrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Half subtractor
Truth table:
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Sl.No. Input Output
A B Difference Borrow
1. 0 0 0 0
2. 0 1 1 1
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3. 1 0 1 04. 1 1 0 0
From the truth table the expression for difference and borrow bits of the output can be obtained as,
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Difference, DIFF = A BBorrow, BORR = A?. B
Logic diagram:
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2. Full subtractor
Truth table:
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Sl.No.Input Output
A B C Difference Borrow
1. 0 0 0 0 0
2. 0 0 1 1 1
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3. 0 1 0 1 14. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
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8. 1 1 1 1 1--- Content provided by FirstRanker.com ---
21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Difference--- Content provided by FirstRanker.com ---
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Difference = A?B?C + A?BC? + AB?C? + ABCBorrow
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Borrow = A?B + A?C + BC
Circuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.5: 4-BIT ADDER AND SUBTRACTORAim:
To design and implement 4-bit adder and subtractor using IC 7483
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. IC IC 7483 13. NOT gate IC 7404 1
4. EX-OR gate IC 7486 1
5. Connecting wires As required
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Theory:4 BIT Binary adder:
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
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constructed with full adders connected in cascade, with the output carry from each full adder connected tothe input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
0
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and it ripples throughthe full adder to the output carry C
4
.
4 BIT Binary subtractor:
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The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
?B? and the corresponding input of full adder. The input carry C
0
must be equal to 1 when performing
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subtraction.4 BIT Binary adder / subtractor:
The addition and subtraction operation can be combined into one circuit with one common binary
adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
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becomes subtractor.23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PIN Diagram for IC 7483:
Logic Diagram: 4-Bit Binary Diagram:
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Logic diagram: 4-Bit Binary Subtractor:4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:--- Content provided by FirstRanker.com ---
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Procedure:1. Connections are given as per the circuit diagrams.
2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
.
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Result:The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
verified.
Outcome:
At the completion of an experiment student will able to design 4-bit binary adder and subtractor
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Input Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
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0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 00 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?2. Write the truth table for half adder.
3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
5. Write the truth table for full subtrator.
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6. Draw the logic diagram of full subtrator.7. What is adder?
8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
10. What is combinational circuit?
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11. What is different between combinational and sequential circuit?12. What are the gates involved for binary adder?
13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.6: MAGNITUDE COMPARATOR
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Aim:To design, construct and study the performance of 2 bit magnitude comparator
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
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7. Connecting wires As requiredTheory:
The comparison of two numbers is an operator that determines one number is greater than, less
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than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares twonumbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
three binary variables that indicate whether A>B, A=B (or) A
Truth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Logic Diagram:
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Pin Diagram for IC 7485:
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:
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Truth table:
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Procedure:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
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Result:
Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
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Outcome:At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
comparator using logic gates.
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A B A>B A=B A0 0 0 0
0 0 0 0
0 0 0 0
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0 0 0 00 1 0
0 0 0 1
0 0 0 1
0 0 0 0
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0 0 0 01 0 0
0 0 0 0
0 0 0 0
0 0 0 1
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0 0 0 10 0 1
Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
1. What is magnitude comparator?
2. What is most significant bit?
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3. Explain operation of AND gate.4. Explain truth table of a comparator.
5. Explain magnitude comparator7485 IC.
6. What is 8-bit input Magnitude Comparator?
7. What is IC?
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8. Explain the k-map simplification of A>B.9. Explain the k-map simplification of A=B.
10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
12. What is the truth table of 1-bit magnitude comparator?
13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION
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31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Aim:
To design, construct and study the performance of 4-bit different code converters
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(i) Binary to gray code converter(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:
The availability of large variety of codes for the same discrete elements of information results in
the use of different codes by different systems. A conversion circuit must be inserted between the two
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systems if each uses different codes for same information. Thus, code converter is a circuit that makes thetwo systems compatible even though each uses different binary code. The bit combination assigned to
binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
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designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is acircuit that makes the two systems compatible even though each uses a different binary code. To convert
from binary code to Excess-3 code, the input lines must supply the bit combination of elements as
specified by code and the output lines generate the corresponding bit combination of code. Each one of the
four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
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level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These arevarious other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is
C+D has been used to implement partially each of three outputs.
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Logic diagram:
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32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00(i) Binary to gray code converter
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Logic Diagram:K map for G3:
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G3 = B3
K map for G2:
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K map for G1:
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33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
K map for G0:
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Truth table:0
0
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00
0
0
0
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01
1
1
1
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11
1
1
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00
0
0
1
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11
1
0
0
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00
1
1
1
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10
0
1
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10
0
1
1
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00
1
1
0
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01
1
0
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10
1
0
1
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01
0
1
0
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10
1
0
1
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0
0
0
0
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00
0
0
1
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11
1
1
1
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11
0
0
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00
1
1
1
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11
1
1
1
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00
0
0
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00
1
1
1
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10
0
0
0
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11
1
1
0
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00
1
1
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00
1
1
0
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01
1
0
0
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11
0
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(ii) Gray to binary code converter
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34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:
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K map for B3:B3=G3
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K map for B2:--- Content provided by FirstRanker.com ---
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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G3 G2 G1 G0 B3 B2 B1 B00
0
0
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00
0
0
0
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11
1
1
1
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11
1
0
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00
0
1
1
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11
1
1
1
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10
0
0
0
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0
0
1
1
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11
0
0
0
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01
1
1
1
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00
0
1
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10
0
1
1
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00
1
1
0
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01
1
0
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00
0
0
0
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00
0
1
1
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11
1
1
1
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10
0
0
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01
1
1
1
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00
0
0
1
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11
1
0
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01
1
0
0
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11
0
0
1
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10
0
1
1
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0
1
0
1
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01
0
1
0
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10
1
0
1
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01
K map for B1:
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K map for B0:
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Truth table:--- Content provided by FirstRanker.com ---
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(iii) BCD to excess-3 code converter
Logic Diagram:
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K map for E3:
E3 = B3 + B2 (B0 + B1)
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K map for E2:
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for E1:
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K map for E0:
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Truth table:
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(iv) Excess-3 to
B3 B2 B1 B0 G3 G2 G1 G0
0
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00
0
0
0
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00
1
1
1
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11
1
1
1
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0
0
0
0
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11
1
1
0
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00
0
1
1
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11
0
0
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11
0
0
1
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10
0
1
1
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00
1
1
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01
0
1
0
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10
1
0
1
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01
0
1
0
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10
0
0
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00
1
1
1
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11
x
x
x
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xx
x
0
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11
1
1
0
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00
0
1
x
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xx
x
x
x
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1
0
0
1
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10
0
1
1
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0x
x
x
x
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xx
1
0
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10
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01
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x
x
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xx
x
x
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38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
BCD code converter
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Logic Diagram:
K map for A:
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A = X1 X2 + X3 X4 X1
K map for B:
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39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for C:
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K map for D:
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Truth table:
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B3 B2 B1 B0 G3 G2 G1 G0
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0
0
0
0
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01
1
1
1
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10
1
1
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11
0
0
0
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01
1
0
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01
1
0
0
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11
0
1
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01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
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00
0
0
0
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00
0
1
1
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0
0
0
0
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11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
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10
1
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40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections were given as per circuit diagram.
2. Logical inputs were given as per truth table
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3. Observe the logical output and verify with the truth tables.Result:
Thus the code converters were designed and verified using the corresponding truth table.
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Outcome:At the completion of an experiment student will able to design the binary to gray converter.
1. What is binary code?
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2. What is gray code?3. What are the advantages of gray code?
4. What is unit distance code?
5. What is sequential code?
6. How to convert binary to gray code?
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7. How to convert gray to binary code?8. What is reflective code?
9. What are the advantages of EX ? 3 code?
10. Which code is used to arithmetic operation in digital circuits?
11. Explain the operation of EX ? OR.
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12. What is K ? Map?13. Draw the truth table of EX- OR gate.
14. What is SOP?
15. What is POS?
16. What is minterm?
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Viva ? Voce
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41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.8: PARITY GENERATORS AND CHECKERS
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Aim:To implement the odd and even parity checkers using the logic gates and also to generate the odd parity
and even parity numbers using the generators
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl. No Component Type Quantity
1 Trainer Kit - 1
2 EX-OR IC7486 1
3 NOT gate IC 7404 1
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4 Connecting wires - RequiredTheory:
Parity checking is used for error detection in data transmission.
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Odd parity checkers:It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
odd.
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Even parity checker:It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
even.
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Odd parity generators:It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also
the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bits
which is an odd parity number.
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Even parity generator:It generates an even parity number. The even parity checker circuit is used with the inverted output and
also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5
bits which is an even parity number.
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42 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Truth table:
Input Checker output Generator output
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A B C D D odd even odd even0 0 0 1 1 0 00010 00011
0 0 1 0 1 0 00100 00101
0 0 1 1 0 1 00111 00110
0 1 0 0 1 0 01000 01001
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0 1 0 1 0 1 01011 010100 1 1 0 0 1 01101 01100
0 1 1 1 1 0 01110 01111
1 0 0 0 1 0 10000 10001
1 0 0 1 0 1 10011 10010
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1 0 1 0 0 1 10101 101001 0 1 1 1 0 10110 10111
1 1 0 0 0 1 11001 11000
1 1 0 1 1 0 11010 11011
1 1 1 0 1 0 11100 11101
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1 1 1 1 0 1 11111 11110Procedure:
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1. The circuit is implemented using logic gates.2. The inputs are given as per the truth table.
3. The corresponding outputs are noted.
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4. The theoretical and practical values were verified.
Result:
The odd and even parity checkers are implemented using the logic gates and the odd parity and
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even parity numbers are generated using the corresponding generators.Outcome:
At the completion of an experiment student will able to verify the odd and even parity checker
using logic gates.
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--- Content provided by FirstRanker.com ---
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43 Format No.FirstRanker/stud/LM/34/issue:00/revision:001. What is parity bit?
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2. Why parity bit is added to message?
3. What is parity checker?
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4. What is odd parity?5. What is even parity?
6. What are the gates involved for parity generator?
7. List the procedures to convert gray code into binary.
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8. Why weighted code is called as reflective codes?9. What is a sequential code?
10. What is error deducting code?
11. What is ASCII code?
12. What is hamming code?
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13. List the binary weighted code.14. List the binary non weighted code.
15. Write the hamming code equation
16. List the procedures to convert binary code into gray
17. What are the applications of gray code?
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18. What are the applications of Excess- 3 code?Viva ? Voce
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44 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.9: MULTIPLEXER AND DEMULTIPLEXER
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Aim:To design and verify the truth table of a 4X1 multiplexer & 1X4 demultiplexer
Apparatus required:
Sl. No Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. OR gate IC 7432 1
3. NOT gate IC 7404 1
4. AND gate ( three input ) IC 7411 1
5. Connecting wires As required
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Theory:
Multiplexing means transmitting a large number of information units over a smaller number of channels or
lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input
lines and directs it to a single output line. The selection of particular input line is controlled by a set of
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selection lines. Normally, there are 2n
input lines and n selection lines whose bit combinations determines
which input is selected. A multiplexer is called a data selector, since it selects one of many inputs and
steers the binary information to the output line. A Strobe is also provided to allow the designer to disable all
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output data until a specified time. Then, by allowing the STROBE to go low, the proper lead can beselected. This feature is very useful where data might be changing the same time DATA SELECT leads
change. It is a very useful Medium Scale Integration (MSI) function and has a multitude of applications. It is
used for connecting two or more sources to a single destination among the computer units and it is useful
for constructing a common bus system. A decoder with an enable input can function as a demultiplexer. A
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Demultiplexer is a circuit that receives information on a single line and transmits this information on one of2
n
possible output lines. The selection of specific output line is controlled by the bit values of n selection
lines. The decoder and demultiplexer operations are obtained from the same circuit; a decoder with an
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enable input is referred to as a decoder / de-multiplexer. The Strobe lead can be used to active or de-active the entire IC, allowing time for the address lines to change the information is fed to the output.
Demultiplexers are useful anytime information from one source must be fed several places.
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45 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
4 X 1 MULTIPLEXER
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CIRCUIT DIAGRAM:
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46 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1X4 DEMULTIPLEXER--- Content provided by FirstRanker.com ---
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CIRCUIT DIAGRAM:--- Content provided by FirstRanker.com ---
47 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Result:
The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth tables
were verified.
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Outcome:At the completion of an experiment student will able to design the multiplexer and the
demultiplexer
--- Content provided by FirstRanker.com ---
1. What is multiplexer?
2. What is demultiplexer?
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3. What are the advantages of multiplexer?4. What are the advantages of demultiplexer?
5. What is select signal?
6. How to choose select signal in multiplexer?
7. How to choose select signal in demultiplexer?
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8. Write the formula used in select signal.9. What is the difference between the multiplexer and demultiplexer?
10. What is the application of multiplexer?
11. What is the application of demultiplexer?
12. Draw the truth table of multiplexer.
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13. Draw the truth table of demultiplexer.14. How many select signals are needed in 8*1 multiplexer?
15. How many select signals are needed in 8*1 demultiplexer?
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Viva ? Voce
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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
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CS8382 DIGITAL SYSTEMS LABORATORY
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Name : _______________________________________
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Register No : _______________________________________Section : _______________________________________
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LABORATORY MANUAL
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2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
training.
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? To provide competent technical manpower capable of meeting requirements of the industry
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? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
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heart and soulDEPARTMENT OF COMPUTER SCIENCE ENGINEERING
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To provide candidates with knowledge and skill in the field of Electrical and ElectronicsEngineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
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? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
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professional ethical code.? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
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VISION
MISSION
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VISIONMISSION
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3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
1. Fundamentals
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To provide students with a solid foundation in mathematics, science and fundamentals ofengineering enabling them to solve complex problems in order to develop real time applications.
2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
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technologies.3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
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development of society.4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
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professional ethics at all strategies.5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM OUTCOMES (POs)a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
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c. Graduates will be able to design and conduct experiments, analyze and interpret data.d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
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g. Graduates will demonstrate knowledge of professional and ethical responsibilities.h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
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k. Graduate who can participate and succeed in competitive examinations.--- Content provided by FirstRanker.com ---
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CS8381 DIGITAL SYSTEMS LABORATORY5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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SYLLABUS
Objectives:
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The student should be made to:? Understand the various logic gates.
? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
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? Learn to use HDLList of experiments:
1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
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3. Design and implementation of combinational circuits using MSI devices:a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
c. Magnitude Comparator
d. Application using multiplexers
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4. Design and implementation of sequential circuits:a. Shift ?registers
b. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
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Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
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? Design the different functional units in a digital computer system.? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Content
Sl.No. Name of the Experiment Page No.
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1.Verification of Boolean Theorems using Digital Logic Gates
2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
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3.
Implementation of half adder and full adder
4.
Implementation of half subtractor and full subtractor
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5.Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
6.
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Design and Implementation of Parity Generator / Checker using Basic Gates and MSIDevices
7.
Design and Implementation of Magnitude Comparator.
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8.Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
Design and Implementation of Shift Registers.
10.
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Design and Implementation of Synchronous and Asynchronous Counters.11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
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12.Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.1: STUDY OF BASIC GATES
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Aim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. NAND gate IC 7400 1
6. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
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AND gateThe AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
low.
OR gate
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The OR gate performs a logical addition commonly known as OR function. The output ishigh when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
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NAND gateThe NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
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output is low when one or both inputs are high.EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
EXOR Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
th
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pin is grounded and 14th
pin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
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Result:
The truth tables of all the basic logic gates were verified.
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Outcome:At the completion of an experiment student will able to verify the truth
table of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
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3. How many gates presented in IC 7408?4. What is IC?
5. What are the applications of gates?
6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
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8. Write the truth table of NOT gate.9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
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13. What are types of linear integrated circuit?14. What is meant by etching?
15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.2:
VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gates
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. NAND gate IC 7400 1
6. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
BASIC Boolean Laws
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1. Commutative Law
The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
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2. A.B=B.A2. Associative Law
The binary operator OR, AND is said to be associative if,
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1. A+(B+C) = (A+B)+C2. A.(B.C) = (A.B).C
3. Distributive Law
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The binary operator OR, AND is said to be distributive if,1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
4. Absorption Law
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1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
1. A+A = A
2. A.A = A
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6. Complementary Law
1. A+A' = 1
2. A.A' = 0
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7. De Morgan ?s Theorem
1. The complement of the sum is equal to the sum of the product of the individual
complements.
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A+B = A.B2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design1. Absorption Law
A+AB = A
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2. Involution (or) Double complement Law
A = A
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3. Idempotent Law
1. A+A = A
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2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:004. Demorgan ?s Law
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A+B = A.B
5. Distributive Law
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A+(B.C) = (A+B).(A+C)Procedure:
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
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cc.
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
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Result:
Thus the above stated Boolean laws are verified.
Outcome:
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At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?2. What is associative law?
3. What is mean by compliment gate?
4. Explain the basic laws in digital electronics
5. What is double complement?
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Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
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To design and verify the truth table of the Half Adder & Full Adder circuitsApparatus required:
S. No. Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
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6. Connecting wires As requiredTheory:
The most basic arithmetic operation is the addition of two binary digits. There are four
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possible elementary operations, namely,0 + 0 = 0
0 + 1 = 1
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1 + 0 = 1
1 + 1 = 0 (with 1 as carry)
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The first three operations produce a sum of whose length is one digit, but when the last operation isperformed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
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designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.Full adder:
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
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with two half adders and one OR gate.From the truth table, the expression for sum and carry bits of the output can be obtained as,
SUM = A?B?C + A?BC? + AB?C? + ABC
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CARRY = A?BC + AB?C + ABC? +ABC16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half Adder
Truth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
S = A B
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Carry, C = A . BCircuit diagram:
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Full adder
Truth table:
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Sl.No. Input OutputA B C S C
1. 0 0 0 0 0
2. 0 0 1 1 0
3. 0 1 0 1 0
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4. 0 1 1 0 15. 1 0 0 1 0
6. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input Output
A B S C
1. 0 0 0 0
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2. 0 1 1 03. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Sum:--- Content provided by FirstRanker.com ---
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B CCarry:
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CARRY = AB + AC + BC
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Logic Diagram:18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections are given as per the circuit diagrams.
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2. For all the IC?s 7th
pin is grounded and 14
th
pin is given +5 V supply.
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3. Apply the inputs and verify the truth table for the half adder and full adder circuits.Result:
The design of the half adder and full adder circuits was done and their truth tables were verified.
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Outcome:At the completion of an experiment student will able to design the half adder circuit and the
full adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTORAim:
To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. EX-OR gate IC 7486 1
6. Connecting wires As required
Theory:
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The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bitis subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
subtrahend bit, hence 1 is borrowed.
Half subtractor:
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A combinational circuit which performs the subtraction of two bits is called half subtractor. The inputvariables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
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three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can beimplemented with two half subtractors and one OR gate.
From the truth table the expression for difference and borrow bits of the output can be obtained
as,
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Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
Borrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half subtractor
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Truth table:
Sl.No. Input Output
A B Difference Borrow
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1. 0 0 0 02. 0 1 1 1
3. 1 0 1 0
4. 1 1 0 0
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From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A B
Borrow, BORR = A?. B
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Logic diagram:
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2. Full subtractor
Truth table:
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Sl.No.
Input Output
A B C Difference Borrow
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1. 0 0 0 0 02. 0 0 1 1 1
3. 0 1 0 1 1
4. 0 1 1 0 1
5. 1 0 0 1 0
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6. 1 0 1 0 07. 1 1 0 0 0
8. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
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Borrow--- Content provided by FirstRanker.com ---
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Borrow = A?B + A?C + BC
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Circuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
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Aim:To design and implement 4-bit adder and subtractor using IC 7483
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. IC IC 7483 1
3. NOT gate IC 7404 1
4. EX-OR gate IC 7486 1
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5. Connecting wires As requiredTheory:
4 BIT Binary adder:
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A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected to
the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
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carries are connected in chain through full adder. The input carry to the adder is C0
and it ripples through
the full adder to the output carry C
4
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.4 BIT Binary subtractor:
The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
?B? and the corresponding input of full adder. The input carry C
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0must be equal to 1 when performing
subtraction.
4 BIT Binary adder / subtractor:
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The addition and subtraction operation can be combined into one circuit with one common binaryadder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
becomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PIN Diagram for IC 7483:
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Logic Diagram: 4-Bit Binary Diagram:Logic diagram: 4-Bit Binary Subtractor:
4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:
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Procedure:
1. Connections are given as per the circuit diagrams.
2. Logical inputs were given as per circuit diagram.
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3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor..
Result:
The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
verified.
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Outcome:At the completion of an experiment student will able to design 4-bit binary adder and subtractor
Input Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
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1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 01 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
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1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 11 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
1. What is expression for difference and borrow?
2. Write the truth table for half adder.
3. Write the truth table for full adder.
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4. Write the truth table for half subtrator.5. Write the truth table for full subtrator.
6. Draw the logic diagram of full subtrator.
7. What is adder?
8. List out the application of adders.
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9. Draw the full adder using two half adder circuits.10. What is combinational circuit?
11. What is different between combinational and sequential circuit?
12. What are the gates involved for binary adder?
13. List the properties of Ex-Nor gate?
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14. What is expression for sum and carry?--- Content provided by FirstRanker.com ---
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.6: MAGNITUDE COMPARATORAim:
To design, construct and study the performance of 2 bit magnitude comparator
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
--- Content provided by FirstRanker.com ---
5. Magnitude comparator IC 7485 26. EX-OR gate IC 7486 1
7. Connecting wires As required
Theory:
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The comparison of two numbers is an operator that determines one number is greater than, less
than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
three binary variables that indicate whether A>B, A=B (or) A
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Truth table:--- Content provided by FirstRanker.com ---
27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Logic Diagram:
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Pin Diagram for IC 7485:
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--- Content provided by FirstRanker.com ---
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
8 Bit Magnitude Comparator:
Truth table:
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Procedure:
1. Connections are given as per circuit diagram.
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2. Logical inputs are given as per circuit diagram.3. Observe the output and verify the truth table.
Result:
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Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.Outcome:
At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
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comparator using logic gates.--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
A B A>B A=B A0 0 0 0
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0 0 0 00 0 0 0
0 0 0 0
0 1 0
0 0 0 1
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0 0 0 10 0 0 0
0 0 0 0
1 0 0
0 0 0 0
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0 0 0 00 0 0 1
0 0 0 1
0 0 1
Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
1. What is magnitude comparator?2. What is most significant bit?
3. Explain operation of AND gate.
4. Explain truth table of a comparator.
5. Explain magnitude comparator7485 IC.
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6. What is 8-bit input Magnitude Comparator?7. What is IC?
8. Explain the k-map simplification of A>B.
9. Explain the k-map simplification of A=B.
10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
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12. What is the truth table of 1-bit magnitude comparator?13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION
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31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Aim:To design, construct and study the performance of 4-bit different code converters
(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
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(iv) Excess-3 to BCD code converterApparatus required:
Sl.No Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
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6. EX-OR gate IC 7486 17. Connecting wires As required
Theory:
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The availability of large variety of codes for the same discrete elements of information results inthe use of different codes by different systems. A conversion circuit must be inserted between the two
systems if each uses different codes for same information. Thus, code converter is a circuit that makes the
two systems compatible even though each uses different binary code. The bit combination assigned to
binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
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and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a
circuit that makes the two systems compatible even though each uses a different binary code. To convert
from binary code to Excess-3 code, the input lines must supply the bit combination of elements as
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specified by code and the output lines generate the corresponding bit combination of code. Each one of thefour maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are
various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is
C+D has been used to implement partially each of three outputs.
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Logic diagram:
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32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(i) Binary to gray code converterLogic Diagram:
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K map for G3:G3 = B3
K map for G2:
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K map for G1:
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33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for G0:
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Truth table:
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00
0
0
0
--- Content provided by FirstRanker.com ---
00
0
1
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
0
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
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(ii) Gray to binary code converter
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34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Logic Diagram:
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K map for B3:
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B3=G3
K map for B2:
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00G3 G2 G1 G0 B3 B2 B1 B0
0
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00
0
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
0
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
0
0
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00
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
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11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
0
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
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10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
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K map for B1:K map for B0:
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Truth table:
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
(iii) BCD to excess-3 code converter
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Logic Diagram:K map for E3:
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E3 = B3 + B2 (B0 + B1)
K map for E2:
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00K map for E1:
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K map for E0:
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Truth table:
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(iv) Excess-3 to
B3 B2 B1 B0 G3 G2 G1 G0
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0
0
0
0
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
1
x
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xx
x
x
x
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0
1
1
1
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10
0
0
0
--- Content provided by FirstRanker.com ---
1x
x
x
x
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xx
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
x
x
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xx
x
x
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10
1
0
1
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01
0
1
0
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xx
x
x
x
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x38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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BCD code converter
Logic Diagram:
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K map for A:
A = X1 X2 + X3 X4 X1
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K map for B:
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39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00K map for C:
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K map for D:
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Truth table:
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B3 B2 B1 B0 G3 G2 G1 G0
0
0
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00
0
1
1
--- Content provided by FirstRanker.com ---
11
1
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
1
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
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40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Procedure:
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1. Connections were given as per circuit diagram.2. Logical inputs were given as per truth table
3. Observe the logical output and verify with the truth tables.
Result:
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Thus the code converters were designed and verified using the corresponding truth table.Outcome:
At the completion of an experiment student will able to design the binary to gray converter.
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1. What is binary code?
2. What is gray code?
3. What are the advantages of gray code?
4. What is unit distance code?
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5. What is sequential code?6. How to convert binary to gray code?
7. How to convert gray to binary code?
8. What is reflective code?
9. What are the advantages of EX ? 3 code?
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10. Which code is used to arithmetic operation in digital circuits?11. Explain the operation of EX ? OR.
12. What is K ? Map?
13. Draw the truth table of EX- OR gate.
14. What is SOP?
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15. What is POS?16. What is minterm?
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Viva ? Voce
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41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.8: PARITY GENERATORS AND CHECKERSAim:
To implement the odd and even parity checkers using the logic gates and also to generate the odd parity
and even parity numbers using the generators
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Apparatus required:
Sl. No Component Type Quantity
1 Trainer Kit - 1
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2 EX-OR IC7486 13 NOT gate IC 7404 1
4 Connecting wires - Required
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Theory:Parity checking is used for error detection in data transmission.
Odd parity checkers:
It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
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odd.Even parity checker:
It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
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even.Odd parity generators:
It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also
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the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bitswhich is an odd parity number.
Even parity generator:
It generates an even parity number. The even parity checker circuit is used with the inverted output and
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also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5bits which is an even parity number.
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42 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Truth table:
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Input Checker output Generator output
A B C D D odd even odd even
0 0 0 1 1 0 00010 00011
0 0 1 0 1 0 00100 00101
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0 0 1 1 0 1 00111 001100 1 0 0 1 0 01000 01001
0 1 0 1 0 1 01011 01010
0 1 1 0 0 1 01101 01100
0 1 1 1 1 0 01110 01111
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1 0 0 0 1 0 10000 100011 0 0 1 0 1 10011 10010
1 0 1 0 0 1 10101 10100
1 0 1 1 1 0 10110 10111
1 1 0 0 0 1 11001 11000
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1 1 0 1 1 0 11010 110111 1 1 0 1 0 11100 11101
1 1 1 1 0 1 11111 11110
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Procedure:
1. The circuit is implemented using logic gates.
2. The inputs are given as per the truth table.
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3. The corresponding outputs are noted.
4. The theoretical and practical values were verified.
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Result:The odd and even parity checkers are implemented using the logic gates and the odd parity and
even parity numbers are generated using the corresponding generators.
Outcome:
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At the completion of an experiment student will able to verify the odd and even parity checkerusing logic gates.
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43 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
1. What is parity bit?
2. Why parity bit is added to message?
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3. What is parity checker?4. What is odd parity?
5. What is even parity?
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6. What are the gates involved for parity generator?7. List the procedures to convert gray code into binary.
8. Why weighted code is called as reflective codes?
9. What is a sequential code?
10. What is error deducting code?
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11. What is ASCII code?12. What is hamming code?
13. List the binary weighted code.
14. List the binary non weighted code.
15. Write the hamming code equation
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16. List the procedures to convert binary code into gray17. What are the applications of gray code?
18. What are the applications of Excess- 3 code?
Viva ? Voce
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44 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.9: MULTIPLEXER AND DEMULTIPLEXERAim:
To design and verify the truth table of a 4X1 multiplexer & 1X4 demultiplexer
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl. No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. OR gate IC 7432 1
3. NOT gate IC 7404 1
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4. AND gate ( three input ) IC 7411 15. Connecting wires As required
Theory:
Multiplexing means transmitting a large number of information units over a smaller number of channels or
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lines. A digital multiplexer is a combinational circuit that selects binary information from one of many inputlines and directs it to a single output line. The selection of particular input line is controlled by a set of
selection lines. Normally, there are 2
n
input lines and n selection lines whose bit combinations determines
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which input is selected. A multiplexer is called a data selector, since it selects one of many inputs andsteers the binary information to the output line. A Strobe is also provided to allow the designer to disable all
output data until a specified time. Then, by allowing the STROBE to go low, the proper lead can be
selected. This feature is very useful where data might be changing the same time DATA SELECT leads
change. It is a very useful Medium Scale Integration (MSI) function and has a multitude of applications. It is
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used for connecting two or more sources to a single destination among the computer units and it is usefulfor constructing a common bus system. A decoder with an enable input can function as a demultiplexer. A
Demultiplexer is a circuit that receives information on a single line and transmits this information on one of
2
n
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possible output lines. The selection of specific output line is controlled by the bit values of n selectionlines. The decoder and demultiplexer operations are obtained from the same circuit; a decoder with an
enable input is referred to as a decoder / de-multiplexer. The Strobe lead can be used to active or de-
active the entire IC, allowing time for the address lines to change the information is fed to the output.
Demultiplexers are useful anytime information from one source must be fed several places.
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45 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4 X 1 MULTIPLEXER
CIRCUIT DIAGRAM:
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46 Format No.FirstRanker/stud/LM/34/issue:00/revision:001X4 DEMULTIPLEXER
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CIRCUIT DIAGRAM:
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47 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Result:
The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth tables
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were verified.Outcome:
At the completion of an experiment student will able to design the multiplexer and the
demultiplexer
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--- Content provided by FirstRanker.com ---
1. What is multiplexer?2. What is demultiplexer?
3. What are the advantages of multiplexer?
4. What are the advantages of demultiplexer?
5. What is select signal?
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6. How to choose select signal in multiplexer?7. How to choose select signal in demultiplexer?
8. Write the formula used in select signal.
9. What is the difference between the multiplexer and demultiplexer?
10. What is the application of multiplexer?
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11. What is the application of demultiplexer?12. Draw the truth table of multiplexer.
13. Draw the truth table of demultiplexer.
14. How many select signals are needed in 8*1 multiplexer?
15. How many select signals are needed in 8*1 demultiplexer?
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Viva ? Voce
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48 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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EXP NO: 11 SHIFT REGISTERAim:
To design and implement the various shift register
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Apparatus required:
Sl. No Name of the Apparatus Range Quantity
1. D flip flop IC 7474 2
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2. OR gate IC 7432 13. IC Trainer kit 1
5. Connecting wires As required
Theory:
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A register is capable of shifting its binary information in one or both directions is
known as shift register. The logical configuration of shift register consist of a D-Flip flop
cascaded with output of one flip flop connected to input of next flip flop. All flip flops receive
common clock pulses which causes the shift in the output of the flip flop.The simplest possible
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shift register is one that uses only flip flop. The output of a given flip flop is connected to theinput of next flip flop of the register. Each clock pulse shifts the content of register one bit position
to right.
PIN Diagram:
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Logic Diagram:SERIAL IN SERIAL OUT
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FirstRanker.com - FirstRanker's Choice
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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
?DEPARTMENT OF
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COMPUTER SCIENCE ENGINEERINGIII SEMESTER - R 2017
CS8382 DIGITAL SYSTEMS LABORATORY
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Name : _______________________________________
Register No : _______________________________________
Section : _______________________________________
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LABORATORY MANUAL
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2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
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is committed to provide highly disciplined, conscientious andenterprising professionals conforming to global standards through value based quality education and
training.
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? To provide competent technical manpower capable of meeting requirements of the industry
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
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levels? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
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DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
--- Content provided by FirstRanker.com ---
Electrical and Electronics Engineers.--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?sneeds.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
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concepts with strongly supported laboratory and prepare them to meet the global needs of theindustry by continuous assessment and training.
VISION
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MISSION
VISION
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MISSION--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
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1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
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2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
technologies.
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3. BreadthTo provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
development of society.
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4. ProfessionalismTo inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
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5. Lifelong Learning/EthicsTo practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
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e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
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i. Graduates will show the understanding of impact of engineering solutions on the society and alsowill be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
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CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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SYLLABUSObjectives:
The student should be made to:
? Understand the various logic gates.
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? Be familiar with various combinational circuits.? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
? Learn to use HDL
List of experiments:
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1. Verification of Boolean Theorems using basic gates.2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
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b. Parity generator / checkerc. Magnitude Comparator
d. Application using multiplexers
4. Design and implementation of sequential circuits:
a. Shift ?registers
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b. Synchronous and asynchronous counters5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
Course Outcomes:
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? Use Boolean simplification techniques to design a combinational hardware circuit.? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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ContentSl.No. Name of the Experiment Page No.
1.
Verification of Boolean Theorems using Digital Logic Gates
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2.Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
3.
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Implementation of half adder and full adder4.
Implementation of half subtractor and full subtractor
5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
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MSI Devices6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
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7.
Design and Implementation of Magnitude Comparator.
8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
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9.Design and Implementation of Shift Registers.
10.
Design and Implementation of Synchronous and Asynchronous Counters.
11.
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Simulation of Combinational Circuits using Hardware Description Language (VHDL / VerilogHDL Software Required).
12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.1: STUDY OF BASIC GATES
Aim:
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To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gatesApparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
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6. NOR gate IC 7402 17. EX-OR gate IC 7486 1
8. Connecting wires As required
Theory:
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Circuit that takes the logical decision and the process are called logic gates. Each gate has one ormore input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
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output is high when both the inputs are high. The output is low level when any one of the inputs islow.
OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
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NOT gateA NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
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and any one of the input is low .The output is low level when both inputs are high.NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
EX-OR gate
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An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It issimilar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
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1. Connections are given as per the circuit diagram.2. For all the IC?s 7
th
pin is grounded and 14
th
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pin is given +5 supply.3. Apply the inputs and verify the truth table for all gates.
Result:
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The truth tables of all the basic logic gates were verified.
Outcome:
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At the completion of an experiment student will able to verify the truthtable of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
3. How many gates presented in IC 7408?
4. What is IC?
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5. What are the applications of gates?6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
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10. Write the truth table of NOR gate.11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
13. What are types of linear integrated circuit?
14. What is meant by etching?
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15. What are the advantages of IC?16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.2:
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VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gatesApparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
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6. NOR gate IC 7402 37. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:BASIC Boolean Laws
1. Commutative Law
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The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A
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2. Associative LawThe binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
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3. Distributive Law
The binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
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2. A.(B+C) = (A.B)+(A.C)4. Absorption Law
1. A+AB = A
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2. A+AB =A+B--- Content provided by FirstRanker.com ---
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:005. Idempotent Law
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1. A+A = A
2. A.A = A
6. Complementary Law
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1. A+A' = 1
2. A.A' = 0
7. De Morgan ?s Theorem
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1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
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A.B = A+BDesign
1. Absorption Law
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A+AB = A
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2. Involution (or) Double complement Law
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A = A
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3. Idempotent Law1. A+A = A
2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
A+B = A.B
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5. Distributive Law
A+(B.C) = (A+B).(A+C)
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Procedure:1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
cc
.
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3. Apply the inputs to the respective input pins.4. Verify the output with the truth table.
Result:
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Thus the above stated Boolean laws are verified.
Outcome:
At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?
2. What is associative law?
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3. What is mean by compliment gate?4. Explain the basic laws in digital electronics
5. What is double complement?
Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
To design and verify the truth table of the Half Adder & Full Adder circuits
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Apparatus required:S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:
The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
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0 + 0 = 00 + 1 = 1
1 + 0 = 1
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1 + 1 = 0 (with 1 as carry)
The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
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significant bit is called the sum.Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
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Full adder:A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
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From the truth table, the expression for sum and carry bits of the output can be obtained as,SUM = A?B?C + A?BC? + AB?C? + ABC
CARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half AdderTruth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,S = A B
Carry, C = A . B
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Circuit diagram:
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Full adderTruth table:
Sl.No. Input Output
A B C S C
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1. 0 0 0 0 02. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
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6. 1 0 1 0 17. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input OutputA B S C
1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
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4. 1 1 1 117 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:
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CARRY = AB + AC + BCLogic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
th
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pin is grounded and 14th
pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
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Result:The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
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At the completion of an experiment student will able to design the half adder circuit and thefull adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
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Aim:To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
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6. Connecting wires As requiredTheory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
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subtrahend bit, hence 1 is borrowed.Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
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difference and borrow bits.Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
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From the truth table the expression for difference and borrow bits of the output can be obtained
as,
Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
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Borrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Half subtractor
Truth table:
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Sl.No. Input Output
A B Difference Borrow
1. 0 0 0 0
2. 0 1 1 1
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3. 1 0 1 04. 1 1 0 0
From the truth table the expression for difference and borrow bits of the output can be obtained as,
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Difference, DIFF = A BBorrow, BORR = A?. B
Logic diagram:
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2. Full subtractor
Truth table:
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Sl.No.Input Output
A B C Difference Borrow
1. 0 0 0 0 0
2. 0 0 1 1 1
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3. 0 1 0 1 14. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
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8. 1 1 1 1 1--- Content provided by FirstRanker.com ---
21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Difference--- Content provided by FirstRanker.com ---
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Difference = A?B?C + A?BC? + AB?C? + ABCBorrow
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Borrow = A?B + A?C + BC
Circuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.5: 4-BIT ADDER AND SUBTRACTORAim:
To design and implement 4-bit adder and subtractor using IC 7483
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. IC IC 7483 13. NOT gate IC 7404 1
4. EX-OR gate IC 7486 1
5. Connecting wires As required
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Theory:4 BIT Binary adder:
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
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constructed with full adders connected in cascade, with the output carry from each full adder connected tothe input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
0
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and it ripples throughthe full adder to the output carry C
4
.
4 BIT Binary subtractor:
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The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
?B? and the corresponding input of full adder. The input carry C
0
must be equal to 1 when performing
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subtraction.4 BIT Binary adder / subtractor:
The addition and subtraction operation can be combined into one circuit with one common binary
adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
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becomes subtractor.23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PIN Diagram for IC 7483:
Logic Diagram: 4-Bit Binary Diagram:
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Logic diagram: 4-Bit Binary Subtractor:4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:--- Content provided by FirstRanker.com ---
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Procedure:1. Connections are given as per the circuit diagrams.
2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
.
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Result:The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
verified.
Outcome:
At the completion of an experiment student will able to design 4-bit binary adder and subtractor
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Input Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
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0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 00 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?2. Write the truth table for half adder.
3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
5. Write the truth table for full subtrator.
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6. Draw the logic diagram of full subtrator.7. What is adder?
8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
10. What is combinational circuit?
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11. What is different between combinational and sequential circuit?12. What are the gates involved for binary adder?
13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.6: MAGNITUDE COMPARATOR
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Aim:To design, construct and study the performance of 2 bit magnitude comparator
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
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7. Connecting wires As requiredTheory:
The comparison of two numbers is an operator that determines one number is greater than, less
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than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares twonumbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
three binary variables that indicate whether A>B, A=B (or) A
Truth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Logic Diagram:
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Pin Diagram for IC 7485:
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:
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Truth table:
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Procedure:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
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Result:
Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
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Outcome:At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
comparator using logic gates.
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A B A>B A=B A0 0 0 0
0 0 0 0
0 0 0 0
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0 0 0 00 1 0
0 0 0 1
0 0 0 1
0 0 0 0
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0 0 0 01 0 0
0 0 0 0
0 0 0 0
0 0 0 1
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0 0 0 10 0 1
Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is magnitude comparator?
2. What is most significant bit?
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3. Explain operation of AND gate.4. Explain truth table of a comparator.
5. Explain magnitude comparator7485 IC.
6. What is 8-bit input Magnitude Comparator?
7. What is IC?
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8. Explain the k-map simplification of A>B.9. Explain the k-map simplification of A=B.
10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
12. What is the truth table of 1-bit magnitude comparator?
13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION
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31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Aim:
To design, construct and study the performance of 4-bit different code converters
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(i) Binary to gray code converter(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:
The availability of large variety of codes for the same discrete elements of information results in
the use of different codes by different systems. A conversion circuit must be inserted between the two
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systems if each uses different codes for same information. Thus, code converter is a circuit that makes thetwo systems compatible even though each uses different binary code. The bit combination assigned to
binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
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designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is acircuit that makes the two systems compatible even though each uses a different binary code. To convert
from binary code to Excess-3 code, the input lines must supply the bit combination of elements as
specified by code and the output lines generate the corresponding bit combination of code. Each one of the
four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
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level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These arevarious other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is
C+D has been used to implement partially each of three outputs.
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Logic diagram:
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32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00(i) Binary to gray code converter
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Logic Diagram:K map for G3:
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G3 = B3
K map for G2:
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K map for G1:
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33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
K map for G0:
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Truth table:0
0
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00
0
0
0
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01
1
1
1
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11
1
1
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00
0
0
1
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11
1
0
0
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00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
1
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10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
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10
1
0
1
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01
0
1
0
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10
1
0
1
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0
0
0
0
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00
0
0
1
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11
1
1
1
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11
0
0
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00
1
1
1
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11
1
1
1
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00
0
0
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00
1
1
1
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10
0
0
0
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11
1
1
0
--- Content provided by FirstRanker.com ---
00
1
1
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00
1
1
0
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01
1
0
0
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11
0
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(ii) Gray to binary code converter
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34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:
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K map for B3:B3=G3
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K map for B2:--- Content provided by FirstRanker.com ---
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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G3 G2 G1 G0 B3 B2 B1 B00
0
0
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00
0
0
0
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11
1
1
1
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11
1
0
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00
0
1
1
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11
1
1
1
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10
0
0
0
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0
0
1
1
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11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
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00
0
1
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10
0
1
1
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00
1
1
0
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01
1
0
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00
0
0
0
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00
0
1
1
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11
1
1
1
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10
0
0
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01
1
1
1
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00
0
0
1
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11
1
0
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01
1
0
0
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11
0
0
1
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10
0
1
1
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0
1
0
1
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01
0
1
0
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10
1
0
1
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01
K map for B1:
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K map for B0:
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Truth table:--- Content provided by FirstRanker.com ---
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(iii) BCD to excess-3 code converter
Logic Diagram:
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K map for E3:
E3 = B3 + B2 (B0 + B1)
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K map for E2:
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for E1:
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K map for E0:
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Truth table:
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(iv) Excess-3 to
B3 B2 B1 B0 G3 G2 G1 G0
0
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00
0
0
0
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00
1
1
1
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11
1
1
1
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0
0
0
0
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11
1
1
0
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00
0
1
1
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11
0
0
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11
0
0
1
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10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
01
0
1
0
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10
1
0
1
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01
0
1
0
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10
0
0
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00
1
1
1
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11
x
x
x
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xx
x
0
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11
1
1
0
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00
0
1
x
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xx
x
x
x
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1
0
0
1
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10
0
1
1
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0x
x
x
x
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xx
1
0
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10
1
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01
0
x
x
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xx
x
x
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38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
BCD code converter
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Logic Diagram:
K map for A:
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A = X1 X2 + X3 X4 X1
K map for B:
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39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for C:
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K map for D:
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Truth table:
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B3 B2 B1 B0 G3 G2 G1 G0
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0
0
0
0
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01
1
1
1
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10
1
1
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11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
0
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01
1
0
0
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11
0
1
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01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
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00
0
0
0
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00
0
1
1
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0
0
0
0
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11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
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40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections were given as per circuit diagram.
2. Logical inputs were given as per truth table
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3. Observe the logical output and verify with the truth tables.Result:
Thus the code converters were designed and verified using the corresponding truth table.
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Outcome:At the completion of an experiment student will able to design the binary to gray converter.
1. What is binary code?
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2. What is gray code?3. What are the advantages of gray code?
4. What is unit distance code?
5. What is sequential code?
6. How to convert binary to gray code?
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7. How to convert gray to binary code?8. What is reflective code?
9. What are the advantages of EX ? 3 code?
10. Which code is used to arithmetic operation in digital circuits?
11. Explain the operation of EX ? OR.
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12. What is K ? Map?13. Draw the truth table of EX- OR gate.
14. What is SOP?
15. What is POS?
16. What is minterm?
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Viva ? Voce
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41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.8: PARITY GENERATORS AND CHECKERS
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Aim:To implement the odd and even parity checkers using the logic gates and also to generate the odd parity
and even parity numbers using the generators
Apparatus required:
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Sl. No Component Type Quantity
1 Trainer Kit - 1
2 EX-OR IC7486 1
3 NOT gate IC 7404 1
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4 Connecting wires - RequiredTheory:
Parity checking is used for error detection in data transmission.
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Odd parity checkers:It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
odd.
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Even parity checker:It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
even.
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Odd parity generators:It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also
the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bits
which is an odd parity number.
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Even parity generator:It generates an even parity number. The even parity checker circuit is used with the inverted output and
also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5
bits which is an even parity number.
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42 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Truth table:
Input Checker output Generator output
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A B C D D odd even odd even0 0 0 1 1 0 00010 00011
0 0 1 0 1 0 00100 00101
0 0 1 1 0 1 00111 00110
0 1 0 0 1 0 01000 01001
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0 1 0 1 0 1 01011 010100 1 1 0 0 1 01101 01100
0 1 1 1 1 0 01110 01111
1 0 0 0 1 0 10000 10001
1 0 0 1 0 1 10011 10010
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1 0 1 0 0 1 10101 101001 0 1 1 1 0 10110 10111
1 1 0 0 0 1 11001 11000
1 1 0 1 1 0 11010 11011
1 1 1 0 1 0 11100 11101
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1 1 1 1 0 1 11111 11110Procedure:
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1. The circuit is implemented using logic gates.2. The inputs are given as per the truth table.
3. The corresponding outputs are noted.
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4. The theoretical and practical values were verified.
Result:
The odd and even parity checkers are implemented using the logic gates and the odd parity and
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even parity numbers are generated using the corresponding generators.Outcome:
At the completion of an experiment student will able to verify the odd and even parity checker
using logic gates.
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43 Format No.FirstRanker/stud/LM/34/issue:00/revision:001. What is parity bit?
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2. Why parity bit is added to message?
3. What is parity checker?
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4. What is odd parity?5. What is even parity?
6. What are the gates involved for parity generator?
7. List the procedures to convert gray code into binary.
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8. Why weighted code is called as reflective codes?9. What is a sequential code?
10. What is error deducting code?
11. What is ASCII code?
12. What is hamming code?
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13. List the binary weighted code.14. List the binary non weighted code.
15. Write the hamming code equation
16. List the procedures to convert binary code into gray
17. What are the applications of gray code?
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18. What are the applications of Excess- 3 code?Viva ? Voce
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44 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.9: MULTIPLEXER AND DEMULTIPLEXER
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Aim:To design and verify the truth table of a 4X1 multiplexer & 1X4 demultiplexer
Apparatus required:
Sl. No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. OR gate IC 7432 1
3. NOT gate IC 7404 1
4. AND gate ( three input ) IC 7411 1
5. Connecting wires As required
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Theory:
Multiplexing means transmitting a large number of information units over a smaller number of channels or
lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input
lines and directs it to a single output line. The selection of particular input line is controlled by a set of
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selection lines. Normally, there are 2n
input lines and n selection lines whose bit combinations determines
which input is selected. A multiplexer is called a data selector, since it selects one of many inputs and
steers the binary information to the output line. A Strobe is also provided to allow the designer to disable all
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output data until a specified time. Then, by allowing the STROBE to go low, the proper lead can beselected. This feature is very useful where data might be changing the same time DATA SELECT leads
change. It is a very useful Medium Scale Integration (MSI) function and has a multitude of applications. It is
used for connecting two or more sources to a single destination among the computer units and it is useful
for constructing a common bus system. A decoder with an enable input can function as a demultiplexer. A
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Demultiplexer is a circuit that receives information on a single line and transmits this information on one of2
n
possible output lines. The selection of specific output line is controlled by the bit values of n selection
lines. The decoder and demultiplexer operations are obtained from the same circuit; a decoder with an
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enable input is referred to as a decoder / de-multiplexer. The Strobe lead can be used to active or de-active the entire IC, allowing time for the address lines to change the information is fed to the output.
Demultiplexers are useful anytime information from one source must be fed several places.
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45 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
4 X 1 MULTIPLEXER
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CIRCUIT DIAGRAM:
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46 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1X4 DEMULTIPLEXER--- Content provided by FirstRanker.com ---
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CIRCUIT DIAGRAM:--- Content provided by FirstRanker.com ---
47 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Result:
The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth tables
were verified.
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Outcome:At the completion of an experiment student will able to design the multiplexer and the
demultiplexer
--- Content provided by FirstRanker.com ---
1. What is multiplexer?
2. What is demultiplexer?
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3. What are the advantages of multiplexer?4. What are the advantages of demultiplexer?
5. What is select signal?
6. How to choose select signal in multiplexer?
7. How to choose select signal in demultiplexer?
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8. Write the formula used in select signal.9. What is the difference between the multiplexer and demultiplexer?
10. What is the application of multiplexer?
11. What is the application of demultiplexer?
12. Draw the truth table of multiplexer.
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13. Draw the truth table of demultiplexer.14. How many select signals are needed in 8*1 multiplexer?
15. How many select signals are needed in 8*1 demultiplexer?
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Viva ? Voce
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48 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
EXP NO: 11 SHIFT REGISTER
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Aim:To design and implement the various shift register
Apparatus required:
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Sl. No Name of the Apparatus Range Quantity
1. D flip flop IC 7474 2
2. OR gate IC 7432 1
3. IC Trainer kit 1
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5. Connecting wires As requiredTheory:
A register is capable of shifting its binary information in one or both directions is
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known as shift register. The logical configuration of shift register consist of a D-Flip flopcascaded with output of one flip flop connected to input of next flip flop. All flip flops receive
common clock pulses which causes the shift in the output of the flip flop.The simplest possible
shift register is one that uses only flip flop. The output of a given flip flop is connected to the
input of next flip flop of the register. Each clock pulse shifts the content of register one bit position
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to right.PIN Diagram:
Logic Diagram:
SERIAL IN SERIAL OUT
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49 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Truth Table:
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CLK Serial in Serial out
1 1 0
2 0 0
3 0 0
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4 1 15 X 0
6 X 0
7 X 1
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Logic Diagram:
Serial in parallel out:
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Truth Table:
CLK DATA
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OUTPUTQ
A
Q
B
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QC
Q
D
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1 1 1 0 0 02 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1
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Parallel in Serial Out:
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FirstRanker.com - FirstRanker's Choice
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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
?DEPARTMENT OF
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COMPUTER SCIENCE ENGINEERINGIII SEMESTER - R 2017
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
Section : _______________________________________
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LABORATORY MANUAL
--- Content provided by FirstRanker.com ---
2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious andenterprising professionals conforming to global standards through value based quality education and
training.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
--- Content provided by FirstRanker.com ---
levels? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
--- Content provided by FirstRanker.com ---
Electrical and Electronics Engineers.--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?sneeds.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
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concepts with strongly supported laboratory and prepare them to meet the global needs of theindustry by continuous assessment and training.
VISION
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MISSION
VISION
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MISSION--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
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1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
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2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
technologies.
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3. BreadthTo provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
development of society.
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4. ProfessionalismTo inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
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5. Lifelong Learning/EthicsTo practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
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e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
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i. Graduates will show the understanding of impact of engineering solutions on the society and alsowill be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
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CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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SYLLABUSObjectives:
The student should be made to:
? Understand the various logic gates.
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? Be familiar with various combinational circuits.? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
? Learn to use HDL
List of experiments:
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1. Verification of Boolean Theorems using basic gates.2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
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b. Parity generator / checkerc. Magnitude Comparator
d. Application using multiplexers
4. Design and implementation of sequential circuits:
a. Shift ?registers
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b. Synchronous and asynchronous counters5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
Course Outcomes:
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? Use Boolean simplification techniques to design a combinational hardware circuit.? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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ContentSl.No. Name of the Experiment Page No.
1.
Verification of Boolean Theorems using Digital Logic Gates
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2.Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
3.
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Implementation of half adder and full adder4.
Implementation of half subtractor and full subtractor
5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
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MSI Devices6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
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7.
Design and Implementation of Magnitude Comparator.
8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
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9.Design and Implementation of Shift Registers.
10.
Design and Implementation of Synchronous and Asynchronous Counters.
11.
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Simulation of Combinational Circuits using Hardware Description Language (VHDL / VerilogHDL Software Required).
12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.1: STUDY OF BASIC GATES
Aim:
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To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gatesApparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
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6. NOR gate IC 7402 17. EX-OR gate IC 7486 1
8. Connecting wires As required
Theory:
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Circuit that takes the logical decision and the process are called logic gates. Each gate has one ormore input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
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output is high when both the inputs are high. The output is low level when any one of the inputs islow.
OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
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NOT gateA NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
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and any one of the input is low .The output is low level when both inputs are high.NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
EX-OR gate
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An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It issimilar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
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1. Connections are given as per the circuit diagram.2. For all the IC?s 7
th
pin is grounded and 14
th
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pin is given +5 supply.3. Apply the inputs and verify the truth table for all gates.
Result:
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The truth tables of all the basic logic gates were verified.
Outcome:
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At the completion of an experiment student will able to verify the truthtable of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
3. How many gates presented in IC 7408?
4. What is IC?
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5. What are the applications of gates?6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
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10. Write the truth table of NOR gate.11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
13. What are types of linear integrated circuit?
14. What is meant by etching?
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15. What are the advantages of IC?16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.2:
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VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gatesApparatus required:
Sl.No Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
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6. NOR gate IC 7402 37. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:BASIC Boolean Laws
1. Commutative Law
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The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A
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2. Associative LawThe binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
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3. Distributive Law
The binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
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2. A.(B+C) = (A.B)+(A.C)4. Absorption Law
1. A+AB = A
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2. A+AB =A+B--- Content provided by FirstRanker.com ---
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:005. Idempotent Law
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1. A+A = A
2. A.A = A
6. Complementary Law
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1. A+A' = 1
2. A.A' = 0
7. De Morgan ?s Theorem
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1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
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A.B = A+BDesign
1. Absorption Law
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A+AB = A
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2. Involution (or) Double complement Law
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A = A
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3. Idempotent Law1. A+A = A
2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
A+B = A.B
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5. Distributive Law
A+(B.C) = (A+B).(A+C)
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Procedure:1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
cc
.
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3. Apply the inputs to the respective input pins.4. Verify the output with the truth table.
Result:
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Thus the above stated Boolean laws are verified.
Outcome:
At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?
2. What is associative law?
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3. What is mean by compliment gate?4. Explain the basic laws in digital electronics
5. What is double complement?
Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
To design and verify the truth table of the Half Adder & Full Adder circuits
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Apparatus required:S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:
The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
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0 + 0 = 00 + 1 = 1
1 + 0 = 1
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1 + 1 = 0 (with 1 as carry)
The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
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significant bit is called the sum.Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
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Full adder:A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
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From the truth table, the expression for sum and carry bits of the output can be obtained as,SUM = A?B?C + A?BC? + AB?C? + ABC
CARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half AdderTruth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,S = A B
Carry, C = A . B
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Circuit diagram:
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Full adderTruth table:
Sl.No. Input Output
A B C S C
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1. 0 0 0 0 02. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
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6. 1 0 1 0 17. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input OutputA B S C
1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
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4. 1 1 1 117 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:
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CARRY = AB + AC + BCLogic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
th
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pin is grounded and 14th
pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
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Result:The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
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At the completion of an experiment student will able to design the half adder circuit and thefull adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
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Aim:To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
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6. Connecting wires As requiredTheory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
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subtrahend bit, hence 1 is borrowed.Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
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difference and borrow bits.Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
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From the truth table the expression for difference and borrow bits of the output can be obtained
as,
Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
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Borrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Half subtractor
Truth table:
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Sl.No. Input Output
A B Difference Borrow
1. 0 0 0 0
2. 0 1 1 1
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3. 1 0 1 04. 1 1 0 0
From the truth table the expression for difference and borrow bits of the output can be obtained as,
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Difference, DIFF = A BBorrow, BORR = A?. B
Logic diagram:
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2. Full subtractor
Truth table:
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Sl.No.Input Output
A B C Difference Borrow
1. 0 0 0 0 0
2. 0 0 1 1 1
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3. 0 1 0 1 14. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
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8. 1 1 1 1 1--- Content provided by FirstRanker.com ---
21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Difference--- Content provided by FirstRanker.com ---
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Difference = A?B?C + A?BC? + AB?C? + ABCBorrow
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Borrow = A?B + A?C + BC
Circuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.5: 4-BIT ADDER AND SUBTRACTORAim:
To design and implement 4-bit adder and subtractor using IC 7483
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. IC IC 7483 13. NOT gate IC 7404 1
4. EX-OR gate IC 7486 1
5. Connecting wires As required
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Theory:4 BIT Binary adder:
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
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constructed with full adders connected in cascade, with the output carry from each full adder connected tothe input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
0
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and it ripples throughthe full adder to the output carry C
4
.
4 BIT Binary subtractor:
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The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
?B? and the corresponding input of full adder. The input carry C
0
must be equal to 1 when performing
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subtraction.4 BIT Binary adder / subtractor:
The addition and subtraction operation can be combined into one circuit with one common binary
adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
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becomes subtractor.23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PIN Diagram for IC 7483:
Logic Diagram: 4-Bit Binary Diagram:
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Logic diagram: 4-Bit Binary Subtractor:4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:--- Content provided by FirstRanker.com ---
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Procedure:1. Connections are given as per the circuit diagrams.
2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
.
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Result:The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
verified.
Outcome:
At the completion of an experiment student will able to design 4-bit binary adder and subtractor
--- Content provided by FirstRanker.com ---
Input Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
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0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 00 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
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1. What is expression for difference and borrow?2. Write the truth table for half adder.
3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
5. Write the truth table for full subtrator.
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6. Draw the logic diagram of full subtrator.7. What is adder?
8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
10. What is combinational circuit?
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11. What is different between combinational and sequential circuit?12. What are the gates involved for binary adder?
13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.6: MAGNITUDE COMPARATOR
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Aim:To design, construct and study the performance of 2 bit magnitude comparator
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
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7. Connecting wires As requiredTheory:
The comparison of two numbers is an operator that determines one number is greater than, less
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than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares twonumbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
three binary variables that indicate whether A>B, A=B (or) A
Truth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Logic Diagram:
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Pin Diagram for IC 7485:
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:
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Truth table:
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Procedure:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
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Result:
Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
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Outcome:At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
comparator using logic gates.
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A B A>B A=B A0 0 0 0
0 0 0 0
0 0 0 0
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0 0 0 00 1 0
0 0 0 1
0 0 0 1
0 0 0 0
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0 0 0 01 0 0
0 0 0 0
0 0 0 0
0 0 0 1
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0 0 0 10 0 1
Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is magnitude comparator?
2. What is most significant bit?
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3. Explain operation of AND gate.4. Explain truth table of a comparator.
5. Explain magnitude comparator7485 IC.
6. What is 8-bit input Magnitude Comparator?
7. What is IC?
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8. Explain the k-map simplification of A>B.9. Explain the k-map simplification of A=B.
10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
12. What is the truth table of 1-bit magnitude comparator?
13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION
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31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Aim:
To design, construct and study the performance of 4-bit different code converters
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(i) Binary to gray code converter(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:
The availability of large variety of codes for the same discrete elements of information results in
the use of different codes by different systems. A conversion circuit must be inserted between the two
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systems if each uses different codes for same information. Thus, code converter is a circuit that makes thetwo systems compatible even though each uses different binary code. The bit combination assigned to
binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
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designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is acircuit that makes the two systems compatible even though each uses a different binary code. To convert
from binary code to Excess-3 code, the input lines must supply the bit combination of elements as
specified by code and the output lines generate the corresponding bit combination of code. Each one of the
four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
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level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These arevarious other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is
C+D has been used to implement partially each of three outputs.
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Logic diagram:
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32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00(i) Binary to gray code converter
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Logic Diagram:K map for G3:
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G3 = B3
K map for G2:
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K map for G1:
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33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
K map for G0:
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Truth table:0
0
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00
0
0
0
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01
1
1
1
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11
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
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11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
0
0
0
0
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00
0
0
1
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11
1
1
1
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11
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
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01
1
0
0
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11
0
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(ii) Gray to binary code converter
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34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:
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K map for B3:B3=G3
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K map for B2:--- Content provided by FirstRanker.com ---
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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G3 G2 G1 G0 B3 B2 B1 B00
0
0
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00
0
0
0
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11
1
1
1
--- Content provided by FirstRanker.com ---
11
1
0
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00
0
1
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
0
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
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00
0
0
0
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00
0
1
1
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11
1
1
1
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10
0
0
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01
1
1
1
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00
0
0
1
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11
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
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11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
0
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
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10
1
0
1
--- Content provided by FirstRanker.com ---
01
K map for B1:
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K map for B0:
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Truth table:--- Content provided by FirstRanker.com ---
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(iii) BCD to excess-3 code converter
Logic Diagram:
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K map for E3:
E3 = B3 + B2 (B0 + B1)
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K map for E2:
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for E1:
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K map for E0:
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Truth table:
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(iv) Excess-3 to
B3 B2 B1 B0 G3 G2 G1 G0
0
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00
0
0
0
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00
1
1
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
0
0
0
0
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11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
11
x
x
x
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xx
x
0
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11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
x
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xx
x
x
x
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1
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
0x
x
x
x
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xx
1
0
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10
1
0
1
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01
0
x
x
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xx
x
x
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38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
BCD code converter
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Logic Diagram:
K map for A:
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A = X1 X2 + X3 X4 X1
K map for B:
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39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for C:
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K map for D:
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Truth table:
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B3 B2 B1 B0 G3 G2 G1 G0
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0
0
0
0
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01
1
1
1
--- Content provided by FirstRanker.com ---
10
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
0
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
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40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Procedure:
1. Connections were given as per circuit diagram.
2. Logical inputs were given as per truth table
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3. Observe the logical output and verify with the truth tables.Result:
Thus the code converters were designed and verified using the corresponding truth table.
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Outcome:At the completion of an experiment student will able to design the binary to gray converter.
1. What is binary code?
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2. What is gray code?3. What are the advantages of gray code?
4. What is unit distance code?
5. What is sequential code?
6. How to convert binary to gray code?
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7. How to convert gray to binary code?8. What is reflective code?
9. What are the advantages of EX ? 3 code?
10. Which code is used to arithmetic operation in digital circuits?
11. Explain the operation of EX ? OR.
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12. What is K ? Map?13. Draw the truth table of EX- OR gate.
14. What is SOP?
15. What is POS?
16. What is minterm?
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Viva ? Voce
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41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.8: PARITY GENERATORS AND CHECKERS
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Aim:To implement the odd and even parity checkers using the logic gates and also to generate the odd parity
and even parity numbers using the generators
Apparatus required:
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Sl. No Component Type Quantity
1 Trainer Kit - 1
2 EX-OR IC7486 1
3 NOT gate IC 7404 1
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4 Connecting wires - RequiredTheory:
Parity checking is used for error detection in data transmission.
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Odd parity checkers:It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
odd.
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Even parity checker:It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
even.
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Odd parity generators:It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also
the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bits
which is an odd parity number.
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Even parity generator:It generates an even parity number. The even parity checker circuit is used with the inverted output and
also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5
bits which is an even parity number.
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42 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Truth table:
Input Checker output Generator output
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A B C D D odd even odd even0 0 0 1 1 0 00010 00011
0 0 1 0 1 0 00100 00101
0 0 1 1 0 1 00111 00110
0 1 0 0 1 0 01000 01001
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0 1 0 1 0 1 01011 010100 1 1 0 0 1 01101 01100
0 1 1 1 1 0 01110 01111
1 0 0 0 1 0 10000 10001
1 0 0 1 0 1 10011 10010
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1 0 1 0 0 1 10101 101001 0 1 1 1 0 10110 10111
1 1 0 0 0 1 11001 11000
1 1 0 1 1 0 11010 11011
1 1 1 0 1 0 11100 11101
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1 1 1 1 0 1 11111 11110Procedure:
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1. The circuit is implemented using logic gates.2. The inputs are given as per the truth table.
3. The corresponding outputs are noted.
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4. The theoretical and practical values were verified.
Result:
The odd and even parity checkers are implemented using the logic gates and the odd parity and
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even parity numbers are generated using the corresponding generators.Outcome:
At the completion of an experiment student will able to verify the odd and even parity checker
using logic gates.
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43 Format No.FirstRanker/stud/LM/34/issue:00/revision:001. What is parity bit?
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2. Why parity bit is added to message?
3. What is parity checker?
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4. What is odd parity?5. What is even parity?
6. What are the gates involved for parity generator?
7. List the procedures to convert gray code into binary.
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8. Why weighted code is called as reflective codes?9. What is a sequential code?
10. What is error deducting code?
11. What is ASCII code?
12. What is hamming code?
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13. List the binary weighted code.14. List the binary non weighted code.
15. Write the hamming code equation
16. List the procedures to convert binary code into gray
17. What are the applications of gray code?
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18. What are the applications of Excess- 3 code?Viva ? Voce
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44 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.9: MULTIPLEXER AND DEMULTIPLEXER
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Aim:To design and verify the truth table of a 4X1 multiplexer & 1X4 demultiplexer
Apparatus required:
Sl. No Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. OR gate IC 7432 1
3. NOT gate IC 7404 1
4. AND gate ( three input ) IC 7411 1
5. Connecting wires As required
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Theory:
Multiplexing means transmitting a large number of information units over a smaller number of channels or
lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input
lines and directs it to a single output line. The selection of particular input line is controlled by a set of
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selection lines. Normally, there are 2n
input lines and n selection lines whose bit combinations determines
which input is selected. A multiplexer is called a data selector, since it selects one of many inputs and
steers the binary information to the output line. A Strobe is also provided to allow the designer to disable all
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output data until a specified time. Then, by allowing the STROBE to go low, the proper lead can beselected. This feature is very useful where data might be changing the same time DATA SELECT leads
change. It is a very useful Medium Scale Integration (MSI) function and has a multitude of applications. It is
used for connecting two or more sources to a single destination among the computer units and it is useful
for constructing a common bus system. A decoder with an enable input can function as a demultiplexer. A
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Demultiplexer is a circuit that receives information on a single line and transmits this information on one of2
n
possible output lines. The selection of specific output line is controlled by the bit values of n selection
lines. The decoder and demultiplexer operations are obtained from the same circuit; a decoder with an
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enable input is referred to as a decoder / de-multiplexer. The Strobe lead can be used to active or de-active the entire IC, allowing time for the address lines to change the information is fed to the output.
Demultiplexers are useful anytime information from one source must be fed several places.
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45 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
4 X 1 MULTIPLEXER
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CIRCUIT DIAGRAM:
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46 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1X4 DEMULTIPLEXER--- Content provided by FirstRanker.com ---
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CIRCUIT DIAGRAM:--- Content provided by FirstRanker.com ---
47 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Result:
The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth tables
were verified.
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Outcome:At the completion of an experiment student will able to design the multiplexer and the
demultiplexer
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1. What is multiplexer?
2. What is demultiplexer?
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3. What are the advantages of multiplexer?4. What are the advantages of demultiplexer?
5. What is select signal?
6. How to choose select signal in multiplexer?
7. How to choose select signal in demultiplexer?
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8. Write the formula used in select signal.9. What is the difference between the multiplexer and demultiplexer?
10. What is the application of multiplexer?
11. What is the application of demultiplexer?
12. Draw the truth table of multiplexer.
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13. Draw the truth table of demultiplexer.14. How many select signals are needed in 8*1 multiplexer?
15. How many select signals are needed in 8*1 demultiplexer?
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Viva ? Voce
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48 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
EXP NO: 11 SHIFT REGISTER
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Aim:To design and implement the various shift register
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl. No Name of the Apparatus Range Quantity
1. D flip flop IC 7474 2
2. OR gate IC 7432 1
3. IC Trainer kit 1
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5. Connecting wires As requiredTheory:
A register is capable of shifting its binary information in one or both directions is
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known as shift register. The logical configuration of shift register consist of a D-Flip flopcascaded with output of one flip flop connected to input of next flip flop. All flip flops receive
common clock pulses which causes the shift in the output of the flip flop.The simplest possible
shift register is one that uses only flip flop. The output of a given flip flop is connected to the
input of next flip flop of the register. Each clock pulse shifts the content of register one bit position
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to right.PIN Diagram:
Logic Diagram:
SERIAL IN SERIAL OUT
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49 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Truth Table:
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CLK Serial in Serial out
1 1 0
2 0 0
3 0 0
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4 1 15 X 0
6 X 0
7 X 1
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Logic Diagram:
Serial in parallel out:
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Truth Table:
CLK DATA
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OUTPUTQ
A
Q
B
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QC
Q
D
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1 1 1 0 0 02 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1
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Parallel in Serial Out:
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50 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
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3 0 0 0 0 1Truth Table:
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Parallel in Parallel Out:
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PARALLEL IN PARALLEL OUT:
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Truth Table:
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Procedure:
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1. Connections are given as per circuit diagram2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
Result:
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Thus the implementation of shift registers using flip flops was completed successfully.
Outcome:
At the completion of an experiment student will able to design the various types of shift register.
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CLK
DATA INPUT OUTPUT
D
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A DB D
C D
D Q
A Q
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B QC Q
D
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
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FirstRanker.com - FirstRanker's Choice1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
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III SEMESTER - R 2017
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
Section : _______________________________________
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LABORATORY MANUAL
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2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
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enterprising professionals conforming to global standards through value based quality education andtraining.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
--- Content provided by FirstRanker.com ---
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
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DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
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needs.? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
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industry by continuous assessment and training.VISION
--- Content provided by FirstRanker.com ---
MISSIONVISION
MISSION
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3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
--- Content provided by FirstRanker.com ---
1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
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2. Core CompetenceTo train the students to meet the needs of core industry with an attitude of learning new
technologies.
3. Breadth
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To provide relevant training and experience to bridge the gap between theory and practice whichenable them to find solutions to problems in industry and research that contributes to the overall
development of society.
4. Professionalism
--- Content provided by FirstRanker.com ---
To inculcate professional and effective communication skills to the students to make them lead ateam and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
5. Lifelong Learning/Ethics
--- Content provided by FirstRanker.com ---
To practice ethical and professional responsibilities in the organization and society withcommitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
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f. Graduates will demonstrate skills to use modern engineering tools, software and equipment toanalyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
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will be aware of contemporary issues.j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
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CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
SYLLABUS
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Objectives:
The student should be made to:
? Understand the various logic gates.
? Be familiar with various combinational circuits.
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? Understand the various components used in the design of digital computers.? Be exposed to sequential circuits
? Learn to use HDL
List of experiments:
1. Verification of Boolean Theorems using basic gates.
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2. Design and implementation of combinational circuits using basic gates for arbitraryfunctions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
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c. Magnitude Comparatord. Application using multiplexers
4. Design and implementation of sequential circuits:
a. Shift ?registers
b. Synchronous and asynchronous counters
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5. Coding combinational / sequential circuits using HDL.6. Design and implementation of a simple digital system (Mini Project).
Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
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? Design and Implement combinational and sequential circuits.? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Content
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Sl.No. Name of the Experiment Page No.
1.
Verification of Boolean Theorems using Digital Logic Gates
2.
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Design and Implementation of Combinational Circuits using Basic Gates for ArbitraryFunctions, Code Converters
3.
Implementation of half adder and full adder
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4.Implementation of half subtractor and full subtractor
5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
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6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
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7.Design and Implementation of Magnitude Comparator.
8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
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Design and Implementation of Shift Registers.10.
Design and Implementation of Synchronous and Asynchronous Counters.
11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
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HDL Software Required).12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.1: STUDY OF BASIC GATES
Aim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
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7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
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more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known asuniversal gates. Basic gates form these gates.
AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
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low.OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
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A NOT gate is the physical realization of the complementation operation. The NOT gate iscalled an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
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NOR gateThe NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
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similar to OR gate but excludes the combination of both A and B being equal to one. The exclusiveOR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Procedure:
1. Connections are given as per the circuit diagram.
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2. For all the IC?s 7th
pin is grounded and 14
th
pin is given +5 supply.
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3. Apply the inputs and verify the truth table for all gates.Result:
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The truth tables of all the basic logic gates were verified.Outcome:
At the completion of an experiment student will able to verify the truth
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table of all basic gates--- Content provided by FirstRanker.com ---
1. List out the basic gate.2. Mention the universal gate.
3. How many gates presented in IC 7408?
4. What is IC?
5. What are the applications of gates?
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6. Write the truth table of AND gate.7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
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11. Write the truth table of EX- OR gate.12. What are the classifications of IC?
13. What are types of linear integrated circuit?
14. What is meant by etching?
15. What are the advantages of IC?
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16. Write the truth table of EX- NOR gate.Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.2:
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VERIFICATION OF BOOLEAN THEOREMS USING LOGICGATES
Aim: To verification of Boolean theorems using logic gates
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 3
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7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
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BASIC Boolean Laws
1. Commutative Law
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The binary operator OR, AND is said to be commutative if,1. A+B = B+A
2. A.B=B.A
2. Associative Law
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The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
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3. Distributive LawThe binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
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4. Absorption Law
1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
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1. A+A = A2. A.A = A
6. Complementary Law
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1. A+A' = 12. A.A' = 0
7. De Morgan ?s Theorem
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1. The complement of the sum is equal to the sum of the product of the individualcomplements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design
1. Absorption Law
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A+AB = A--- Content provided by FirstRanker.com ---
2. Involution (or) Double complement Law
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A = A--- Content provided by FirstRanker.com ---
3. Idempotent Law
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1. A+A = A
2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
A+B = A.B
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5. Distributive Law
A+(B.C) = (A+B).(A+C)
Procedure:
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1. Obtain the required IC along with the Digital trainer kit.2. Connect zero volts to GND pin and +5 volts to V
cc
.
3. Apply the inputs to the respective input pins.
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4. Verify the output with the truth table.Result:
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Thus the above stated Boolean laws are verified.Outcome:
At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?
2. What is associative law?
3. What is mean by compliment gate?
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4. Explain the basic laws in digital electronics5. What is double complement?
Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.3: HALF ADDER AND FULL ADDERAim:
To design and verify the truth table of the Half Adder & Full Adder circuits
Apparatus required:
--- Content provided by FirstRanker.com ---
S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
0 + 0 = 0
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0 + 1 = 1
1 + 0 = 1
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1 + 1 = 0 (with 1 as carry)The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
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Half adder:A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
Full adder:
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A combinational circuit which performs the arithmetic sum of three input bits is called full adder. Thethree input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
From the truth table, the expression for sum and carry bits of the output can be obtained as,
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SUM = A?B?C + A?BC? + AB?C? + ABCCARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half Adder
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Truth table:--- Content provided by FirstRanker.com ---
From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
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S = A BCarry, C = A . B
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Circuit diagram:--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
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Full adder
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Truth table:Sl.No. Input Output
A B C S C
1. 0 0 0 0 0
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2. 0 0 1 1 03. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
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7. 1 1 0 0 18. 1 1 1 1 1
Sl.No. Input Output
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A B S C1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,Sum:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:--- Content provided by FirstRanker.com ---
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CARRY = AB + AC + BC
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Logic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
--- Content provided by FirstRanker.com ---
1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
th
pin is grounded and 14
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thpin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
Result:
--- Content provided by FirstRanker.com ---
The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
At the completion of an experiment student will able to design the half adder circuit and the
--- Content provided by FirstRanker.com ---
full adder circuit.--- Content provided by FirstRanker.com ---
19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
Aim:
--- Content provided by FirstRanker.com ---
To design and verify the truth table of the half subtractor & full subtractor circuitsApparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
--- Content provided by FirstRanker.com ---
2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
--- Content provided by FirstRanker.com ---
Theory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
subtrahend bit, hence 1 is borrowed.
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Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
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Full subtractor:A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
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From the truth table the expression for difference and borrow bits of the output can be obtainedas,
Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
--- Content provided by FirstRanker.com ---
Borrow, BORR = A?BC + AB?C + ABC? +ABC--- Content provided by FirstRanker.com ---
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Half subtractor
Truth table:
--- Content provided by FirstRanker.com ---
Sl.No. Input OutputA B Difference Borrow
1. 0 0 0 0
2. 0 1 1 1
3. 1 0 1 0
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4. 1 1 0 0From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A B
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Borrow, BORR = A?. B
Logic diagram:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
2. Full subtractorTruth table:
Sl.No.
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Input OutputA B C Difference Borrow
1. 0 0 0 0 0
2. 0 0 1 1 1
3. 0 1 0 1 1
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4. 0 1 1 0 15. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
8. 1 1 1 1 1
--- Content provided by FirstRanker.com ---
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Difference
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Difference = A?B?C + A?BC? + AB?C? + ABC
--- Content provided by FirstRanker.com ---
Borrow
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Borrow = A?B + A?C + BCCircuit diagram:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
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Aim:
To design and implement 4-bit adder and subtractor using IC 7483
--- Content provided by FirstRanker.com ---
Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. IC IC 7483 1
--- Content provided by FirstRanker.com ---
3. NOT gate IC 7404 14. EX-OR gate IC 7486 1
5. Connecting wires As required
Theory:
--- Content provided by FirstRanker.com ---
4 BIT Binary adder:
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected to
--- Content provided by FirstRanker.com ---
the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? aredesignated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
0
and it ripples through
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the full adder to the output carry C4
.
4 BIT Binary subtractor:
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The circuit for subtracting A-B consists of an adder with inverters, placed between each data input?B? and the corresponding input of full adder. The input carry C
0
must be equal to 1 when performing
subtraction.
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4 BIT Binary adder / subtractor:The addition and subtraction operation can be combined into one circuit with one common binary
adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
becomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PIN Diagram for IC 7483:Logic Diagram: 4-Bit Binary Diagram:
Logic diagram: 4-Bit Binary Subtractor:
--- Content provided by FirstRanker.com ---
4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Truth table:
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--- Content provided by FirstRanker.com ---
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Procedure:
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1. Connections are given as per the circuit diagrams.2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
.
Result:
--- Content provided by FirstRanker.com ---
The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table wasverified.
Outcome:
At the completion of an experiment student will able to design 4-bit binary adder and subtractor
--- Content provided by FirstRanker.com ---
Input Data A Input Data B Addition SubtractionA4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
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0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 01 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?
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2. Write the truth table for half adder.3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
5. Write the truth table for full subtrator.
6. Draw the logic diagram of full subtrator.
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7. What is adder?8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
10. What is combinational circuit?
11. What is different between combinational and sequential circuit?
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12. What are the gates involved for binary adder?13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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--- Content provided by FirstRanker.com ---
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--- Content provided by FirstRanker.com ---
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Viva ? Voce--- Content provided by FirstRanker.com ---
26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.6: MAGNITUDE COMPARATOR
Aim:
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To design, construct and study the performance of 2 bit magnitude comparatorApparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
--- Content provided by FirstRanker.com ---
3. OR gate IC 7432 14. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:
The comparison of two numbers is an operator that determines one number is greater than, less
than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
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numbers A and B and determines their relative magnitude. The outcome of the comparator is specified bythree binary variables that indicate whether A>B, A=B (or) A
Truth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:
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Pin Diagram for IC 7485:--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:
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Truth table:
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Procedure:1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
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Result:Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
comparator using logic gates.
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--- Content provided by FirstRanker.com ---
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A B A>B A=B A0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
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0 1 00 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
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1 0 00 0 0 0
0 0 0 0
0 0 0 1
0 0 0 1
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0 0 1Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
1. What is magnitude comparator?
2. What is most significant bit?
3. Explain operation of AND gate.
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4. Explain truth table of a comparator.5. Explain magnitude comparator7485 IC.
6. What is 8-bit input Magnitude Comparator?
7. What is IC?
8. Explain the k-map simplification of A>B.
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9. Explain the k-map simplification of A=B.10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
12. What is the truth table of 1-bit magnitude comparator?
13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Aim:
To design, construct and study the performance of 4-bit different code converters
(i) Binary to gray code converter
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(ii) Gray to binary code converter(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:The availability of large variety of codes for the same discrete elements of information results in
the use of different codes by different systems. A conversion circuit must be inserted between the two
systems if each uses different codes for same information. Thus, code converter is a circuit that makes the
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two systems compatible even though each uses different binary code. The bit combination assigned tobinary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a
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circuit that makes the two systems compatible even though each uses a different binary code. To convertfrom binary code to Excess-3 code, the input lines must supply the bit combination of elements as
specified by code and the output lines generate the corresponding bit combination of code. Each one of the
four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are
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various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output isC+D has been used to implement partially each of three outputs.
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Logic diagram:32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(i) Binary to gray code converter
Logic Diagram:
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K map for G3:
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G3 = B3K map for G2:
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K map for G1:33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
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K map for G0:Truth table:
--- Content provided by FirstRanker.com ---
0
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
0
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
0
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
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11
0
0
1
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10
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(ii) Gray to binary code converter
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34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:K map for B3:
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B3=G3
K map for B2:
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
G3 G2 G1 G0 B3 B2 B1 B0
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0
0
0
0
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
0
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
01
0
1
0
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10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
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1K map for B1:
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K map for B0:
Truth table:
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(iii) BCD to excess-3 code converterLogic Diagram:
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K map for E3:E3 = B3 + B2 (B0 + B1)
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K map for E2:--- Content provided by FirstRanker.com ---
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for E1:--- Content provided by FirstRanker.com ---
K map for E0:--- Content provided by FirstRanker.com ---
Truth table:
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(iv) Excess-3 toB3 B2 B1 B0 G3 G2 G1 G0
0
0
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00
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
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10
1
0
1
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0
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
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1x
x
x
x
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xx
0
1
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11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
x
x
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xx
x
x
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
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xx
x
x
x
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x1
0
1
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01
0
1
0
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10
x
x
x
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xx
x
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38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
BCD code converter
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Logic Diagram:K map for A:
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A = X1 X2 + X3 X4 X1
K map for B:
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39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for C:--- Content provided by FirstRanker.com ---
K map for D:--- Content provided by FirstRanker.com ---
Truth table:--- Content provided by FirstRanker.com ---
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--- Content provided by FirstRanker.com ---
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B3 B2 B1 B0 G3 G2 G1 G0
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00
0
0
0
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11
1
1
1
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0
1
1
1
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10
0
0
0
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11
0
0
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11
0
0
1
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10
1
0
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10
1
0
1
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01
0
0
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00
0
0
0
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00
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1
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00
0
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1
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11
1
0
0
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0
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1
1
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00
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1
0
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00
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0
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10
1
0
1
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01
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40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections were given as per circuit diagram.
2. Logical inputs were given as per truth table
3. Observe the logical output and verify with the truth tables.
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Result:
Thus the code converters were designed and verified using the corresponding truth table.
Outcome:
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At the completion of an experiment student will able to design the binary to gray converter.1. What is binary code?
2. What is gray code?
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3. What are the advantages of gray code?4. What is unit distance code?
5. What is sequential code?
6. How to convert binary to gray code?
7. How to convert gray to binary code?
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8. What is reflective code?9. What are the advantages of EX ? 3 code?
10. Which code is used to arithmetic operation in digital circuits?
11. Explain the operation of EX ? OR.
12. What is K ? Map?
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13. Draw the truth table of EX- OR gate.14. What is SOP?
15. What is POS?
16. What is minterm?
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Viva ? Voce--- Content provided by FirstRanker.com ---
41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.8: PARITY GENERATORS AND CHECKERS
Aim:
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To implement the odd and even parity checkers using the logic gates and also to generate the odd parityand even parity numbers using the generators
Apparatus required:
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Sl. No Component Type Quantity1 Trainer Kit - 1
2 EX-OR IC7486 1
3 NOT gate IC 7404 1
4 Connecting wires - Required
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Theory:
Parity checking is used for error detection in data transmission.
Odd parity checkers:
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It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
odd.
Even parity checker:
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It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
even.
Odd parity generators:
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It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also
the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bits
which is an odd parity number.
Even parity generator:
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It generates an even parity number. The even parity checker circuit is used with the inverted output and
also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5
bits which is an even parity number.
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42 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:
Input Checker output Generator output
A B C D D odd even odd even
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0 0 0 1 1 0 00010 000110 0 1 0 1 0 00100 00101
0 0 1 1 0 1 00111 00110
0 1 0 0 1 0 01000 01001
0 1 0 1 0 1 01011 01010
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0 1 1 0 0 1 01101 011000 1 1 1 1 0 01110 01111
1 0 0 0 1 0 10000 10001
1 0 0 1 0 1 10011 10010
1 0 1 0 0 1 10101 10100
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1 0 1 1 1 0 10110 101111 1 0 0 0 1 11001 11000
1 1 0 1 1 0 11010 11011
1 1 1 0 1 0 11100 11101
1 1 1 1 0 1 11111 11110
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Procedure:
1. The circuit is implemented using logic gates.
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2. The inputs are given as per the truth table.
3. The corresponding outputs are noted.
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4. The theoretical and practical values were verified.Result:
The odd and even parity checkers are implemented using the logic gates and the odd parity and
even parity numbers are generated using the corresponding generators.
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Outcome:
At the completion of an experiment student will able to verify the odd and even parity checker
using logic gates.
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43 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is parity bit?
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2. Why parity bit is added to message?3. What is parity checker?
4. What is odd parity?
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5. What is even parity?6. What are the gates involved for parity generator?
7. List the procedures to convert gray code into binary.
8. Why weighted code is called as reflective codes?
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9. What is a sequential code?10. What is error deducting code?
11. What is ASCII code?
12. What is hamming code?
13. List the binary weighted code.
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14. List the binary non weighted code.15. Write the hamming code equation
16. List the procedures to convert binary code into gray
17. What are the applications of gray code?
18. What are the applications of Excess- 3 code?
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Viva ? Voce--- Content provided by FirstRanker.com ---
44 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.9: MULTIPLEXER AND DEMULTIPLEXER
Aim:
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To design and verify the truth table of a 4X1 multiplexer & 1X4 demultiplexerApparatus required:
Sl. No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. OR gate IC 7432 13. NOT gate IC 7404 1
4. AND gate ( three input ) IC 7411 1
5. Connecting wires As required
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Theory:Multiplexing means transmitting a large number of information units over a smaller number of channels or
lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input
lines and directs it to a single output line. The selection of particular input line is controlled by a set of
selection lines. Normally, there are 2
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ninput lines and n selection lines whose bit combinations determines
which input is selected. A multiplexer is called a data selector, since it selects one of many inputs and
steers the binary information to the output line. A Strobe is also provided to allow the designer to disable all
output data until a specified time. Then, by allowing the STROBE to go low, the proper lead can be
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selected. This feature is very useful where data might be changing the same time DATA SELECT leadschange. It is a very useful Medium Scale Integration (MSI) function and has a multitude of applications. It is
used for connecting two or more sources to a single destination among the computer units and it is useful
for constructing a common bus system. A decoder with an enable input can function as a demultiplexer. A
Demultiplexer is a circuit that receives information on a single line and transmits this information on one of
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2n
possible output lines. The selection of specific output line is controlled by the bit values of n selection
lines. The decoder and demultiplexer operations are obtained from the same circuit; a decoder with an
enable input is referred to as a decoder / de-multiplexer. The Strobe lead can be used to active or de-
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active the entire IC, allowing time for the address lines to change the information is fed to the output.Demultiplexers are useful anytime information from one source must be fed several places.
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45 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
4 X 1 MULTIPLEXER
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CIRCUIT DIAGRAM:--- Content provided by FirstRanker.com ---
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46 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
1X4 DEMULTIPLEXER
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CIRCUIT DIAGRAM:
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47 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Result:The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth tables
were verified.
Outcome:
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At the completion of an experiment student will able to design the multiplexer and thedemultiplexer
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1. What is multiplexer?
2. What is demultiplexer?
3. What are the advantages of multiplexer?
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4. What are the advantages of demultiplexer?5. What is select signal?
6. How to choose select signal in multiplexer?
7. How to choose select signal in demultiplexer?
8. Write the formula used in select signal.
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9. What is the difference between the multiplexer and demultiplexer?10. What is the application of multiplexer?
11. What is the application of demultiplexer?
12. Draw the truth table of multiplexer.
13. Draw the truth table of demultiplexer.
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14. How many select signals are needed in 8*1 multiplexer?15. How many select signals are needed in 8*1 demultiplexer?
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Viva ? Voce--- Content provided by FirstRanker.com ---
48 Format No.FirstRanker/stud/LM/34/issue:00/revision:00EXP NO: 11 SHIFT REGISTER
Aim:
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To design and implement the various shift register
Apparatus required:
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Sl. No Name of the Apparatus Range Quantity1. D flip flop IC 7474 2
2. OR gate IC 7432 1
3. IC Trainer kit 1
5. Connecting wires As required
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Theory:
A register is capable of shifting its binary information in one or both directions is
known as shift register. The logical configuration of shift register consist of a D-Flip flop
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cascaded with output of one flip flop connected to input of next flip flop. All flip flops receivecommon clock pulses which causes the shift in the output of the flip flop.The simplest possible
shift register is one that uses only flip flop. The output of a given flip flop is connected to the
input of next flip flop of the register. Each clock pulse shifts the content of register one bit position
to right.
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PIN Diagram:Logic Diagram:
SERIAL IN SERIAL OUT
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49 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Truth Table:
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CLK Serial in Serial out1 1 0
2 0 0
3 0 0
4 1 1
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5 X 06 X 0
7 X 1
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Logic Diagram:Serial in parallel out:
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Truth Table:
CLK DATA
OUTPUT
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QA
Q
B
Q
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CQ
D
1 1 1 0 0 0
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2 0 0 1 0 03 0 0 0 1 1
4 1 1 0 0 1
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Parallel in Serial Out:--- Content provided by FirstRanker.com ---
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50 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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CLK Q3 Q2 Q1 Q0 O/P0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1
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Truth Table:
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Parallel in Parallel Out:--- Content provided by FirstRanker.com ---
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PARALLEL IN PARALLEL OUT:--- Content provided by FirstRanker.com ---
Truth Table:
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Procedure:
1. Connections are given as per circuit diagram
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2. Logical inputs are given as per circuit diagram.3. Observe the output and verify the truth table.
Result:
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Thus the implementation of shift registers using flip flops was completed successfully.Outcome:
At the completion of an experiment student will able to design the various types of shift register.
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CLK
DATA INPUT OUTPUT
D
A D
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B DC D
D Q
A Q
B Q
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C QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
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51 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.12: SYNCHRONOUS UP/DOWN COUNTER
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Aim:
To design and implement 3 bit synchronous up/down counter
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Apparatus required:S.No Name of the Apparatus Range Quantity
1. JK Flip Flop IC 7474 2
2. OR gate IC 7432 1
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3. NOT gate IC 7404 14. AND gate ( three input ) IC 7411 1
5 XOR gate IC 7486 1
6 IC Trainer Kit 1
7. Connecting wires As required
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Theory:
A counter is a register capable of counting number of clock pulse arriving at its clock input.
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Counter represents the number of clock pulses arrived. An up/down counter is one that is capable ofprogressing in increasing order or decreasing order through a certain sequence. An up/down counter
is also called bidirectional counter. Usually up/down operation of the counter is controlled by up/down
signal. When this signal is high counter goes through up sequence and when up/down signal is low counter
follows reverse sequence.
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K map:
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FirstRanker.com - FirstRanker's Choice
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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OFCOMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
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CS8382 DIGITAL SYSTEMS LABORATORY--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
--- Content provided by FirstRanker.com ---
Section : _______________________________________--- Content provided by FirstRanker.com ---
LABORATORY MANUAL2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
training.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
--- Content provided by FirstRanker.com ---
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at differentlevels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
--- Content provided by FirstRanker.com ---
Engineering and thereby produce extremely well trained employable, socially responsible and innovativeElectrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
--- Content provided by FirstRanker.com ---
? To provide highest quality learning environment for the students emphasizing fundamentalconcepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
--- Content provided by FirstRanker.com ---
VISIONMISSION
VISION
--- Content provided by FirstRanker.com ---
MISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
--- Content provided by FirstRanker.com ---
engineering enabling them to solve complex problems in order to develop real time applications.2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
technologies.
--- Content provided by FirstRanker.com ---
3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
development of society.
--- Content provided by FirstRanker.com ---
4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
--- Content provided by FirstRanker.com ---
5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
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d. Graduates will be able to design a system, component or process as per needs and specifications.e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
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h. Graduates will be able to communicate effectively by both verbal and written form.i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
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CS8381 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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SYLLABUS
Objectives:
The student should be made to:
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? Understand the various logic gates.? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
? Learn to use HDL
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List of experiments:1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
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a. 4 ? bit binary adder / subtractorb. Parity generator / checker
c. Magnitude Comparator
d. Application using multiplexers
4. Design and implementation of sequential circuits:
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a. Shift ?registersb. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
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Course Outcomes:? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
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? Design and Implement a simple digital system.--- Content provided by FirstRanker.com ---
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Content
Sl.No. Name of the Experiment Page No.
1.
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Verification of Boolean Theorems using Digital Logic Gates2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
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3.Implementation of half adder and full adder
4.
Implementation of half subtractor and full subtractor
5.
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Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates andMSI Devices
6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
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Devices7.
Design and Implementation of Magnitude Comparator.
8.
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Design and Implementation of Application using Multiplexers / Demultiplexers.9.
Design and Implementation of Shift Registers.
10.
Design and Implementation of Synchronous and Asynchronous Counters.
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11.Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
12.
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Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).--- Content provided by FirstRanker.com ---
7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.1: STUDY OF BASIC GATES
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Aim:To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. NAND gate IC 7400 16. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND gate
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The AND gate performs a logical multiplication commonly known as AND function. Theoutput is high when both the inputs are high. The output is low level when any one of the inputs is
low.
OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
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high when any one of the inputs is high. The output is low level when both the inputs are low.NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
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The NAND gate is a contraction of AND-NOT. The output is high when both inputs are lowand any one of the input is low .The output is low level when both inputs are high.
NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
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EX-OR gateAn Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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AND Gate Symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
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OR Gate:--- Content provided by FirstRanker.com ---
OR GATE:--- Content provided by FirstRanker.com ---
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00NAND Gate symbol: PIN Diagram:
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NOR Gate:--- Content provided by FirstRanker.com ---
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
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1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
th
pin is grounded and 14
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thpin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
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Result:The truth tables of all the basic logic gates were verified.
Outcome:
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At the completion of an experiment student will able to verify the truth
table of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
3. How many gates presented in IC 7408?
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4. What is IC?5. What are the applications of gates?
6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
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9. Write the truth table of NAND gate.10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
13. What are types of linear integrated circuit?
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14. What is meant by etching?15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.2:VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gates
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
--- Content provided by FirstRanker.com ---
5. NAND gate IC 7400 16. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
BASIC Boolean Laws
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1. Commutative LawThe binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A
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2. Associative Law
The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
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2. A.(B.C) = (A.B).C3. Distributive Law
The binary operator OR, AND is said to be distributive if,
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1. A+(B.C) = (A+B).(A+C)2. A.(B+C) = (A.B)+(A.C)
4. Absorption Law
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1. A+AB = A2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law1. A+A = A
2. A.A = A
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6. Complementary Law1. A+A' = 1
2. A.A' = 0
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7. De Morgan ?s Theorem1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
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2. The complement of the product is equal to the sum of the individual complements.A.B = A+B
Design
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1. Absorption LawA+AB = A
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2. Involution (or) Double complement LawA = A
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3. Idempotent Law
1. A+A = A
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2. A.A = A--- Content provided by FirstRanker.com ---
14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
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A+B = A.B5. Distributive Law
A+(B.C) = (A+B).(A+C)
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Procedure:
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
cc
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.3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
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Result:Thus the above stated Boolean laws are verified.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to know the basic laws with their truth table.1. What is Demorgan?s law?
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2. What is associative law?3. What is mean by compliment gate?
4. Explain the basic laws in digital electronics
5. What is double complement?
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Viva ? Voce--- Content provided by FirstRanker.com ---
15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
To design and verify the truth table of the Half Adder & Full Adder circuits
--- Content provided by FirstRanker.com ---
Apparatus required:
S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
--- Content provided by FirstRanker.com ---
2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
--- Content provided by FirstRanker.com ---
Theory:
The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
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0 + 0 = 0
0 + 1 = 1
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1 + 0 = 11 + 1 = 0 (with 1 as carry)
The first three operations produce a sum of whose length is one digit, but when the last operation is
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performed the sum is two digits. The higher significant bit of this result is called a carry and lowersignificant bit is called the sum.
Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
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Full adder:
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
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From the truth table, the expression for sum and carry bits of the output can be obtained as,
SUM = A?B?C + A?BC? + AB?C? + ABC
CARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half Adder
Truth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
S = A B
Carry, C = A . B
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Circuit diagram:
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Full adder
Truth table:
Sl.No. Input Output
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A B C S C1. 0 0 0 0 0
2. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
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5. 1 0 0 1 06. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input Output
A B S C
1. 0 0 0 0
2. 0 1 1 0
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3. 1 0 1 04. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:
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CARRY = AB + AC + BC
Logic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
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thpin is grounded and 14
th
pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
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Result:
The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to design the half adder circuit and the
full adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
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Aim:
To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
--- Content provided by FirstRanker.com ---
5. EX-OR gate IC 7486 16. Connecting wires As required
Theory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
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is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than thesubtrahend bit, hence 1 is borrowed.
Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
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variables designate the minuend and the subtrahend bit, whereas the output variables produce thedifference and borrow bits.
Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
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implemented with two half subtractors and one OR gate.From the truth table the expression for difference and borrow bits of the output can be obtained
as,
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Difference, DIFF= A?B?C + A?BC? + AB?C? + ABCBorrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half subtractor
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Truth table:Sl.No. Input Output
A B Difference Borrow
1. 0 0 0 0
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2. 0 1 1 13. 1 0 1 0
4. 1 1 0 0
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From the truth table the expression for difference and borrow bits of the output can be obtained as,Difference, DIFF = A B
Borrow, BORR = A?. B
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Logic diagram:--- Content provided by FirstRanker.com ---
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2. Full subtractor
Truth table:
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Sl.No.
Input Output
A B C Difference Borrow
1. 0 0 0 0 0
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2. 0 0 1 1 13. 0 1 0 1 1
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 0
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7. 1 1 0 0 08. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
Borrow
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Borrow = A?B + A?C + BC
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Circuit diagram:--- Content provided by FirstRanker.com ---
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
Aim:
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To design and implement 4-bit adder and subtractor using IC 7483Apparatus required:
Sl.No Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. IC IC 7483 1
3. NOT gate IC 7404 1
4. EX-OR gate IC 7486 1
5. Connecting wires As required
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Theory:
4 BIT Binary adder:
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A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can beconstructed with full adders connected in cascade, with the output carry from each full adder connected to
the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
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0and it ripples through
the full adder to the output carry C
4
.
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4 BIT Binary subtractor:The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
?B? and the corresponding input of full adder. The input carry C
0
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must be equal to 1 when performingsubtraction.
4 BIT Binary adder / subtractor:
The addition and subtraction operation can be combined into one circuit with one common binary
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adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, itbecomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PIN Diagram for IC 7483:
Logic Diagram: 4-Bit Binary Diagram:
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Logic diagram: 4-Bit Binary Subtractor:
4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:
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Procedure:
1. Connections are given as per the circuit diagrams.
2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
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.Result:
The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
verified.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to design 4-bit binary adder and subtractorInput Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
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1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 00 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
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1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 125 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?
2. Write the truth table for half adder.
3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
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5. Write the truth table for full subtrator.6. Draw the logic diagram of full subtrator.
7. What is adder?
8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
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10. What is combinational circuit?11. What is different between combinational and sequential circuit?
12. What are the gates involved for binary adder?
13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.6: MAGNITUDE COMPARATOR
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Aim:
To design, construct and study the performance of 2 bit magnitude comparator
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
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6. EX-OR gate IC 7486 17. Connecting wires As required
Theory:
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The comparison of two numbers is an operator that determines one number is greater than, lessthan (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
three binary variables that indicate whether A>B, A=B (or) A
Truth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Logic Diagram:
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Pin Diagram for IC 7485:
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Logic Diagram:29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:Truth table:
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Procedure:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
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3. Observe the output and verify the truth table.Result:
Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
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Outcome:
At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
comparator using logic gates.
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--- Content provided by FirstRanker.com ---
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A B A>B A=B A0 0 0 0
0 0 0 0
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0 0 0 00 0 0 0
0 1 0
0 0 0 1
0 0 0 1
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0 0 0 00 0 0 0
1 0 0
0 0 0 0
0 0 0 0
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0 0 0 10 0 0 1
0 0 1
Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
1. What is magnitude comparator?
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2. What is most significant bit?3. Explain operation of AND gate.
4. Explain truth table of a comparator.
5. Explain magnitude comparator7485 IC.
6. What is 8-bit input Magnitude Comparator?
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7. What is IC?8. Explain the k-map simplification of A>B.
9. Explain the k-map simplification of A=B.
10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
12. What is the truth table of 1-bit magnitude comparator?
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13. What is the use of magnitude comparator?--- Content provided by FirstRanker.com ---
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Expt.No.7: CODE CONVERSION
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31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Aim:
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To design, construct and study the performance of 4-bit different code converters(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
--- Content provided by FirstRanker.com ---
2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
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7. Connecting wires As requiredTheory:
The availability of large variety of codes for the same discrete elements of information results in
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the use of different codes by different systems. A conversion circuit must be inserted between the twosystems if each uses different codes for same information. Thus, code converter is a circuit that makes the
two systems compatible even though each uses different binary code. The bit combination assigned to
binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
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and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit isdesigned. The Boolean functions are obtained from K-Map for each output variable. A code converter is a
circuit that makes the two systems compatible even though each uses a different binary code. To convert
from binary code to Excess-3 code, the input lines must supply the bit combination of elements as
specified by code and the output lines generate the corresponding bit combination of code. Each one of the
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four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are
various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is
C+D has been used to implement partially each of three outputs.
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Logic diagram:
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32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
(i) Binary to gray code converter
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Logic Diagram:
K map for G3:
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G3 = B3
K map for G2:
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K map for G1:
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33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for G0:
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Truth table:
0
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00
0
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
0
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
0
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
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(ii) Gray to binary code converter34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:
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K map for B3:
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B3=G3K map for B2:
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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G3 G2 G1 G0 B3 B2 B1 B0
0
0
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00
0
0
0
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01
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
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00
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
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00
1
1
1
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10
0
0
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11
0
0
1
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10
0
1
1
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00
1
1
0
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0
0
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0
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00
0
0
1
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1
1
1
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11
0
0
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00
1
1
1
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10
0
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1
1
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00
1
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01
1
0
0
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11
0
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10
1
0
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10
1
0
1
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01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
K map for B1:
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K map for B0:
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Truth table:
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00(iii) BCD to excess-3 code converter
Logic Diagram:
--- Content provided by FirstRanker.com ---
K map for E3:
--- Content provided by FirstRanker.com ---
E3 = B3 + B2 (B0 + B1)K map for E2:
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for E1:
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K map for E0:
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Truth table:
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(iv) Excess-3 to
B3 B2 B1 B0 G3 G2 G1 G0
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00
0
0
0
--- Content provided by FirstRanker.com ---
00
0
1
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
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00
0
0
1
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11
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
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11
0
0
1
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10
0
1
1
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0
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
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10
1
0
1
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01
0
0
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00
0
1
1
--- Content provided by FirstRanker.com ---
11
1
x
x
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xx
x
x
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01
1
1
1
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00
0
0
1
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xx
x
x
x
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x1
0
0
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11
0
0
1
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10
x
x
x
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xx
x
1
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01
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10
1
0
x
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xx
x
x
x
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38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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BCD code converterLogic Diagram:
--- Content provided by FirstRanker.com ---
K map for A:A = X1 X2 + X3 X4 X1
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K map for B:--- Content provided by FirstRanker.com ---
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39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
K map for C:
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K map for D:
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Truth table:
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B3 B2 B1 B0 G3 G2 G1 G00
0
0
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00
1
1
1
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11
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
1
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00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
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10
1
0
1
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01
0
1
0
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0
0
0
0
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00
0
0
1
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10
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
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00
0
0
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11
0
0
1
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10
0
0
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10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
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40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Procedure:
1. Connections were given as per circuit diagram.
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2. Logical inputs were given as per truth table3. Observe the logical output and verify with the truth tables.
Result:
Thus the code converters were designed and verified using the corresponding truth table.
--- Content provided by FirstRanker.com ---
Outcome:
At the completion of an experiment student will able to design the binary to gray converter.
--- Content provided by FirstRanker.com ---
1. What is binary code?2. What is gray code?
3. What are the advantages of gray code?
4. What is unit distance code?
5. What is sequential code?
--- Content provided by FirstRanker.com ---
6. How to convert binary to gray code?7. How to convert gray to binary code?
8. What is reflective code?
9. What are the advantages of EX ? 3 code?
10. Which code is used to arithmetic operation in digital circuits?
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11. Explain the operation of EX ? OR.12. What is K ? Map?
13. Draw the truth table of EX- OR gate.
14. What is SOP?
15. What is POS?
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16. What is minterm?--- Content provided by FirstRanker.com ---
Viva ? Voce
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41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.8: PARITY GENERATORS AND CHECKERS
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Aim:
To implement the odd and even parity checkers using the logic gates and also to generate the odd parity
and even parity numbers using the generators
--- Content provided by FirstRanker.com ---
Apparatus required:Sl. No Component Type Quantity
1 Trainer Kit - 1
2 EX-OR IC7486 1
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3 NOT gate IC 7404 14 Connecting wires - Required
Theory:
--- Content provided by FirstRanker.com ---
Parity checking is used for error detection in data transmission.Odd parity checkers:
It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
odd.
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Even parity checker:
It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
even.
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Odd parity generators:
It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also
the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bits
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which is an odd parity number.Even parity generator:
It generates an even parity number. The even parity checker circuit is used with the inverted output and
also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5
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bits which is an even parity number.--- Content provided by FirstRanker.com ---
42 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Truth table:
--- Content provided by FirstRanker.com ---
Input Checker output Generator outputA B C D D odd even odd even
0 0 0 1 1 0 00010 00011
0 0 1 0 1 0 00100 00101
0 0 1 1 0 1 00111 00110
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0 1 0 0 1 0 01000 010010 1 0 1 0 1 01011 01010
0 1 1 0 0 1 01101 01100
0 1 1 1 1 0 01110 01111
1 0 0 0 1 0 10000 10001
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1 0 0 1 0 1 10011 100101 0 1 0 0 1 10101 10100
1 0 1 1 1 0 10110 10111
1 1 0 0 0 1 11001 11000
1 1 0 1 1 0 11010 11011
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1 1 1 0 1 0 11100 111011 1 1 1 0 1 11111 11110
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Procedure:1. The circuit is implemented using logic gates.
2. The inputs are given as per the truth table.
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3. The corresponding outputs are noted.4. The theoretical and practical values were verified.
Result:
--- Content provided by FirstRanker.com ---
The odd and even parity checkers are implemented using the logic gates and the odd parity andeven parity numbers are generated using the corresponding generators.
Outcome:
At the completion of an experiment student will able to verify the odd and even parity checker
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using logic gates.--- Content provided by FirstRanker.com ---
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43 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
1. What is parity bit?2. Why parity bit is added to message?
3. What is parity checker?
--- Content provided by FirstRanker.com ---
4. What is odd parity?
5. What is even parity?
6. What are the gates involved for parity generator?
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7. List the procedures to convert gray code into binary.8. Why weighted code is called as reflective codes?
9. What is a sequential code?
10. What is error deducting code?
11. What is ASCII code?
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12. What is hamming code?13. List the binary weighted code.
14. List the binary non weighted code.
15. Write the hamming code equation
16. List the procedures to convert binary code into gray
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17. What are the applications of gray code?18. What are the applications of Excess- 3 code?
Viva ? Voce
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44 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.9: MULTIPLEXER AND DEMULTIPLEXER
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Aim:
To design and verify the truth table of a 4X1 multiplexer & 1X4 demultiplexer
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl. No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. OR gate IC 7432 1
3. NOT gate IC 7404 1
4. AND gate ( three input ) IC 7411 1
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5. Connecting wires As requiredTheory:
Multiplexing means transmitting a large number of information units over a smaller number of channels or
lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input
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lines and directs it to a single output line. The selection of particular input line is controlled by a set ofselection lines. Normally, there are 2
n
input lines and n selection lines whose bit combinations determines
which input is selected. A multiplexer is called a data selector, since it selects one of many inputs and
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steers the binary information to the output line. A Strobe is also provided to allow the designer to disable alloutput data until a specified time. Then, by allowing the STROBE to go low, the proper lead can be
selected. This feature is very useful where data might be changing the same time DATA SELECT leads
change. It is a very useful Medium Scale Integration (MSI) function and has a multitude of applications. It is
used for connecting two or more sources to a single destination among the computer units and it is useful
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for constructing a common bus system. A decoder with an enable input can function as a demultiplexer. ADemultiplexer is a circuit that receives information on a single line and transmits this information on one of
2
n
possible output lines. The selection of specific output line is controlled by the bit values of n selection
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lines. The decoder and demultiplexer operations are obtained from the same circuit; a decoder with anenable input is referred to as a decoder / de-multiplexer. The Strobe lead can be used to active or de-
active the entire IC, allowing time for the address lines to change the information is fed to the output.
Demultiplexers are useful anytime information from one source must be fed several places.
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45 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4 X 1 MULTIPLEXERCIRCUIT DIAGRAM:
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46 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1X4 DEMULTIPLEXER
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CIRCUIT DIAGRAM:
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47 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Result:
The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth tables
were verified.
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Outcome:
At the completion of an experiment student will able to design the multiplexer and the
demultiplexer
--- Content provided by FirstRanker.com ---
1. What is multiplexer?
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2. What is demultiplexer?3. What are the advantages of multiplexer?
4. What are the advantages of demultiplexer?
5. What is select signal?
6. How to choose select signal in multiplexer?
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7. How to choose select signal in demultiplexer?8. Write the formula used in select signal.
9. What is the difference between the multiplexer and demultiplexer?
10. What is the application of multiplexer?
11. What is the application of demultiplexer?
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12. Draw the truth table of multiplexer.13. Draw the truth table of demultiplexer.
14. How many select signals are needed in 8*1 multiplexer?
15. How many select signals are needed in 8*1 demultiplexer?
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Viva ? Voce
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48 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
EXP NO: 11 SHIFT REGISTER
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Aim:
To design and implement the various shift register
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Apparatus required:Sl. No Name of the Apparatus Range Quantity
1. D flip flop IC 7474 2
2. OR gate IC 7432 1
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3. IC Trainer kit 15. Connecting wires As required
Theory:
--- Content provided by FirstRanker.com ---
A register is capable of shifting its binary information in one or both directions isknown as shift register. The logical configuration of shift register consist of a D-Flip flop
cascaded with output of one flip flop connected to input of next flip flop. All flip flops receive
common clock pulses which causes the shift in the output of the flip flop.The simplest possible
shift register is one that uses only flip flop. The output of a given flip flop is connected to the
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input of next flip flop of the register. Each clock pulse shifts the content of register one bit positionto right.
PIN Diagram:
Logic Diagram:
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SERIAL IN SERIAL OUT--- Content provided by FirstRanker.com ---
49 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth Table:CLK Serial in Serial out
1 1 0
2 0 0
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3 0 04 1 1
5 X 0
6 X 0
7 X 1
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Logic Diagram:
Serial in parallel out:
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Truth Table:
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CLK DATAOUTPUT
Q
A
Q
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BQ
C
Q
D
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1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1
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Parallel in Serial Out:
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50 Format No.FirstRanker/stud/LM/34/issue:00/revision:00CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
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2 0 0 0 0 03 0 0 0 0 1
Truth Table:
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Parallel in Parallel Out:
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PARALLEL IN PARALLEL OUT:
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Truth Table:
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Procedure:
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1. Connections are given as per circuit diagram
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
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Result:Thus the implementation of shift registers using flip flops was completed successfully.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to design the various types of shift register.--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
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CLK
DATA INPUT OUTPUT
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DA D
B D
C D
D Q
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A QB Q
C Q
D
1 1 0 0 1 1 0 0 1
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2 1 0 1 0 1 0 1 051 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.12: SYNCHRONOUS UP/DOWN COUNTER
Aim:
--- Content provided by FirstRanker.com ---
To design and implement 3 bit synchronous up/down counterApparatus required:
S.No Name of the Apparatus Range Quantity
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1. JK Flip Flop IC 7474 22. OR gate IC 7432 1
3. NOT gate IC 7404 1
4. AND gate ( three input ) IC 7411 1
5 XOR gate IC 7486 1
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6 IC Trainer Kit 17. Connecting wires As required
Theory:
--- Content provided by FirstRanker.com ---
A counter is a register capable of counting number of clock pulse arriving at its clock input.
Counter represents the number of clock pulses arrived. An up/down counter is one that is capable of
progressing in increasing order or decreasing order through a certain sequence. An up/down counter
is also called bidirectional counter. Usually up/down operation of the counter is controlled by up/down
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signal. When this signal is high counter goes through up sequence and when up/down signal is low counterfollows reverse sequence.
K map:
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52 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Q Q
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t+1 J K0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
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State Diagram:
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Characteristic Table:
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Logic Diagram:
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FirstRanker.com - FirstRanker's Choice
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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
?
--- Content provided by FirstRanker.com ---
DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
--- Content provided by FirstRanker.com ---
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
Name : _______________________________________
--- Content provided by FirstRanker.com ---
Register No : _______________________________________Section : _______________________________________
--- Content provided by FirstRanker.com ---
LABORATORY MANUAL
--- Content provided by FirstRanker.com ---
2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
training.
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? To provide competent technical manpower capable of meeting requirements of the industry
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? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
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heart and soulDEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
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To provide candidates with knowledge and skill in the field of Electrical and ElectronicsEngineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
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? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
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professional ethical code.? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
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VISION
MISSION
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VISIONMISSION
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3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
1. Fundamentals
--- Content provided by FirstRanker.com ---
To provide students with a solid foundation in mathematics, science and fundamentals ofengineering enabling them to solve complex problems in order to develop real time applications.
2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
--- Content provided by FirstRanker.com ---
technologies.3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
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development of society.4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
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professional ethics at all strategies.5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM OUTCOMES (POs)a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
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c. Graduates will be able to design and conduct experiments, analyze and interpret data.d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
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g. Graduates will demonstrate knowledge of professional and ethical responsibilities.h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
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k. Graduate who can participate and succeed in competitive examinations.--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
SYLLABUS
Objectives:
--- Content provided by FirstRanker.com ---
The student should be made to:? Understand the various logic gates.
? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
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? Learn to use HDLList of experiments:
1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
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3. Design and implementation of combinational circuits using MSI devices:a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
c. Magnitude Comparator
d. Application using multiplexers
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4. Design and implementation of sequential circuits:a. Shift ?registers
b. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
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Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
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? Design the different functional units in a digital computer system.? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Content
Sl.No. Name of the Experiment Page No.
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1.Verification of Boolean Theorems using Digital Logic Gates
2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
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3.
Implementation of half adder and full adder
4.
Implementation of half subtractor and full subtractor
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5.Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
6.
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Design and Implementation of Parity Generator / Checker using Basic Gates and MSIDevices
7.
Design and Implementation of Magnitude Comparator.
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8.Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
Design and Implementation of Shift Registers.
10.
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Design and Implementation of Synchronous and Asynchronous Counters.11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
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12.Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.1: STUDY OF BASIC GATES
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Aim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. NAND gate IC 7400 1
6. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
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AND gateThe AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
low.
OR gate
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The OR gate performs a logical addition commonly known as OR function. The output ishigh when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
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NAND gateThe NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
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output is low when one or both inputs are high.EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
EXOR Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
th
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pin is grounded and 14th
pin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
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Result:
The truth tables of all the basic logic gates were verified.
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Outcome:At the completion of an experiment student will able to verify the truth
table of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
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3. How many gates presented in IC 7408?4. What is IC?
5. What are the applications of gates?
6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
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8. Write the truth table of NOT gate.9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
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13. What are types of linear integrated circuit?14. What is meant by etching?
15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.2:
VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gates
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. NAND gate IC 7400 1
6. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
BASIC Boolean Laws
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1. Commutative Law
The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
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2. A.B=B.A2. Associative Law
The binary operator OR, AND is said to be associative if,
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1. A+(B+C) = (A+B)+C2. A.(B.C) = (A.B).C
3. Distributive Law
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The binary operator OR, AND is said to be distributive if,1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
4. Absorption Law
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1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
1. A+A = A
2. A.A = A
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6. Complementary Law
1. A+A' = 1
2. A.A' = 0
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7. De Morgan ?s Theorem
1. The complement of the sum is equal to the sum of the product of the individual
complements.
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A+B = A.B2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design1. Absorption Law
A+AB = A
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2. Involution (or) Double complement Law
A = A
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3. Idempotent Law
1. A+A = A
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2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:004. Demorgan ?s Law
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A+B = A.B
5. Distributive Law
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A+(B.C) = (A+B).(A+C)Procedure:
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
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cc.
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
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Result:
Thus the above stated Boolean laws are verified.
Outcome:
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At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?2. What is associative law?
3. What is mean by compliment gate?
4. Explain the basic laws in digital electronics
5. What is double complement?
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Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
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To design and verify the truth table of the Half Adder & Full Adder circuitsApparatus required:
S. No. Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
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6. Connecting wires As requiredTheory:
The most basic arithmetic operation is the addition of two binary digits. There are four
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possible elementary operations, namely,0 + 0 = 0
0 + 1 = 1
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1 + 0 = 1
1 + 1 = 0 (with 1 as carry)
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The first three operations produce a sum of whose length is one digit, but when the last operation isperformed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
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designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.Full adder:
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
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with two half adders and one OR gate.From the truth table, the expression for sum and carry bits of the output can be obtained as,
SUM = A?B?C + A?BC? + AB?C? + ABC
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CARRY = A?BC + AB?C + ABC? +ABC16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half Adder
Truth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
S = A B
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Carry, C = A . BCircuit diagram:
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Full adder
Truth table:
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Sl.No. Input OutputA B C S C
1. 0 0 0 0 0
2. 0 0 1 1 0
3. 0 1 0 1 0
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4. 0 1 1 0 15. 1 0 0 1 0
6. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input Output
A B S C
1. 0 0 0 0
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2. 0 1 1 03. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Sum:--- Content provided by FirstRanker.com ---
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B CCarry:
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CARRY = AB + AC + BC
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Logic Diagram:18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections are given as per the circuit diagrams.
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2. For all the IC?s 7th
pin is grounded and 14
th
pin is given +5 V supply.
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3. Apply the inputs and verify the truth table for the half adder and full adder circuits.Result:
The design of the half adder and full adder circuits was done and their truth tables were verified.
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Outcome:At the completion of an experiment student will able to design the half adder circuit and the
full adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTORAim:
To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. EX-OR gate IC 7486 1
6. Connecting wires As required
Theory:
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The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bitis subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
subtrahend bit, hence 1 is borrowed.
Half subtractor:
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A combinational circuit which performs the subtraction of two bits is called half subtractor. The inputvariables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
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three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can beimplemented with two half subtractors and one OR gate.
From the truth table the expression for difference and borrow bits of the output can be obtained
as,
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Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
Borrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half subtractor
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Truth table:
Sl.No. Input Output
A B Difference Borrow
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1. 0 0 0 02. 0 1 1 1
3. 1 0 1 0
4. 1 1 0 0
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From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A B
Borrow, BORR = A?. B
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Logic diagram:
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2. Full subtractor
Truth table:
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Sl.No.
Input Output
A B C Difference Borrow
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1. 0 0 0 0 02. 0 0 1 1 1
3. 0 1 0 1 1
4. 0 1 1 0 1
5. 1 0 0 1 0
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6. 1 0 1 0 07. 1 1 0 0 0
8. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
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Borrow--- Content provided by FirstRanker.com ---
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Borrow = A?B + A?C + BC
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Circuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
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Aim:To design and implement 4-bit adder and subtractor using IC 7483
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. IC IC 7483 1
3. NOT gate IC 7404 1
4. EX-OR gate IC 7486 1
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5. Connecting wires As requiredTheory:
4 BIT Binary adder:
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A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected to
the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
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carries are connected in chain through full adder. The input carry to the adder is C0
and it ripples through
the full adder to the output carry C
4
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.4 BIT Binary subtractor:
The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
?B? and the corresponding input of full adder. The input carry C
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0must be equal to 1 when performing
subtraction.
4 BIT Binary adder / subtractor:
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The addition and subtraction operation can be combined into one circuit with one common binaryadder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
becomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PIN Diagram for IC 7483:
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Logic Diagram: 4-Bit Binary Diagram:Logic diagram: 4-Bit Binary Subtractor:
4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:
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Procedure:
1. Connections are given as per the circuit diagrams.
2. Logical inputs were given as per circuit diagram.
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3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor..
Result:
The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
verified.
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Outcome:At the completion of an experiment student will able to design 4-bit binary adder and subtractor
Input Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
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1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 01 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
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1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 11 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
1. What is expression for difference and borrow?
2. Write the truth table for half adder.
3. Write the truth table for full adder.
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4. Write the truth table for half subtrator.5. Write the truth table for full subtrator.
6. Draw the logic diagram of full subtrator.
7. What is adder?
8. List out the application of adders.
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9. Draw the full adder using two half adder circuits.10. What is combinational circuit?
11. What is different between combinational and sequential circuit?
12. What are the gates involved for binary adder?
13. List the properties of Ex-Nor gate?
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.6: MAGNITUDE COMPARATORAim:
To design, construct and study the performance of 2 bit magnitude comparator
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. Magnitude comparator IC 7485 26. EX-OR gate IC 7486 1
7. Connecting wires As required
Theory:
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The comparison of two numbers is an operator that determines one number is greater than, less
than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
three binary variables that indicate whether A>B, A=B (or) A
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Truth table:--- Content provided by FirstRanker.com ---
27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Logic Diagram:
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Pin Diagram for IC 7485:
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
8 Bit Magnitude Comparator:
Truth table:
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Procedure:
1. Connections are given as per circuit diagram.
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2. Logical inputs are given as per circuit diagram.3. Observe the output and verify the truth table.
Result:
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Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.Outcome:
At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
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comparator using logic gates.--- Content provided by FirstRanker.com ---
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A B A>B A=B A0 0 0 0
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0 0 0 00 0 0 0
0 0 0 0
0 1 0
0 0 0 1
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0 0 0 10 0 0 0
0 0 0 0
1 0 0
0 0 0 0
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0 0 0 00 0 0 1
0 0 0 1
0 0 1
Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is magnitude comparator?2. What is most significant bit?
3. Explain operation of AND gate.
4. Explain truth table of a comparator.
5. Explain magnitude comparator7485 IC.
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6. What is 8-bit input Magnitude Comparator?7. What is IC?
8. Explain the k-map simplification of A>B.
9. Explain the k-map simplification of A=B.
10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
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12. What is the truth table of 1-bit magnitude comparator?13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION
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31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Aim:To design, construct and study the performance of 4-bit different code converters
(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
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(iv) Excess-3 to BCD code converterApparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
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6. EX-OR gate IC 7486 17. Connecting wires As required
Theory:
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The availability of large variety of codes for the same discrete elements of information results inthe use of different codes by different systems. A conversion circuit must be inserted between the two
systems if each uses different codes for same information. Thus, code converter is a circuit that makes the
two systems compatible even though each uses different binary code. The bit combination assigned to
binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
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and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a
circuit that makes the two systems compatible even though each uses a different binary code. To convert
from binary code to Excess-3 code, the input lines must supply the bit combination of elements as
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specified by code and the output lines generate the corresponding bit combination of code. Each one of thefour maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are
various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is
C+D has been used to implement partially each of three outputs.
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Logic diagram:
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32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(i) Binary to gray code converterLogic Diagram:
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K map for G3:G3 = B3
K map for G2:
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K map for G1:
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33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for G0:
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Truth table:
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00
0
0
0
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00
0
1
1
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11
1
1
1
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10
0
0
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01
1
1
1
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00
0
0
1
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11
1
0
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01
1
0
0
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11
0
0
1
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10
0
1
1
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0
1
0
1
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01
0
1
0
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10
1
0
1
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01
0
0
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00
0
0
0
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01
1
1
1
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11
1
1
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00
0
0
1
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11
1
1
1
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11
0
0
0
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00
0
1
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11
1
0
0
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00
1
1
1
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10
0
0
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11
0
0
1
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10
0
1
1
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00
1
1
0
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(ii) Gray to binary code converter
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34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Logic Diagram:
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K map for B3:
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B3=G3
K map for B2:
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00G3 G2 G1 G0 B3 B2 B1 B0
0
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00
0
0
0
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00
1
1
1
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11
1
1
1
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0
0
0
0
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11
1
1
1
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11
1
0
0
--- Content provided by FirstRanker.com ---
00
0
0
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11
1
1
0
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00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
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01
1
0
0
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11
0
0
1
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10
0
1
1
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00
0
0
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00
0
0
0
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11
1
1
1
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11
1
0
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00
0
1
1
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11
0
0
0
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01
1
1
1
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0
0
1
1
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00
1
1
0
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01
1
0
0
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11
0
1
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01
0
1
0
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10
1
0
1
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01
0
1
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K map for B1:K map for B0:
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Truth table:
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
(iii) BCD to excess-3 code converter
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Logic Diagram:K map for E3:
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E3 = B3 + B2 (B0 + B1)
K map for E2:
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00K map for E1:
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K map for E0:
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Truth table:
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(iv) Excess-3 to
B3 B2 B1 B0 G3 G2 G1 G0
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0
0
0
0
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00
0
0
1
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11
1
1
1
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11
0
0
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00
1
1
1
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10
0
0
0
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11
1
1
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00
1
1
0
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01
1
0
0
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11
0
0
1
--- Content provided by FirstRanker.com ---
10
1
0
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10
1
0
1
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01
0
1
0
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10
1
0
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00
0
0
1
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11
1
1
x
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xx
x
x
x
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0
1
1
1
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10
0
0
0
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1x
x
x
x
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xx
1
0
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01
1
0
0
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11
0
x
x
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xx
x
x
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10
1
0
1
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01
0
1
0
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xx
x
x
x
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x38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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BCD code converter
Logic Diagram:
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K map for A:
A = X1 X2 + X3 X4 X1
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K map for B:
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39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00K map for C:
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K map for D:
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Truth table:
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B3 B2 B1 B0 G3 G2 G1 G0
0
0
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00
0
1
1
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11
1
0
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11
1
1
0
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00
0
1
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10
0
1
1
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00
1
1
0
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1
0
1
0
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10
1
0
1
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00
0
0
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00
0
0
0
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11
0
0
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00
1
1
1
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10
0
0
--- Content provided by FirstRanker.com ---
01
1
0
0
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11
0
0
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01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
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40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Procedure:
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1. Connections were given as per circuit diagram.2. Logical inputs were given as per truth table
3. Observe the logical output and verify with the truth tables.
Result:
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Thus the code converters were designed and verified using the corresponding truth table.Outcome:
At the completion of an experiment student will able to design the binary to gray converter.
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1. What is binary code?
2. What is gray code?
3. What are the advantages of gray code?
4. What is unit distance code?
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5. What is sequential code?6. How to convert binary to gray code?
7. How to convert gray to binary code?
8. What is reflective code?
9. What are the advantages of EX ? 3 code?
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10. Which code is used to arithmetic operation in digital circuits?11. Explain the operation of EX ? OR.
12. What is K ? Map?
13. Draw the truth table of EX- OR gate.
14. What is SOP?
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15. What is POS?16. What is minterm?
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Viva ? Voce
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41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.8: PARITY GENERATORS AND CHECKERSAim:
To implement the odd and even parity checkers using the logic gates and also to generate the odd parity
and even parity numbers using the generators
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Apparatus required:
Sl. No Component Type Quantity
1 Trainer Kit - 1
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2 EX-OR IC7486 13 NOT gate IC 7404 1
4 Connecting wires - Required
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Theory:Parity checking is used for error detection in data transmission.
Odd parity checkers:
It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
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odd.Even parity checker:
It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
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even.Odd parity generators:
It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also
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the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bitswhich is an odd parity number.
Even parity generator:
It generates an even parity number. The even parity checker circuit is used with the inverted output and
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also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5bits which is an even parity number.
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42 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Truth table:
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Input Checker output Generator output
A B C D D odd even odd even
0 0 0 1 1 0 00010 00011
0 0 1 0 1 0 00100 00101
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0 0 1 1 0 1 00111 001100 1 0 0 1 0 01000 01001
0 1 0 1 0 1 01011 01010
0 1 1 0 0 1 01101 01100
0 1 1 1 1 0 01110 01111
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1 0 0 0 1 0 10000 100011 0 0 1 0 1 10011 10010
1 0 1 0 0 1 10101 10100
1 0 1 1 1 0 10110 10111
1 1 0 0 0 1 11001 11000
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1 1 0 1 1 0 11010 110111 1 1 0 1 0 11100 11101
1 1 1 1 0 1 11111 11110
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Procedure:
1. The circuit is implemented using logic gates.
2. The inputs are given as per the truth table.
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3. The corresponding outputs are noted.
4. The theoretical and practical values were verified.
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Result:The odd and even parity checkers are implemented using the logic gates and the odd parity and
even parity numbers are generated using the corresponding generators.
Outcome:
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At the completion of an experiment student will able to verify the odd and even parity checkerusing logic gates.
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43 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is parity bit?
2. Why parity bit is added to message?
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3. What is parity checker?4. What is odd parity?
5. What is even parity?
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6. What are the gates involved for parity generator?7. List the procedures to convert gray code into binary.
8. Why weighted code is called as reflective codes?
9. What is a sequential code?
10. What is error deducting code?
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11. What is ASCII code?12. What is hamming code?
13. List the binary weighted code.
14. List the binary non weighted code.
15. Write the hamming code equation
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16. List the procedures to convert binary code into gray17. What are the applications of gray code?
18. What are the applications of Excess- 3 code?
Viva ? Voce
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44 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.9: MULTIPLEXER AND DEMULTIPLEXERAim:
To design and verify the truth table of a 4X1 multiplexer & 1X4 demultiplexer
Apparatus required:
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Sl. No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. OR gate IC 7432 1
3. NOT gate IC 7404 1
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4. AND gate ( three input ) IC 7411 15. Connecting wires As required
Theory:
Multiplexing means transmitting a large number of information units over a smaller number of channels or
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lines. A digital multiplexer is a combinational circuit that selects binary information from one of many inputlines and directs it to a single output line. The selection of particular input line is controlled by a set of
selection lines. Normally, there are 2
n
input lines and n selection lines whose bit combinations determines
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which input is selected. A multiplexer is called a data selector, since it selects one of many inputs andsteers the binary information to the output line. A Strobe is also provided to allow the designer to disable all
output data until a specified time. Then, by allowing the STROBE to go low, the proper lead can be
selected. This feature is very useful where data might be changing the same time DATA SELECT leads
change. It is a very useful Medium Scale Integration (MSI) function and has a multitude of applications. It is
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used for connecting two or more sources to a single destination among the computer units and it is usefulfor constructing a common bus system. A decoder with an enable input can function as a demultiplexer. A
Demultiplexer is a circuit that receives information on a single line and transmits this information on one of
2
n
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possible output lines. The selection of specific output line is controlled by the bit values of n selectionlines. The decoder and demultiplexer operations are obtained from the same circuit; a decoder with an
enable input is referred to as a decoder / de-multiplexer. The Strobe lead can be used to active or de-
active the entire IC, allowing time for the address lines to change the information is fed to the output.
Demultiplexers are useful anytime information from one source must be fed several places.
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45 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4 X 1 MULTIPLEXER
CIRCUIT DIAGRAM:
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46 Format No.FirstRanker/stud/LM/34/issue:00/revision:001X4 DEMULTIPLEXER
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CIRCUIT DIAGRAM:
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47 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Result:
The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth tables
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were verified.Outcome:
At the completion of an experiment student will able to design the multiplexer and the
demultiplexer
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1. What is multiplexer?2. What is demultiplexer?
3. What are the advantages of multiplexer?
4. What are the advantages of demultiplexer?
5. What is select signal?
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6. How to choose select signal in multiplexer?7. How to choose select signal in demultiplexer?
8. Write the formula used in select signal.
9. What is the difference between the multiplexer and demultiplexer?
10. What is the application of multiplexer?
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11. What is the application of demultiplexer?12. Draw the truth table of multiplexer.
13. Draw the truth table of demultiplexer.
14. How many select signals are needed in 8*1 multiplexer?
15. How many select signals are needed in 8*1 demultiplexer?
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Viva ? Voce
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48 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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EXP NO: 11 SHIFT REGISTERAim:
To design and implement the various shift register
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Apparatus required:
Sl. No Name of the Apparatus Range Quantity
1. D flip flop IC 7474 2
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2. OR gate IC 7432 13. IC Trainer kit 1
5. Connecting wires As required
Theory:
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A register is capable of shifting its binary information in one or both directions is
known as shift register. The logical configuration of shift register consist of a D-Flip flop
cascaded with output of one flip flop connected to input of next flip flop. All flip flops receive
common clock pulses which causes the shift in the output of the flip flop.The simplest possible
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shift register is one that uses only flip flop. The output of a given flip flop is connected to theinput of next flip flop of the register. Each clock pulse shifts the content of register one bit position
to right.
PIN Diagram:
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Logic Diagram:SERIAL IN SERIAL OUT
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49 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth Table:
CLK Serial in Serial out
1 1 0
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2 0 03 0 0
4 1 1
5 X 0
6 X 0
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7 X 1Logic Diagram:
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Serial in parallel out:Truth Table:
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CLK DATA
OUTPUT
Q
A
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QB
Q
C
Q
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D1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
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4 1 1 0 0 1Parallel in Serial Out:
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50 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
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1 0 0 0 0 02 0 0 0 0 0
3 0 0 0 0 1
Truth Table:
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Parallel in Parallel Out:
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PARALLEL IN PARALLEL OUT:
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Truth Table:
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Procedure:1. Connections are given as per circuit diagram
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
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Result:
Thus the implementation of shift registers using flip flops was completed successfully.
Outcome:
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At the completion of an experiment student will able to design the various types of shift register.
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CLK
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DATA INPUT OUTPUTD
A D
B D
C D
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D QA Q
B Q
C Q
D
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1 1 0 0 1 1 0 0 12 1 0 1 0 1 0 1 0
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51 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.12: SYNCHRONOUS UP/DOWN COUNTER
Aim:
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To design and implement 3 bit synchronous up/down counter
Apparatus required:
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S.No Name of the Apparatus Range Quantity1. JK Flip Flop IC 7474 2
2. OR gate IC 7432 1
3. NOT gate IC 7404 1
4. AND gate ( three input ) IC 7411 1
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5 XOR gate IC 7486 16 IC Trainer Kit 1
7. Connecting wires As required
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Theory:A counter is a register capable of counting number of clock pulse arriving at its clock input.
Counter represents the number of clock pulses arrived. An up/down counter is one that is capable of
progressing in increasing order or decreasing order through a certain sequence. An up/down counter
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is also called bidirectional counter. Usually up/down operation of the counter is controlled by up/downsignal. When this signal is high counter goes through up sequence and when up/down signal is low counter
follows reverse sequence.
K map:
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52 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
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1 1 X 0State Diagram:
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Characteristic Table:--- Content provided by FirstRanker.com ---
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Logic Diagram:--- Content provided by FirstRanker.com ---
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53 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Input
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Up/DownPresent
State
Q
A
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QB
Q
C
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Next StateQ
A+1
Q
B+1
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QC+1
A
J
A
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KA
B
J
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BK
B
C
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JC
K
C
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0 0 0 0 1 1 1 1 X 1 X 1 X0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
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0 0 1 1 0 1 0 0 X X 0 X 10 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
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1 0 1 0 0 1 1 0 X X 0 1 X1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
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1 1 1 1 0 0 0 X 1 X 1 X 1Truth Table:
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Procedure:
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1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
Result:
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Thus the 3-bit synchronous up/down counters was implemented successfully.Outcome:
At the completion of an experiment student will able to design the synchronous up/down counter.
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FirstRanker.com - FirstRanker's Choice
--- Content provided by FirstRanker.com ---
1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
?DEPARTMENT OF
--- Content provided by FirstRanker.com ---
COMPUTER SCIENCE ENGINEERINGIII SEMESTER - R 2017
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
Section : _______________________________________
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LABORATORY MANUAL
--- Content provided by FirstRanker.com ---
2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious andenterprising professionals conforming to global standards through value based quality education and
training.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
--- Content provided by FirstRanker.com ---
levels? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
--- Content provided by FirstRanker.com ---
Electrical and Electronics Engineers.--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?sneeds.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
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concepts with strongly supported laboratory and prepare them to meet the global needs of theindustry by continuous assessment and training.
VISION
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MISSION
VISION
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MISSION--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
--- Content provided by FirstRanker.com ---
1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
--- Content provided by FirstRanker.com ---
2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
technologies.
--- Content provided by FirstRanker.com ---
3. BreadthTo provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
development of society.
--- Content provided by FirstRanker.com ---
4. ProfessionalismTo inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
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5. Lifelong Learning/EthicsTo practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
--- Content provided by FirstRanker.com ---
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
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e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
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i. Graduates will show the understanding of impact of engineering solutions on the society and alsowill be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
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CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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SYLLABUSObjectives:
The student should be made to:
? Understand the various logic gates.
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? Be familiar with various combinational circuits.? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
? Learn to use HDL
List of experiments:
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1. Verification of Boolean Theorems using basic gates.2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
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b. Parity generator / checkerc. Magnitude Comparator
d. Application using multiplexers
4. Design and implementation of sequential circuits:
a. Shift ?registers
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b. Synchronous and asynchronous counters5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
Course Outcomes:
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? Use Boolean simplification techniques to design a combinational hardware circuit.? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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ContentSl.No. Name of the Experiment Page No.
1.
Verification of Boolean Theorems using Digital Logic Gates
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2.Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
3.
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Implementation of half adder and full adder4.
Implementation of half subtractor and full subtractor
5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
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MSI Devices6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
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7.
Design and Implementation of Magnitude Comparator.
8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
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9.Design and Implementation of Shift Registers.
10.
Design and Implementation of Synchronous and Asynchronous Counters.
11.
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Simulation of Combinational Circuits using Hardware Description Language (VHDL / VerilogHDL Software Required).
12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.1: STUDY OF BASIC GATES
Aim:
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To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gatesApparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
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6. NOR gate IC 7402 17. EX-OR gate IC 7486 1
8. Connecting wires As required
Theory:
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Circuit that takes the logical decision and the process are called logic gates. Each gate has one ormore input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
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output is high when both the inputs are high. The output is low level when any one of the inputs islow.
OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
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NOT gateA NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
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and any one of the input is low .The output is low level when both inputs are high.NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
EX-OR gate
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An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It issimilar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
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1. Connections are given as per the circuit diagram.2. For all the IC?s 7
th
pin is grounded and 14
th
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pin is given +5 supply.3. Apply the inputs and verify the truth table for all gates.
Result:
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The truth tables of all the basic logic gates were verified.
Outcome:
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At the completion of an experiment student will able to verify the truthtable of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
3. How many gates presented in IC 7408?
4. What is IC?
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5. What are the applications of gates?6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
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10. Write the truth table of NOR gate.11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
13. What are types of linear integrated circuit?
14. What is meant by etching?
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15. What are the advantages of IC?16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.2:
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VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gatesApparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
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6. NOR gate IC 7402 37. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:BASIC Boolean Laws
1. Commutative Law
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The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A
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2. Associative LawThe binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
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3. Distributive Law
The binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
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2. A.(B+C) = (A.B)+(A.C)4. Absorption Law
1. A+AB = A
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2. A+AB =A+B--- Content provided by FirstRanker.com ---
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:005. Idempotent Law
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1. A+A = A
2. A.A = A
6. Complementary Law
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1. A+A' = 1
2. A.A' = 0
7. De Morgan ?s Theorem
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1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
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A.B = A+BDesign
1. Absorption Law
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A+AB = A
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2. Involution (or) Double complement Law
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A = A
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3. Idempotent Law1. A+A = A
2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
A+B = A.B
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5. Distributive Law
A+(B.C) = (A+B).(A+C)
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Procedure:1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
cc
.
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3. Apply the inputs to the respective input pins.4. Verify the output with the truth table.
Result:
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Thus the above stated Boolean laws are verified.
Outcome:
At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?
2. What is associative law?
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3. What is mean by compliment gate?4. Explain the basic laws in digital electronics
5. What is double complement?
Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
To design and verify the truth table of the Half Adder & Full Adder circuits
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Apparatus required:S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:
The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
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0 + 0 = 00 + 1 = 1
1 + 0 = 1
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1 + 1 = 0 (with 1 as carry)
The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
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significant bit is called the sum.Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
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Full adder:A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
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From the truth table, the expression for sum and carry bits of the output can be obtained as,SUM = A?B?C + A?BC? + AB?C? + ABC
CARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half AdderTruth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,S = A B
Carry, C = A . B
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Circuit diagram:
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Full adderTruth table:
Sl.No. Input Output
A B C S C
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1. 0 0 0 0 02. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
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6. 1 0 1 0 17. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input OutputA B S C
1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
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4. 1 1 1 117 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:
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CARRY = AB + AC + BCLogic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Procedure:1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
th
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pin is grounded and 14th
pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
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Result:The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
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At the completion of an experiment student will able to design the half adder circuit and thefull adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
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Aim:To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
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6. Connecting wires As requiredTheory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
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subtrahend bit, hence 1 is borrowed.Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
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difference and borrow bits.Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
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From the truth table the expression for difference and borrow bits of the output can be obtained
as,
Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
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Borrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Half subtractor
Truth table:
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Sl.No. Input Output
A B Difference Borrow
1. 0 0 0 0
2. 0 1 1 1
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3. 1 0 1 04. 1 1 0 0
From the truth table the expression for difference and borrow bits of the output can be obtained as,
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Difference, DIFF = A BBorrow, BORR = A?. B
Logic diagram:
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2. Full subtractor
Truth table:
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Sl.No.Input Output
A B C Difference Borrow
1. 0 0 0 0 0
2. 0 0 1 1 1
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3. 0 1 0 1 14. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
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8. 1 1 1 1 1--- Content provided by FirstRanker.com ---
21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Difference--- Content provided by FirstRanker.com ---
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Difference = A?B?C + A?BC? + AB?C? + ABCBorrow
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Borrow = A?B + A?C + BC
Circuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.5: 4-BIT ADDER AND SUBTRACTORAim:
To design and implement 4-bit adder and subtractor using IC 7483
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. IC IC 7483 13. NOT gate IC 7404 1
4. EX-OR gate IC 7486 1
5. Connecting wires As required
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Theory:4 BIT Binary adder:
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
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constructed with full adders connected in cascade, with the output carry from each full adder connected tothe input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
0
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and it ripples throughthe full adder to the output carry C
4
.
4 BIT Binary subtractor:
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The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
?B? and the corresponding input of full adder. The input carry C
0
must be equal to 1 when performing
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subtraction.4 BIT Binary adder / subtractor:
The addition and subtraction operation can be combined into one circuit with one common binary
adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
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becomes subtractor.23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PIN Diagram for IC 7483:
Logic Diagram: 4-Bit Binary Diagram:
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Logic diagram: 4-Bit Binary Subtractor:4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:--- Content provided by FirstRanker.com ---
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Procedure:1. Connections are given as per the circuit diagrams.
2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
.
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Result:The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
verified.
Outcome:
At the completion of an experiment student will able to design 4-bit binary adder and subtractor
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Input Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
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0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 00 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
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1. What is expression for difference and borrow?2. Write the truth table for half adder.
3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
5. Write the truth table for full subtrator.
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6. Draw the logic diagram of full subtrator.7. What is adder?
8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
10. What is combinational circuit?
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11. What is different between combinational and sequential circuit?12. What are the gates involved for binary adder?
13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.6: MAGNITUDE COMPARATOR
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Aim:To design, construct and study the performance of 2 bit magnitude comparator
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
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7. Connecting wires As requiredTheory:
The comparison of two numbers is an operator that determines one number is greater than, less
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than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares twonumbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
three binary variables that indicate whether A>B, A=B (or) A
Truth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Logic Diagram:
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Pin Diagram for IC 7485:
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:
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Truth table:
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Procedure:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
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Result:
Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
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Outcome:At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
comparator using logic gates.
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A B A>B A=B A0 0 0 0
0 0 0 0
0 0 0 0
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0 0 0 00 1 0
0 0 0 1
0 0 0 1
0 0 0 0
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0 0 0 01 0 0
0 0 0 0
0 0 0 0
0 0 0 1
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0 0 0 10 0 1
Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is magnitude comparator?
2. What is most significant bit?
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3. Explain operation of AND gate.4. Explain truth table of a comparator.
5. Explain magnitude comparator7485 IC.
6. What is 8-bit input Magnitude Comparator?
7. What is IC?
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8. Explain the k-map simplification of A>B.9. Explain the k-map simplification of A=B.
10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
12. What is the truth table of 1-bit magnitude comparator?
13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION
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31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Aim:
To design, construct and study the performance of 4-bit different code converters
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(i) Binary to gray code converter(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:
The availability of large variety of codes for the same discrete elements of information results in
the use of different codes by different systems. A conversion circuit must be inserted between the two
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systems if each uses different codes for same information. Thus, code converter is a circuit that makes thetwo systems compatible even though each uses different binary code. The bit combination assigned to
binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
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designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is acircuit that makes the two systems compatible even though each uses a different binary code. To convert
from binary code to Excess-3 code, the input lines must supply the bit combination of elements as
specified by code and the output lines generate the corresponding bit combination of code. Each one of the
four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
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level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These arevarious other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is
C+D has been used to implement partially each of three outputs.
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Logic diagram:
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32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00(i) Binary to gray code converter
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Logic Diagram:K map for G3:
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G3 = B3
K map for G2:
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K map for G1:
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33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
K map for G0:
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Truth table:0
0
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00
0
0
0
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01
1
1
1
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11
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
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11
1
0
0
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00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
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10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
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10
1
0
1
--- Content provided by FirstRanker.com ---
0
0
0
0
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00
0
0
1
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11
1
1
1
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11
0
0
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00
1
1
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
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00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
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11
1
1
0
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
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01
1
0
0
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11
0
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(ii) Gray to binary code converter
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34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:
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K map for B3:B3=G3
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K map for B2:--- Content provided by FirstRanker.com ---
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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G3 G2 G1 G0 B3 B2 B1 B00
0
0
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00
0
0
0
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11
1
1
1
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11
1
0
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00
0
1
1
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11
1
1
1
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10
0
0
0
--- Content provided by FirstRanker.com ---
0
0
1
1
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11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
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00
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
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00
0
0
0
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00
0
1
1
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11
1
1
1
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10
0
0
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01
1
1
1
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00
0
0
1
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11
1
0
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01
1
0
0
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11
0
0
1
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10
0
1
1
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0
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
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10
1
0
1
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01
K map for B1:
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K map for B0:
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Truth table:--- Content provided by FirstRanker.com ---
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(iii) BCD to excess-3 code converter
Logic Diagram:
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K map for E3:
E3 = B3 + B2 (B0 + B1)
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K map for E2:
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for E1:
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K map for E0:
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Truth table:
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(iv) Excess-3 to
B3 B2 B1 B0 G3 G2 G1 G0
0
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00
0
0
0
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00
1
1
1
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11
1
1
1
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0
0
0
0
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11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
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11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
11
x
x
x
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xx
x
0
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11
1
1
0
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00
0
1
x
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xx
x
x
x
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1
0
0
1
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10
0
1
1
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0x
x
x
x
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xx
1
0
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10
1
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1
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01
0
x
x
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xx
x
x
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38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
BCD code converter
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Logic Diagram:
K map for A:
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A = X1 X2 + X3 X4 X1
K map for B:
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39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for C:
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K map for D:
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Truth table:
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B3 B2 B1 B0 G3 G2 G1 G0
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0
0
0
0
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01
1
1
1
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10
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
0
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01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
1
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01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
0
0
0
0
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11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
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40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections were given as per circuit diagram.
2. Logical inputs were given as per truth table
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3. Observe the logical output and verify with the truth tables.Result:
Thus the code converters were designed and verified using the corresponding truth table.
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Outcome:At the completion of an experiment student will able to design the binary to gray converter.
1. What is binary code?
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2. What is gray code?3. What are the advantages of gray code?
4. What is unit distance code?
5. What is sequential code?
6. How to convert binary to gray code?
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7. How to convert gray to binary code?8. What is reflective code?
9. What are the advantages of EX ? 3 code?
10. Which code is used to arithmetic operation in digital circuits?
11. Explain the operation of EX ? OR.
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12. What is K ? Map?13. Draw the truth table of EX- OR gate.
14. What is SOP?
15. What is POS?
16. What is minterm?
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Viva ? Voce
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41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.8: PARITY GENERATORS AND CHECKERS
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Aim:To implement the odd and even parity checkers using the logic gates and also to generate the odd parity
and even parity numbers using the generators
Apparatus required:
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Sl. No Component Type Quantity
1 Trainer Kit - 1
2 EX-OR IC7486 1
3 NOT gate IC 7404 1
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4 Connecting wires - RequiredTheory:
Parity checking is used for error detection in data transmission.
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Odd parity checkers:It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
odd.
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Even parity checker:It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
even.
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Odd parity generators:It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also
the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bits
which is an odd parity number.
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Even parity generator:It generates an even parity number. The even parity checker circuit is used with the inverted output and
also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5
bits which is an even parity number.
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42 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Truth table:
Input Checker output Generator output
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A B C D D odd even odd even0 0 0 1 1 0 00010 00011
0 0 1 0 1 0 00100 00101
0 0 1 1 0 1 00111 00110
0 1 0 0 1 0 01000 01001
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0 1 0 1 0 1 01011 010100 1 1 0 0 1 01101 01100
0 1 1 1 1 0 01110 01111
1 0 0 0 1 0 10000 10001
1 0 0 1 0 1 10011 10010
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1 0 1 0 0 1 10101 101001 0 1 1 1 0 10110 10111
1 1 0 0 0 1 11001 11000
1 1 0 1 1 0 11010 11011
1 1 1 0 1 0 11100 11101
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1 1 1 1 0 1 11111 11110Procedure:
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1. The circuit is implemented using logic gates.2. The inputs are given as per the truth table.
3. The corresponding outputs are noted.
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4. The theoretical and practical values were verified.
Result:
The odd and even parity checkers are implemented using the logic gates and the odd parity and
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even parity numbers are generated using the corresponding generators.Outcome:
At the completion of an experiment student will able to verify the odd and even parity checker
using logic gates.
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43 Format No.FirstRanker/stud/LM/34/issue:00/revision:001. What is parity bit?
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2. Why parity bit is added to message?
3. What is parity checker?
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4. What is odd parity?5. What is even parity?
6. What are the gates involved for parity generator?
7. List the procedures to convert gray code into binary.
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8. Why weighted code is called as reflective codes?9. What is a sequential code?
10. What is error deducting code?
11. What is ASCII code?
12. What is hamming code?
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13. List the binary weighted code.14. List the binary non weighted code.
15. Write the hamming code equation
16. List the procedures to convert binary code into gray
17. What are the applications of gray code?
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18. What are the applications of Excess- 3 code?Viva ? Voce
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44 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.9: MULTIPLEXER AND DEMULTIPLEXER
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Aim:To design and verify the truth table of a 4X1 multiplexer & 1X4 demultiplexer
Apparatus required:
Sl. No Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. OR gate IC 7432 1
3. NOT gate IC 7404 1
4. AND gate ( three input ) IC 7411 1
5. Connecting wires As required
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Theory:
Multiplexing means transmitting a large number of information units over a smaller number of channels or
lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input
lines and directs it to a single output line. The selection of particular input line is controlled by a set of
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selection lines. Normally, there are 2n
input lines and n selection lines whose bit combinations determines
which input is selected. A multiplexer is called a data selector, since it selects one of many inputs and
steers the binary information to the output line. A Strobe is also provided to allow the designer to disable all
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output data until a specified time. Then, by allowing the STROBE to go low, the proper lead can beselected. This feature is very useful where data might be changing the same time DATA SELECT leads
change. It is a very useful Medium Scale Integration (MSI) function and has a multitude of applications. It is
used for connecting two or more sources to a single destination among the computer units and it is useful
for constructing a common bus system. A decoder with an enable input can function as a demultiplexer. A
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Demultiplexer is a circuit that receives information on a single line and transmits this information on one of2
n
possible output lines. The selection of specific output line is controlled by the bit values of n selection
lines. The decoder and demultiplexer operations are obtained from the same circuit; a decoder with an
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enable input is referred to as a decoder / de-multiplexer. The Strobe lead can be used to active or de-active the entire IC, allowing time for the address lines to change the information is fed to the output.
Demultiplexers are useful anytime information from one source must be fed several places.
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45 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
4 X 1 MULTIPLEXER
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CIRCUIT DIAGRAM:
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46 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1X4 DEMULTIPLEXER--- Content provided by FirstRanker.com ---
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CIRCUIT DIAGRAM:--- Content provided by FirstRanker.com ---
47 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Result:
The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth tables
were verified.
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Outcome:At the completion of an experiment student will able to design the multiplexer and the
demultiplexer
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1. What is multiplexer?
2. What is demultiplexer?
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3. What are the advantages of multiplexer?4. What are the advantages of demultiplexer?
5. What is select signal?
6. How to choose select signal in multiplexer?
7. How to choose select signal in demultiplexer?
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8. Write the formula used in select signal.9. What is the difference between the multiplexer and demultiplexer?
10. What is the application of multiplexer?
11. What is the application of demultiplexer?
12. Draw the truth table of multiplexer.
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13. Draw the truth table of demultiplexer.14. How many select signals are needed in 8*1 multiplexer?
15. How many select signals are needed in 8*1 demultiplexer?
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Viva ? Voce
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48 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
EXP NO: 11 SHIFT REGISTER
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Aim:To design and implement the various shift register
Apparatus required:
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Sl. No Name of the Apparatus Range Quantity
1. D flip flop IC 7474 2
2. OR gate IC 7432 1
3. IC Trainer kit 1
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5. Connecting wires As requiredTheory:
A register is capable of shifting its binary information in one or both directions is
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known as shift register. The logical configuration of shift register consist of a D-Flip flopcascaded with output of one flip flop connected to input of next flip flop. All flip flops receive
common clock pulses which causes the shift in the output of the flip flop.The simplest possible
shift register is one that uses only flip flop. The output of a given flip flop is connected to the
input of next flip flop of the register. Each clock pulse shifts the content of register one bit position
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to right.PIN Diagram:
Logic Diagram:
SERIAL IN SERIAL OUT
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49 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Truth Table:
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CLK Serial in Serial out
1 1 0
2 0 0
3 0 0
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4 1 15 X 0
6 X 0
7 X 1
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Logic Diagram:
Serial in parallel out:
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Truth Table:
CLK DATA
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OUTPUTQ
A
Q
B
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QC
Q
D
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1 1 1 0 0 02 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1
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Parallel in Serial Out:
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50 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
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3 0 0 0 0 1Truth Table:
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Parallel in Parallel Out:
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PARALLEL IN PARALLEL OUT:
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Truth Table:
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Procedure:
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1. Connections are given as per circuit diagram2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
Result:
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Thus the implementation of shift registers using flip flops was completed successfully.
Outcome:
At the completion of an experiment student will able to design the various types of shift register.
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CLK
DATA INPUT OUTPUT
D
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A DB D
C D
D Q
A Q
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B QC Q
D
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
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51 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.12: SYNCHRONOUS UP/DOWN COUNTERAim:
To design and implement 3 bit synchronous up/down counter
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Apparatus required:
S.No Name of the Apparatus Range Quantity
1. JK Flip Flop IC 7474 2
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2. OR gate IC 7432 13. NOT gate IC 7404 1
4. AND gate ( three input ) IC 7411 1
5 XOR gate IC 7486 1
6 IC Trainer Kit 1
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7. Connecting wires As requiredTheory:
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A counter is a register capable of counting number of clock pulse arriving at its clock input.Counter represents the number of clock pulses arrived. An up/down counter is one that is capable of
progressing in increasing order or decreasing order through a certain sequence. An up/down counter
is also called bidirectional counter. Usually up/down operation of the counter is controlled by up/down
signal. When this signal is high counter goes through up sequence and when up/down signal is low counter
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follows reverse sequence.K map:
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52 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Q Q
t+1 J K
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0 0 0 X0 1 1 X
1 0 X 1
1 1 X 0
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State Diagram:--- Content provided by FirstRanker.com ---
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Characteristic Table:
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Logic Diagram:
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53 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Input
Up/Down
Present
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StateQ
A
Q
B
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QC
Next State
Q
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A+1Q
B+1
Q
C+1
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AJ
A
K
A
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B
J
B
K
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BC
J
C
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KC
0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
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0 1 1 0 1 0 1 X 0 X 1 1 X0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
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0 0 0 1 0 0 0 0 X 0 X X 11 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
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1 1 0 0 1 0 1 X 0 0 X 1 X1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1
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Truth Table:
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Procedure:
1. Connections are given as per circuit diagram.
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2. Logical inputs are given as per circuit diagram.3. Observe the output and verify the truth table.
Result:
Thus the 3-bit synchronous up/down counters was implemented successfully.
Outcome:
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At the completion of an experiment student will able to design the synchronous up/down counter.
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54 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Expt.No.12:SIMULATION OF COMBINATIONAL CIRCUITS USING HDL
Aim:
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To write a verilog code for half adder, full adder and multiplexer
Tools Required:
Xilinx 9.2
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Program:
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Simulation wave for half adder
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FirstRanker.com - FirstRanker's Choice
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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
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CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
Name : _______________________________________
--- Content provided by FirstRanker.com ---
Register No : _______________________________________Section : _______________________________________
--- Content provided by FirstRanker.com ---
LABORATORY MANUAL
--- Content provided by FirstRanker.com ---
2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
training.
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? To provide competent technical manpower capable of meeting requirements of the industry
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? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
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heart and soulDEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and ElectronicsEngineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
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? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
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professional ethical code.? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
--- Content provided by FirstRanker.com ---
VISION
MISSION
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VISIONMISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
1. Fundamentals
--- Content provided by FirstRanker.com ---
To provide students with a solid foundation in mathematics, science and fundamentals ofengineering enabling them to solve complex problems in order to develop real time applications.
2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
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technologies.3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
--- Content provided by FirstRanker.com ---
development of society.4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
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professional ethics at all strategies.5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM OUTCOMES (POs)a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
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c. Graduates will be able to design and conduct experiments, analyze and interpret data.d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
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g. Graduates will demonstrate knowledge of professional and ethical responsibilities.h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
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k. Graduate who can participate and succeed in competitive examinations.--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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SYLLABUS
Objectives:
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The student should be made to:? Understand the various logic gates.
? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
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? Learn to use HDLList of experiments:
1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
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3. Design and implementation of combinational circuits using MSI devices:a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
c. Magnitude Comparator
d. Application using multiplexers
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4. Design and implementation of sequential circuits:a. Shift ?registers
b. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
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Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
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? Design the different functional units in a digital computer system.? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Content
Sl.No. Name of the Experiment Page No.
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1.Verification of Boolean Theorems using Digital Logic Gates
2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
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3.
Implementation of half adder and full adder
4.
Implementation of half subtractor and full subtractor
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5.Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
6.
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Design and Implementation of Parity Generator / Checker using Basic Gates and MSIDevices
7.
Design and Implementation of Magnitude Comparator.
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8.Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
Design and Implementation of Shift Registers.
10.
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Design and Implementation of Synchronous and Asynchronous Counters.11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
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12.Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.1: STUDY OF BASIC GATES
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Aim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. NAND gate IC 7400 1
6. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
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AND gateThe AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
low.
OR gate
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The OR gate performs a logical addition commonly known as OR function. The output ishigh when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
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NAND gateThe NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
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output is low when one or both inputs are high.EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
EXOR Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
th
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pin is grounded and 14th
pin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
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Result:
The truth tables of all the basic logic gates were verified.
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Outcome:At the completion of an experiment student will able to verify the truth
table of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
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3. How many gates presented in IC 7408?4. What is IC?
5. What are the applications of gates?
6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
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8. Write the truth table of NOT gate.9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
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13. What are types of linear integrated circuit?14. What is meant by etching?
15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.2:
VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gates
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. NAND gate IC 7400 1
6. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
BASIC Boolean Laws
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1. Commutative Law
The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
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2. A.B=B.A2. Associative Law
The binary operator OR, AND is said to be associative if,
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1. A+(B+C) = (A+B)+C2. A.(B.C) = (A.B).C
3. Distributive Law
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The binary operator OR, AND is said to be distributive if,1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
4. Absorption Law
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1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
1. A+A = A
2. A.A = A
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6. Complementary Law
1. A+A' = 1
2. A.A' = 0
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7. De Morgan ?s Theorem
1. The complement of the sum is equal to the sum of the product of the individual
complements.
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A+B = A.B2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design1. Absorption Law
A+AB = A
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2. Involution (or) Double complement Law
A = A
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3. Idempotent Law
1. A+A = A
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2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:004. Demorgan ?s Law
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A+B = A.B
5. Distributive Law
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A+(B.C) = (A+B).(A+C)Procedure:
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
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cc.
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
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Result:
Thus the above stated Boolean laws are verified.
Outcome:
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At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?2. What is associative law?
3. What is mean by compliment gate?
4. Explain the basic laws in digital electronics
5. What is double complement?
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Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
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To design and verify the truth table of the Half Adder & Full Adder circuitsApparatus required:
S. No. Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
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6. Connecting wires As requiredTheory:
The most basic arithmetic operation is the addition of two binary digits. There are four
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possible elementary operations, namely,0 + 0 = 0
0 + 1 = 1
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1 + 0 = 1
1 + 1 = 0 (with 1 as carry)
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The first three operations produce a sum of whose length is one digit, but when the last operation isperformed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
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designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.Full adder:
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
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with two half adders and one OR gate.From the truth table, the expression for sum and carry bits of the output can be obtained as,
SUM = A?B?C + A?BC? + AB?C? + ABC
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CARRY = A?BC + AB?C + ABC? +ABC16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half Adder
Truth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
S = A B
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Carry, C = A . BCircuit diagram:
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Full adder
Truth table:
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Sl.No. Input OutputA B C S C
1. 0 0 0 0 0
2. 0 0 1 1 0
3. 0 1 0 1 0
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4. 0 1 1 0 15. 1 0 0 1 0
6. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input Output
A B S C
1. 0 0 0 0
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2. 0 1 1 03. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Sum:--- Content provided by FirstRanker.com ---
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B CCarry:
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CARRY = AB + AC + BC
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Logic Diagram:18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections are given as per the circuit diagrams.
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2. For all the IC?s 7th
pin is grounded and 14
th
pin is given +5 V supply.
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3. Apply the inputs and verify the truth table for the half adder and full adder circuits.Result:
The design of the half adder and full adder circuits was done and their truth tables were verified.
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Outcome:At the completion of an experiment student will able to design the half adder circuit and the
full adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTORAim:
To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. EX-OR gate IC 7486 1
6. Connecting wires As required
Theory:
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The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bitis subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
subtrahend bit, hence 1 is borrowed.
Half subtractor:
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A combinational circuit which performs the subtraction of two bits is called half subtractor. The inputvariables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
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three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can beimplemented with two half subtractors and one OR gate.
From the truth table the expression for difference and borrow bits of the output can be obtained
as,
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Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
Borrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half subtractor
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Truth table:
Sl.No. Input Output
A B Difference Borrow
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1. 0 0 0 02. 0 1 1 1
3. 1 0 1 0
4. 1 1 0 0
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From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A B
Borrow, BORR = A?. B
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Logic diagram:
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2. Full subtractor
Truth table:
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Sl.No.
Input Output
A B C Difference Borrow
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1. 0 0 0 0 02. 0 0 1 1 1
3. 0 1 0 1 1
4. 0 1 1 0 1
5. 1 0 0 1 0
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6. 1 0 1 0 07. 1 1 0 0 0
8. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
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Borrow--- Content provided by FirstRanker.com ---
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Borrow = A?B + A?C + BC
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Circuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
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Aim:To design and implement 4-bit adder and subtractor using IC 7483
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. IC IC 7483 1
3. NOT gate IC 7404 1
4. EX-OR gate IC 7486 1
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5. Connecting wires As requiredTheory:
4 BIT Binary adder:
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A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected to
the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
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carries are connected in chain through full adder. The input carry to the adder is C0
and it ripples through
the full adder to the output carry C
4
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.4 BIT Binary subtractor:
The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
?B? and the corresponding input of full adder. The input carry C
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0must be equal to 1 when performing
subtraction.
4 BIT Binary adder / subtractor:
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The addition and subtraction operation can be combined into one circuit with one common binaryadder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
becomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PIN Diagram for IC 7483:
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Logic Diagram: 4-Bit Binary Diagram:Logic diagram: 4-Bit Binary Subtractor:
4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:
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Procedure:
1. Connections are given as per the circuit diagrams.
2. Logical inputs were given as per circuit diagram.
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3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor..
Result:
The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
verified.
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Outcome:At the completion of an experiment student will able to design 4-bit binary adder and subtractor
Input Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
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1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 01 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
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1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 11 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
1. What is expression for difference and borrow?
2. Write the truth table for half adder.
3. Write the truth table for full adder.
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4. Write the truth table for half subtrator.5. Write the truth table for full subtrator.
6. Draw the logic diagram of full subtrator.
7. What is adder?
8. List out the application of adders.
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9. Draw the full adder using two half adder circuits.10. What is combinational circuit?
11. What is different between combinational and sequential circuit?
12. What are the gates involved for binary adder?
13. List the properties of Ex-Nor gate?
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14. What is expression for sum and carry?--- Content provided by FirstRanker.com ---
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.6: MAGNITUDE COMPARATORAim:
To design, construct and study the performance of 2 bit magnitude comparator
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. Magnitude comparator IC 7485 26. EX-OR gate IC 7486 1
7. Connecting wires As required
Theory:
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The comparison of two numbers is an operator that determines one number is greater than, less
than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
three binary variables that indicate whether A>B, A=B (or) A
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Truth table:--- Content provided by FirstRanker.com ---
27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Logic Diagram:
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Pin Diagram for IC 7485:
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
8 Bit Magnitude Comparator:
Truth table:
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Procedure:
1. Connections are given as per circuit diagram.
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2. Logical inputs are given as per circuit diagram.3. Observe the output and verify the truth table.
Result:
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Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.Outcome:
At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
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comparator using logic gates.--- Content provided by FirstRanker.com ---
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A B A>B A=B A0 0 0 0
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0 0 0 00 0 0 0
0 0 0 0
0 1 0
0 0 0 1
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0 0 0 10 0 0 0
0 0 0 0
1 0 0
0 0 0 0
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0 0 0 00 0 0 1
0 0 0 1
0 0 1
Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is magnitude comparator?2. What is most significant bit?
3. Explain operation of AND gate.
4. Explain truth table of a comparator.
5. Explain magnitude comparator7485 IC.
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6. What is 8-bit input Magnitude Comparator?7. What is IC?
8. Explain the k-map simplification of A>B.
9. Explain the k-map simplification of A=B.
10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
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12. What is the truth table of 1-bit magnitude comparator?13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION
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31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Aim:To design, construct and study the performance of 4-bit different code converters
(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
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(iv) Excess-3 to BCD code converterApparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
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6. EX-OR gate IC 7486 17. Connecting wires As required
Theory:
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The availability of large variety of codes for the same discrete elements of information results inthe use of different codes by different systems. A conversion circuit must be inserted between the two
systems if each uses different codes for same information. Thus, code converter is a circuit that makes the
two systems compatible even though each uses different binary code. The bit combination assigned to
binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
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and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a
circuit that makes the two systems compatible even though each uses a different binary code. To convert
from binary code to Excess-3 code, the input lines must supply the bit combination of elements as
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specified by code and the output lines generate the corresponding bit combination of code. Each one of thefour maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are
various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is
C+D has been used to implement partially each of three outputs.
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Logic diagram:
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32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(i) Binary to gray code converterLogic Diagram:
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K map for G3:G3 = B3
K map for G2:
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K map for G1:
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33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for G0:
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Truth table:
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00
0
0
0
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00
0
1
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
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01
1
1
1
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00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
0
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01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
0
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
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10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
0
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00
0
0
0
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01
1
1
1
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11
1
1
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00
0
0
1
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11
1
1
1
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11
0
0
0
--- Content provided by FirstRanker.com ---
00
0
1
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11
1
0
0
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00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
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11
0
0
1
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10
0
1
1
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00
1
1
0
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(ii) Gray to binary code converter
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34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Logic Diagram:
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K map for B3:
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B3=G3
K map for B2:
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00G3 G2 G1 G0 B3 B2 B1 B0
0
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00
0
0
0
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00
1
1
1
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11
1
1
1
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0
0
0
0
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11
1
1
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
00
0
0
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11
1
1
0
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00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
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01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
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10
0
1
1
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00
0
0
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00
0
0
0
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11
1
1
1
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11
1
0
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00
0
1
1
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11
0
0
0
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01
1
1
1
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0
0
1
1
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00
1
1
0
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01
1
0
0
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11
0
1
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01
0
1
0
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10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
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K map for B1:K map for B0:
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Truth table:
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
(iii) BCD to excess-3 code converter
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Logic Diagram:K map for E3:
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E3 = B3 + B2 (B0 + B1)
K map for E2:
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00K map for E1:
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K map for E0:
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Truth table:
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(iv) Excess-3 to
B3 B2 B1 B0 G3 G2 G1 G0
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0
0
0
0
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00
0
0
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
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11
0
0
1
--- Content provided by FirstRanker.com ---
10
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
1
x
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xx
x
x
x
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0
1
1
1
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10
0
0
0
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1x
x
x
x
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xx
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
x
x
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xx
x
x
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10
1
0
1
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01
0
1
0
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xx
x
x
x
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x38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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BCD code converter
Logic Diagram:
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K map for A:
A = X1 X2 + X3 X4 X1
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K map for B:
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39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00K map for C:
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K map for D:
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Truth table:
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B3 B2 B1 B0 G3 G2 G1 G0
0
0
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00
0
1
1
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11
1
0
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11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
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10
0
1
1
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00
1
1
0
--- Content provided by FirstRanker.com ---
1
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
00
0
0
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00
0
0
0
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
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10
0
0
--- Content provided by FirstRanker.com ---
01
1
0
0
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11
0
0
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01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
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40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Procedure:
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1. Connections were given as per circuit diagram.2. Logical inputs were given as per truth table
3. Observe the logical output and verify with the truth tables.
Result:
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Thus the code converters were designed and verified using the corresponding truth table.Outcome:
At the completion of an experiment student will able to design the binary to gray converter.
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1. What is binary code?
2. What is gray code?
3. What are the advantages of gray code?
4. What is unit distance code?
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5. What is sequential code?6. How to convert binary to gray code?
7. How to convert gray to binary code?
8. What is reflective code?
9. What are the advantages of EX ? 3 code?
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10. Which code is used to arithmetic operation in digital circuits?11. Explain the operation of EX ? OR.
12. What is K ? Map?
13. Draw the truth table of EX- OR gate.
14. What is SOP?
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15. What is POS?16. What is minterm?
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Viva ? Voce
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41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.8: PARITY GENERATORS AND CHECKERSAim:
To implement the odd and even parity checkers using the logic gates and also to generate the odd parity
and even parity numbers using the generators
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Apparatus required:
Sl. No Component Type Quantity
1 Trainer Kit - 1
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2 EX-OR IC7486 13 NOT gate IC 7404 1
4 Connecting wires - Required
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Theory:Parity checking is used for error detection in data transmission.
Odd parity checkers:
It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
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odd.Even parity checker:
It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
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even.Odd parity generators:
It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also
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the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bitswhich is an odd parity number.
Even parity generator:
It generates an even parity number. The even parity checker circuit is used with the inverted output and
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also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5bits which is an even parity number.
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42 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Truth table:
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Input Checker output Generator output
A B C D D odd even odd even
0 0 0 1 1 0 00010 00011
0 0 1 0 1 0 00100 00101
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0 0 1 1 0 1 00111 001100 1 0 0 1 0 01000 01001
0 1 0 1 0 1 01011 01010
0 1 1 0 0 1 01101 01100
0 1 1 1 1 0 01110 01111
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1 0 0 0 1 0 10000 100011 0 0 1 0 1 10011 10010
1 0 1 0 0 1 10101 10100
1 0 1 1 1 0 10110 10111
1 1 0 0 0 1 11001 11000
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1 1 0 1 1 0 11010 110111 1 1 0 1 0 11100 11101
1 1 1 1 0 1 11111 11110
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Procedure:
1. The circuit is implemented using logic gates.
2. The inputs are given as per the truth table.
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3. The corresponding outputs are noted.
4. The theoretical and practical values were verified.
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Result:The odd and even parity checkers are implemented using the logic gates and the odd parity and
even parity numbers are generated using the corresponding generators.
Outcome:
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At the completion of an experiment student will able to verify the odd and even parity checkerusing logic gates.
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43 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is parity bit?
2. Why parity bit is added to message?
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3. What is parity checker?4. What is odd parity?
5. What is even parity?
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6. What are the gates involved for parity generator?7. List the procedures to convert gray code into binary.
8. Why weighted code is called as reflective codes?
9. What is a sequential code?
10. What is error deducting code?
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11. What is ASCII code?12. What is hamming code?
13. List the binary weighted code.
14. List the binary non weighted code.
15. Write the hamming code equation
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16. List the procedures to convert binary code into gray17. What are the applications of gray code?
18. What are the applications of Excess- 3 code?
Viva ? Voce
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44 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.9: MULTIPLEXER AND DEMULTIPLEXERAim:
To design and verify the truth table of a 4X1 multiplexer & 1X4 demultiplexer
Apparatus required:
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Sl. No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. OR gate IC 7432 1
3. NOT gate IC 7404 1
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4. AND gate ( three input ) IC 7411 15. Connecting wires As required
Theory:
Multiplexing means transmitting a large number of information units over a smaller number of channels or
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lines. A digital multiplexer is a combinational circuit that selects binary information from one of many inputlines and directs it to a single output line. The selection of particular input line is controlled by a set of
selection lines. Normally, there are 2
n
input lines and n selection lines whose bit combinations determines
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which input is selected. A multiplexer is called a data selector, since it selects one of many inputs andsteers the binary information to the output line. A Strobe is also provided to allow the designer to disable all
output data until a specified time. Then, by allowing the STROBE to go low, the proper lead can be
selected. This feature is very useful where data might be changing the same time DATA SELECT leads
change. It is a very useful Medium Scale Integration (MSI) function and has a multitude of applications. It is
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used for connecting two or more sources to a single destination among the computer units and it is usefulfor constructing a common bus system. A decoder with an enable input can function as a demultiplexer. A
Demultiplexer is a circuit that receives information on a single line and transmits this information on one of
2
n
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possible output lines. The selection of specific output line is controlled by the bit values of n selectionlines. The decoder and demultiplexer operations are obtained from the same circuit; a decoder with an
enable input is referred to as a decoder / de-multiplexer. The Strobe lead can be used to active or de-
active the entire IC, allowing time for the address lines to change the information is fed to the output.
Demultiplexers are useful anytime information from one source must be fed several places.
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45 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4 X 1 MULTIPLEXER
CIRCUIT DIAGRAM:
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46 Format No.FirstRanker/stud/LM/34/issue:00/revision:001X4 DEMULTIPLEXER
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CIRCUIT DIAGRAM:
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47 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Result:
The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth tables
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were verified.Outcome:
At the completion of an experiment student will able to design the multiplexer and the
demultiplexer
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1. What is multiplexer?2. What is demultiplexer?
3. What are the advantages of multiplexer?
4. What are the advantages of demultiplexer?
5. What is select signal?
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6. How to choose select signal in multiplexer?7. How to choose select signal in demultiplexer?
8. Write the formula used in select signal.
9. What is the difference between the multiplexer and demultiplexer?
10. What is the application of multiplexer?
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11. What is the application of demultiplexer?12. Draw the truth table of multiplexer.
13. Draw the truth table of demultiplexer.
14. How many select signals are needed in 8*1 multiplexer?
15. How many select signals are needed in 8*1 demultiplexer?
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Viva ? Voce
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48 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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EXP NO: 11 SHIFT REGISTERAim:
To design and implement the various shift register
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Apparatus required:
Sl. No Name of the Apparatus Range Quantity
1. D flip flop IC 7474 2
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2. OR gate IC 7432 13. IC Trainer kit 1
5. Connecting wires As required
Theory:
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A register is capable of shifting its binary information in one or both directions is
known as shift register. The logical configuration of shift register consist of a D-Flip flop
cascaded with output of one flip flop connected to input of next flip flop. All flip flops receive
common clock pulses which causes the shift in the output of the flip flop.The simplest possible
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shift register is one that uses only flip flop. The output of a given flip flop is connected to theinput of next flip flop of the register. Each clock pulse shifts the content of register one bit position
to right.
PIN Diagram:
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Logic Diagram:SERIAL IN SERIAL OUT
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49 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth Table:
CLK Serial in Serial out
1 1 0
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2 0 03 0 0
4 1 1
5 X 0
6 X 0
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7 X 1Logic Diagram:
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Serial in parallel out:Truth Table:
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CLK DATA
OUTPUT
Q
A
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QB
Q
C
Q
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D1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
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4 1 1 0 0 1Parallel in Serial Out:
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50 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
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1 0 0 0 0 02 0 0 0 0 0
3 0 0 0 0 1
Truth Table:
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Parallel in Parallel Out:
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PARALLEL IN PARALLEL OUT:
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Truth Table:
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Procedure:1. Connections are given as per circuit diagram
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
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Result:
Thus the implementation of shift registers using flip flops was completed successfully.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to design the various types of shift register.
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CLK
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DATA INPUT OUTPUTD
A D
B D
C D
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D QA Q
B Q
C Q
D
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1 1 0 0 1 1 0 0 12 1 0 1 0 1 0 1 0
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51 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.12: SYNCHRONOUS UP/DOWN COUNTER
Aim:
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To design and implement 3 bit synchronous up/down counter
Apparatus required:
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S.No Name of the Apparatus Range Quantity1. JK Flip Flop IC 7474 2
2. OR gate IC 7432 1
3. NOT gate IC 7404 1
4. AND gate ( three input ) IC 7411 1
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5 XOR gate IC 7486 16 IC Trainer Kit 1
7. Connecting wires As required
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Theory:A counter is a register capable of counting number of clock pulse arriving at its clock input.
Counter represents the number of clock pulses arrived. An up/down counter is one that is capable of
progressing in increasing order or decreasing order through a certain sequence. An up/down counter
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is also called bidirectional counter. Usually up/down operation of the counter is controlled by up/downsignal. When this signal is high counter goes through up sequence and when up/down signal is low counter
follows reverse sequence.
K map:
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52 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
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1 1 X 0State Diagram:
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Characteristic Table:--- Content provided by FirstRanker.com ---
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Logic Diagram:--- Content provided by FirstRanker.com ---
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53 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Input
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Up/DownPresent
State
Q
A
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QB
Q
C
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Next StateQ
A+1
Q
B+1
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QC+1
A
J
A
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KA
B
J
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BK
B
C
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JC
K
C
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0 0 0 0 1 1 1 1 X 1 X 1 X0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
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0 0 1 1 0 1 0 0 X X 0 X 10 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
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1 0 1 0 0 1 1 0 X X 0 1 X1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
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1 1 1 1 0 0 0 X 1 X 1 X 1Truth Table:
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Procedure:
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1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
Result:
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Thus the 3-bit synchronous up/down counters was implemented successfully.Outcome:
At the completion of an experiment student will able to design the synchronous up/down counter.
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54 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.12:
SIMULATION OF COMBINATIONAL CIRCUITS USING HDL
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Aim:
To write a verilog code for half adder, full adder and multiplexer
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Tools Required:Xilinx 9.2
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Program:--- Content provided by FirstRanker.com ---
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Simulation wave for half adder
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55 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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MULTIPLEXER:
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Procedure:1. Write and draw the Digital logic system.
2. Write the Verilog code for above system.
3. Enter the Verilog code in Xilinx software.
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4. Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and verify theoutput waveform as obtained.
5. Implement the above code in Spartan III using FPGA kit.
Result:
--- Content provided by FirstRanker.com ---
Thus the verilog code for half adder, full adder and multiplexer were simulated and verified
successfully.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to be known the verilog code for half adder,
full adder and multiplexer.
FirstRanker.com - FirstRanker's Choice
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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
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III SEMESTER - R 2017CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________Register No : _______________________________________
Section : _______________________________________
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LABORATORY MANUAL
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2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
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training.--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
--- Content provided by FirstRanker.com ---
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag onheart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
--- Content provided by FirstRanker.com ---
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering toprofessional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
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VISION
MISSION
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VISION
MISSION
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3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
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1. FundamentalsTo provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
2. Core Competence
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To train the students to meet the needs of core industry with an attitude of learning newtechnologies.
3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
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enable them to find solutions to problems in industry and research that contributes to the overalldevelopment of society.
4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
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team and stand as a good decision maker to manage any constraint environment with goodprofessional ethics at all strategies.
5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
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commitment and lifelong learning needed for successful professional career.--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM OUTCOMES (POs)
a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
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b. Graduates will be able to identify, formulate and solve electrical engineering problems.c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
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analyze problems.g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
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j. Graduates will develop confidence for self-education and ability for lifelong learning.k. Graduate who can participate and succeed in competitive examinations.
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CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00SYLLABUS
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Objectives:The student should be made to:
? Understand the various logic gates.
? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
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? Be exposed to sequential circuits? Learn to use HDL
List of experiments:
1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
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functions, code converters.3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
c. Magnitude Comparator
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d. Application using multiplexers4. Design and implementation of sequential circuits:
a. Shift ?registers
b. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
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6. Design and implementation of a simple digital system (Mini Project).Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
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? Analyze a given digital circuit ? combinational and sequential.? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Content
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Sl.No. Name of the Experiment Page No.1.
Verification of Boolean Theorems using Digital Logic Gates
2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
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Functions, Code Converters3.
Implementation of half adder and full adder
4.
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Implementation of half subtractor and full subtractor5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
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6.Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
7.
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Design and Implementation of Magnitude Comparator.8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
Design and Implementation of Shift Registers.
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10.Design and Implementation of Synchronous and Asynchronous Counters.
11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
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12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.1: STUDY OF BASIC GATESAim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
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8. Connecting wires As requiredTheory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
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universal gates. Basic gates form these gates.AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
low.
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OR gateThe OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
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called an inverter. The output is high when the input is low. The output is low when the input is high.NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
NOR gate
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The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. Theoutput is low when one or both inputs are high.
EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
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OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NAND Gate symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
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thpin is grounded and 14
th
pin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
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Result:
The truth tables of all the basic logic gates were verified.
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Outcome:
At the completion of an experiment student will able to verify the truth
table of all basic gates
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1. List out the basic gate.
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2. Mention the universal gate.3. How many gates presented in IC 7408?
4. What is IC?
5. What are the applications of gates?
6. Write the truth table of AND gate.
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7. Write the truth table of OR gate.8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
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12. What are the classifications of IC?13. What are types of linear integrated circuit?
14. What is meant by etching?
15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
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Viva ? Voce--- Content provided by FirstRanker.com ---
12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.2:
VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
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GATESAim: To verification of Boolean theorems using logic gates
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
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8. Connecting wires As requiredTheory:
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BASIC Boolean Laws1. Commutative Law
The binary operator OR, AND is said to be commutative if,
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1. A+B = B+A2. A.B=B.A
2. Associative Law
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The binary operator OR, AND is said to be associative if,1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
3. Distributive Law
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The binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
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4. Absorption Law1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
1. A+A = A
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2. A.A = A6. Complementary Law
1. A+A' = 1
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2. A.A' = 07. De Morgan ?s Theorem
1. The complement of the sum is equal to the sum of the product of the individual
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complements.A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design
1. Absorption Law
A+AB = A
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2. Involution (or) Double complement Law
A = A
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3. Idempotent Law
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1. A+A = A2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s LawA+B = A.B
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5. Distributive LawA+(B.C) = (A+B).(A+C)
Procedure:
1. Obtain the required IC along with the Digital trainer kit.
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2. Connect zero volts to GND pin and +5 volts to Vcc
.
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
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Result:
Thus the above stated Boolean laws are verified.
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Outcome:At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?
2. What is associative law?
3. What is mean by compliment gate?
4. Explain the basic laws in digital electronics
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5. What is double complement?Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.3: HALF ADDER AND FULL ADDER
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Aim:To design and verify the truth table of the Half Adder & Full Adder circuits
Apparatus required:
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S. No. Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. EX-OR gate IC 7486 16. Connecting wires As required
Theory:
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The most basic arithmetic operation is the addition of two binary digits. There are fourpossible elementary operations, namely,
0 + 0 = 0
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0 + 1 = 11 + 0 = 1
1 + 1 = 0 (with 1 as carry)
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The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
Half adder:
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A combinational circuit which performs the addition of two bits is called half adder. The input variablesdesignate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
Full adder:
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
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three input bits include two significant bits and a previous carry bit. A full adder circuit can be implementedwith two half adders and one OR gate.
From the truth table, the expression for sum and carry bits of the output can be obtained as,
SUM = A?B?C + A?BC? + AB?C? + ABC
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CARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Half Adder
Truth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
S = A B
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Carry, C = A . B
Circuit diagram:
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Full adder
Truth table:
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Sl.No. Input Output
A B C S C
1. 0 0 0 0 0
2. 0 0 1 1 0
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3. 0 1 0 1 04. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
7. 1 1 0 0 1
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8. 1 1 1 1 1Sl.No. Input Output
A B S C
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1. 0 0 0 02. 0 1 1 0
3. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
Carry:
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CARRY = AB + AC + BC
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Logic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Procedure:
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1. Connections are given as per the circuit diagrams.2. For all the IC?s 7
th
pin is grounded and 14
th
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pin is given +5 V supply.3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
Result:
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The design of the half adder and full adder circuits was done and their truth tables were verified.Outcome:
At the completion of an experiment student will able to design the half adder circuit and the
full adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
Aim:
To design and verify the truth table of the half subtractor & full subtractor circuits
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
subtrahend bit, hence 1 is borrowed.
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Half subtractor:A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
Full subtractor:
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A combinational circuit which performs the subtraction of three input bits is called full subtractor. Thethree input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
From the truth table the expression for difference and borrow bits of the output can be obtained
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as,Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
Borrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half subtractorTruth table:
Sl.No. Input Output
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A B Difference Borrow1. 0 0 0 0
2. 0 1 1 1
3. 1 0 1 0
4. 1 1 0 0
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From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A B
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Borrow, BORR = A?. BLogic diagram:
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2. Full subtractor
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Truth table:Sl.No.
Input Output
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A B C Difference Borrow1. 0 0 0 0 0
2. 0 0 1 1 1
3. 0 1 0 1 1
4. 0 1 1 0 1
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5. 1 0 0 1 06. 1 0 1 0 0
7. 1 1 0 0 0
8. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
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Borrow
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Borrow = A?B + A?C + BC
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Circuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
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Aim:
To design and implement 4-bit adder and subtractor using IC 7483
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. IC IC 7483 1
3. NOT gate IC 7404 1
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4. EX-OR gate IC 7486 15. Connecting wires As required
Theory:
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4 BIT Binary adder:A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected to
the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
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designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. Thecarries are connected in chain through full adder. The input carry to the adder is C
0
and it ripples through
the full adder to the output carry C
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4.
4 BIT Binary subtractor:
The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
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?B? and the corresponding input of full adder. The input carry C0
must be equal to 1 when performing
subtraction.
4 BIT Binary adder / subtractor:
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The addition and subtraction operation can be combined into one circuit with one common binary
adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
becomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PIN Diagram for IC 7483:
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Logic Diagram: 4-Bit Binary Diagram:
Logic diagram: 4-Bit Binary Subtractor:
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4-Bit Binary Adder /Subtractor:24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:
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Procedure:
1. Connections are given as per the circuit diagrams.
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2. Logical inputs were given as per circuit diagram.3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
.
Result:
The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
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verified.Outcome:
At the completion of an experiment student will able to design 4-bit binary adder and subtractor
Input Data A Input Data B Addition Subtraction
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A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D11 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
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1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 11 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?
2. Write the truth table for half adder.
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3. Write the truth table for full adder.4. Write the truth table for half subtrator.
5. Write the truth table for full subtrator.
6. Draw the logic diagram of full subtrator.
7. What is adder?
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8. List out the application of adders.9. Draw the full adder using two half adder circuits.
10. What is combinational circuit?
11. What is different between combinational and sequential circuit?
12. What are the gates involved for binary adder?
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13. List the properties of Ex-Nor gate?14. What is expression for sum and carry?
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.6: MAGNITUDE COMPARATOR
Aim:
To design, construct and study the performance of 2 bit magnitude comparator
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:The comparison of two numbers is an operator that determines one number is greater than, less
than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
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three binary variables that indicate whether A>B, A=B (or) ATruth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K-map--- Content provided by FirstRanker.com ---
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:Pin Diagram for IC 7485:
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:
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Truth table:--- Content provided by FirstRanker.com ---
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Procedure:
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1. Connections are given as per circuit diagram.2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
Result:
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Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
Outcome:
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At the completion of an experiment student will able to design the 2-bit and 8-bit magnitudecomparator using logic gates.
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A B A>B A=B A0 0 0 00 0 0 0
0 0 0 0
0 0 0 0
0 1 0
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0 0 0 10 0 0 1
0 0 0 0
0 0 0 0
1 0 0
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0 0 0 00 0 0 0
0 0 0 1
0 0 0 1
0 0 1
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Viva ? Voce--- Content provided by FirstRanker.com ---
30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
1. What is magnitude comparator?
2. What is most significant bit?
3. Explain operation of AND gate.
4. Explain truth table of a comparator.
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5. Explain magnitude comparator7485 IC.6. What is 8-bit input Magnitude Comparator?
7. What is IC?
8. Explain the k-map simplification of A>B.
9. Explain the k-map simplification of A=B.
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10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.12. What is the truth table of 1-bit magnitude comparator?
13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION
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31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Aim:
To design, construct and study the performance of 4-bit different code converters
(i) Binary to gray code converter
(ii) Gray to binary code converter
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(iii) BCD to excess-3 code converter(iv) Excess-3 to BCD code converter
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. Magnitude comparator IC 7485 26. EX-OR gate IC 7486 1
7. Connecting wires As required
Theory:
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The availability of large variety of codes for the same discrete elements of information results in
the use of different codes by different systems. A conversion circuit must be inserted between the two
systems if each uses different codes for same information. Thus, code converter is a circuit that makes the
two systems compatible even though each uses different binary code. The bit combination assigned to
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binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputsand four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a
circuit that makes the two systems compatible even though each uses a different binary code. To convert
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from binary code to Excess-3 code, the input lines must supply the bit combination of elements asspecified by code and the output lines generate the corresponding bit combination of code. Each one of the
four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are
various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is
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C+D has been used to implement partially each of three outputs.Logic diagram:
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32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(i) Binary to gray code converter
Logic Diagram:
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K map for G3:
G3 = B3
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K map for G2:--- Content provided by FirstRanker.com ---
K map for G1:
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33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for G0:
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Truth table:
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0
0
0
0
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00
0
0
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
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11
0
0
1
--- Content provided by FirstRanker.com ---
10
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
0
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
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0--- Content provided by FirstRanker.com ---
(ii) Gray to binary code converter
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34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Logic Diagram:
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K map for B3:
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B3=G3
K map for B2:
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
G3 G2 G1 G0 B3 B2 B1 B0
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00
0
0
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
0
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
K map for B1:
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K map for B0:Truth table:
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
(iii) BCD to excess-3 code converter
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Logic Diagram:
K map for E3:
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E3 = B3 + B2 (B0 + B1)
K map for E2:
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
K map for E1:
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K map for E0:
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Truth table:--- Content provided by FirstRanker.com ---
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(iv) Excess-3 to
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B3 B2 B1 B0 G3 G2 G1 G00
0
0
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00
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
0
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
xx
x
x
x
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x0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
01
x
x
x
--- Content provided by FirstRanker.com ---
xx
x
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
x
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xx
x
x
x
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1
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
0x
x
x
x
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xx
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38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00BCD code converter
Logic Diagram:
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K map for A:
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A = X1 X2 + X3 X4 X1K map for B:
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39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
K map for C:
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K map for D:
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Truth table:
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B3 B2 B1 B0 G3 G2 G1 G0
0
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00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
1
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
01
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
01
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
0
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
1--- Content provided by FirstRanker.com ---
40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Procedure:1. Connections were given as per circuit diagram.
2. Logical inputs were given as per truth table
3. Observe the logical output and verify with the truth tables.
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Result:Thus the code converters were designed and verified using the corresponding truth table.
Outcome:
At the completion of an experiment student will able to design the binary to gray converter.
--- Content provided by FirstRanker.com ---
1. What is binary code?
2. What is gray code?
3. What are the advantages of gray code?
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4. What is unit distance code?5. What is sequential code?
6. How to convert binary to gray code?
7. How to convert gray to binary code?
8. What is reflective code?
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9. What are the advantages of EX ? 3 code?10. Which code is used to arithmetic operation in digital circuits?
11. Explain the operation of EX ? OR.
12. What is K ? Map?
13. Draw the truth table of EX- OR gate.
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14. What is SOP?15. What is POS?
16. What is minterm?
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Viva ? Voce
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41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.8: PARITY GENERATORS AND CHECKERS
Aim:
To implement the odd and even parity checkers using the logic gates and also to generate the odd parity
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and even parity numbers using the generatorsApparatus required:
Sl. No Component Type Quantity
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1 Trainer Kit - 12 EX-OR IC7486 1
3 NOT gate IC 7404 1
4 Connecting wires - Required
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Theory:
Parity checking is used for error detection in data transmission.
Odd parity checkers:
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It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s isodd.
Even parity checker:
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It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s iseven.
Odd parity generators:
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It generates an odd parity number. The odd parity checker circuit is used with the inverted output and alsothe input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bits
which is an odd parity number.
Even parity generator:
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It generates an even parity number. The even parity checker circuit is used with the inverted output andalso the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5
bits which is an even parity number.
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42 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:Input Checker output Generator output
A B C D D odd even odd even
0 0 0 1 1 0 00010 00011
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0 0 1 0 1 0 00100 001010 0 1 1 0 1 00111 00110
0 1 0 0 1 0 01000 01001
0 1 0 1 0 1 01011 01010
0 1 1 0 0 1 01101 01100
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0 1 1 1 1 0 01110 011111 0 0 0 1 0 10000 10001
1 0 0 1 0 1 10011 10010
1 0 1 0 0 1 10101 10100
1 0 1 1 1 0 10110 10111
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1 1 0 0 0 1 11001 110001 1 0 1 1 0 11010 11011
1 1 1 0 1 0 11100 11101
1 1 1 1 0 1 11111 11110
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Procedure:
1. The circuit is implemented using logic gates.
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2. The inputs are given as per the truth table.3. The corresponding outputs are noted.
4. The theoretical and practical values were verified.
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Result:
The odd and even parity checkers are implemented using the logic gates and the odd parity and
even parity numbers are generated using the corresponding generators.
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Outcome:At the completion of an experiment student will able to verify the odd and even parity checker
using logic gates.
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43 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
1. What is parity bit?
2. Why parity bit is added to message?
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3. What is parity checker?
4. What is odd parity?
5. What is even parity?
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6. What are the gates involved for parity generator?
7. List the procedures to convert gray code into binary.
8. Why weighted code is called as reflective codes?
9. What is a sequential code?
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10. What is error deducting code?11. What is ASCII code?
12. What is hamming code?
13. List the binary weighted code.
14. List the binary non weighted code.
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15. Write the hamming code equation16. List the procedures to convert binary code into gray
17. What are the applications of gray code?
18. What are the applications of Excess- 3 code?
Viva ? Voce
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44 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Expt.No.9: MULTIPLEXER AND DEMULTIPLEXER
Aim:
To design and verify the truth table of a 4X1 multiplexer & 1X4 demultiplexer
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Apparatus required:Sl. No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. OR gate IC 7432 1
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3. NOT gate IC 7404 14. AND gate ( three input ) IC 7411 1
5. Connecting wires As required
Theory:
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Multiplexing means transmitting a large number of information units over a smaller number of channels orlines. A digital multiplexer is a combinational circuit that selects binary information from one of many input
lines and directs it to a single output line. The selection of particular input line is controlled by a set of
selection lines. Normally, there are 2
n
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input lines and n selection lines whose bit combinations determineswhich input is selected. A multiplexer is called a data selector, since it selects one of many inputs and
steers the binary information to the output line. A Strobe is also provided to allow the designer to disable all
output data until a specified time. Then, by allowing the STROBE to go low, the proper lead can be
selected. This feature is very useful where data might be changing the same time DATA SELECT leads
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change. It is a very useful Medium Scale Integration (MSI) function and has a multitude of applications. It isused for connecting two or more sources to a single destination among the computer units and it is useful
for constructing a common bus system. A decoder with an enable input can function as a demultiplexer. A
Demultiplexer is a circuit that receives information on a single line and transmits this information on one of
2
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npossible output lines. The selection of specific output line is controlled by the bit values of n selection
lines. The decoder and demultiplexer operations are obtained from the same circuit; a decoder with an
enable input is referred to as a decoder / de-multiplexer. The Strobe lead can be used to active or de-
active the entire IC, allowing time for the address lines to change the information is fed to the output.
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Demultiplexers are useful anytime information from one source must be fed several places.--- Content provided by FirstRanker.com ---
45 Format No.FirstRanker/stud/LM/34/issue:00/revision:004 X 1 MULTIPLEXER
CIRCUIT DIAGRAM:
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--- Content provided by FirstRanker.com ---
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46 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
1X4 DEMULTIPLEXER
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--- Content provided by FirstRanker.com ---
CIRCUIT DIAGRAM:
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47 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Result:
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The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth tableswere verified.
Outcome:
At the completion of an experiment student will able to design the multiplexer and the
--- Content provided by FirstRanker.com ---
demultiplexer--- Content provided by FirstRanker.com ---
1. What is multiplexer?
2. What is demultiplexer?
3. What are the advantages of multiplexer?
4. What are the advantages of demultiplexer?
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5. What is select signal?6. How to choose select signal in multiplexer?
7. How to choose select signal in demultiplexer?
8. Write the formula used in select signal.
9. What is the difference between the multiplexer and demultiplexer?
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10. What is the application of multiplexer?11. What is the application of demultiplexer?
12. Draw the truth table of multiplexer.
13. Draw the truth table of demultiplexer.
14. How many select signals are needed in 8*1 multiplexer?
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15. How many select signals are needed in 8*1 demultiplexer?Viva ? Voce
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48 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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EXP NO: 11 SHIFT REGISTER
Aim:
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To design and implement the various shift registerApparatus required:
Sl. No Name of the Apparatus Range Quantity
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1. D flip flop IC 7474 22. OR gate IC 7432 1
3. IC Trainer kit 1
5. Connecting wires As required
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Theory:A register is capable of shifting its binary information in one or both directions is
known as shift register. The logical configuration of shift register consist of a D-Flip flop
cascaded with output of one flip flop connected to input of next flip flop. All flip flops receive
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common clock pulses which causes the shift in the output of the flip flop.The simplest possibleshift register is one that uses only flip flop. The output of a given flip flop is connected to the
input of next flip flop of the register. Each clock pulse shifts the content of register one bit position
to right.
PIN Diagram:
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Logic Diagram:
SERIAL IN SERIAL OUT
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49 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Truth Table:
CLK Serial in Serial out
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1 1 02 0 0
3 0 0
4 1 1
5 X 0
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6 X 07 X 1
Logic Diagram:
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Serial in parallel out:
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Truth Table:CLK DATA
OUTPUT
Q
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AQ
B
Q
C
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QD
1 1 1 0 0 0
2 0 0 1 0 0
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3 0 0 0 1 14 1 1 0 0 1
Parallel in Serial Out:
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50 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
CLK Q3 Q2 Q1 Q0 O/P
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0 1 0 0 1 11 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1
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Truth Table:--- Content provided by FirstRanker.com ---
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Parallel in Parallel Out:
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PARALLEL IN PARALLEL OUT:
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Truth Table:--- Content provided by FirstRanker.com ---
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Procedure:
1. Connections are given as per circuit diagram
2. Logical inputs are given as per circuit diagram.
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3. Observe the output and verify the truth table.Result:
Thus the implementation of shift registers using flip flops was completed successfully.
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Outcome:At the completion of an experiment student will able to design the various types of shift register.
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CLKDATA INPUT OUTPUT
D
A D
B D
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C DD Q
A Q
B Q
C Q
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D1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
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51 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.12: SYNCHRONOUS UP/DOWN COUNTER
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Aim:To design and implement 3 bit synchronous up/down counter
Apparatus required:
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S.No Name of the Apparatus Range Quantity
1. JK Flip Flop IC 7474 2
2. OR gate IC 7432 1
3. NOT gate IC 7404 1
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4. AND gate ( three input ) IC 7411 15 XOR gate IC 7486 1
6 IC Trainer Kit 1
7. Connecting wires As required
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Theory:
A counter is a register capable of counting number of clock pulse arriving at its clock input.
Counter represents the number of clock pulses arrived. An up/down counter is one that is capable of
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progressing in increasing order or decreasing order through a certain sequence. An up/down counteris also called bidirectional counter. Usually up/down operation of the counter is controlled by up/down
signal. When this signal is high counter goes through up sequence and when up/down signal is low counter
follows reverse sequence.
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K map:--- Content provided by FirstRanker.com ---
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52 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Q Q
t+1 J K
0 0 0 X
0 1 1 X
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1 0 X 11 1 X 0
State Diagram:
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Characteristic Table:
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Logic Diagram:
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53 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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InputUp/Down
Present
State
Q
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AQ
B
Q
C
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Next State
Q
A+1
Q
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B+1Q
C+1
A
J
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AK
A
B
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JB
K
B
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CJ
C
K
C
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0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
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0 1 0 0 0 1 1 X 1 1 X 1 X0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
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1 0 0 1 0 1 0 0 X 1 X X 11 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
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1 1 1 0 1 1 1 X 0 X 0 1 X1 1 1 1 0 0 0 X 1 X 1 X 1
Truth Table:
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Procedure:1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
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Result:Thus the 3-bit synchronous up/down counters was implemented successfully.
Outcome:
At the completion of an experiment student will able to design the synchronous up/down counter.
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54 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.12:
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SIMULATION OF COMBINATIONAL CIRCUITS USING HDLAim:
To write a verilog code for half adder, full adder and multiplexer
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Tools Required:
Xilinx 9.2
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Program:
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Simulation wave for half adder
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55 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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MULTIPLEXER:
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Procedure:
1. Write and draw the Digital logic system.
2. Write the Verilog code for above system.
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3. Enter the Verilog code in Xilinx software.4. Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and verify the
output waveform as obtained.
5. Implement the above code in Spartan III using FPGA kit.
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Result:Thus the verilog code for half adder, full adder and multiplexer were simulated and verified
successfully.
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Outcome:At the completion of an experiment student will able to be known the verilog code for half adder,
full adder and multiplexer.
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56 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.13:SIMULATION OF SEQUENTIAL CIRCUITS USING HDL
Aim:
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To write a verilog code for RS, D, JK flip flop and up counter
Tools required:
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Xilinx 9.2Program:
RS Flip Flop:
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D Flip Flop:
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FirstRanker.com - FirstRanker's Choice1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
III SEMESTER - R 2017
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
Section : _______________________________________
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LABORATORY MANUAL
--- Content provided by FirstRanker.com ---
2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
--- Content provided by FirstRanker.com ---
enterprising professionals conforming to global standards through value based quality education andtraining.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
--- Content provided by FirstRanker.com ---
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
--- Content provided by FirstRanker.com ---
needs.? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
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industry by continuous assessment and training.VISION
--- Content provided by FirstRanker.com ---
MISSIONVISION
MISSION
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3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
--- Content provided by FirstRanker.com ---
1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
--- Content provided by FirstRanker.com ---
2. Core CompetenceTo train the students to meet the needs of core industry with an attitude of learning new
technologies.
3. Breadth
--- Content provided by FirstRanker.com ---
To provide relevant training and experience to bridge the gap between theory and practice whichenable them to find solutions to problems in industry and research that contributes to the overall
development of society.
4. Professionalism
--- Content provided by FirstRanker.com ---
To inculcate professional and effective communication skills to the students to make them lead ateam and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
5. Lifelong Learning/Ethics
--- Content provided by FirstRanker.com ---
To practice ethical and professional responsibilities in the organization and society withcommitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
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f. Graduates will demonstrate skills to use modern engineering tools, software and equipment toanalyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
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will be aware of contemporary issues.j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
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--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
SYLLABUS
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Objectives:
The student should be made to:
? Understand the various logic gates.
? Be familiar with various combinational circuits.
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? Understand the various components used in the design of digital computers.? Be exposed to sequential circuits
? Learn to use HDL
List of experiments:
1. Verification of Boolean Theorems using basic gates.
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2. Design and implementation of combinational circuits using basic gates for arbitraryfunctions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
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c. Magnitude Comparatord. Application using multiplexers
4. Design and implementation of sequential circuits:
a. Shift ?registers
b. Synchronous and asynchronous counters
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5. Coding combinational / sequential circuits using HDL.6. Design and implementation of a simple digital system (Mini Project).
Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
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? Design and Implement combinational and sequential circuits.? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Content
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Sl.No. Name of the Experiment Page No.
1.
Verification of Boolean Theorems using Digital Logic Gates
2.
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Design and Implementation of Combinational Circuits using Basic Gates for ArbitraryFunctions, Code Converters
3.
Implementation of half adder and full adder
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4.Implementation of half subtractor and full subtractor
5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
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6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
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7.Design and Implementation of Magnitude Comparator.
8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
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Design and Implementation of Shift Registers.10.
Design and Implementation of Synchronous and Asynchronous Counters.
11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
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HDL Software Required).12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.1: STUDY OF BASIC GATES
Aim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
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7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
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more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known asuniversal gates. Basic gates form these gates.
AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
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low.OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
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A NOT gate is the physical realization of the complementation operation. The NOT gate iscalled an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
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NOR gateThe NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
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similar to OR gate but excludes the combination of both A and B being equal to one. The exclusiveOR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Procedure:
1. Connections are given as per the circuit diagram.
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2. For all the IC?s 7th
pin is grounded and 14
th
pin is given +5 supply.
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3. Apply the inputs and verify the truth table for all gates.Result:
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The truth tables of all the basic logic gates were verified.Outcome:
At the completion of an experiment student will able to verify the truth
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table of all basic gates--- Content provided by FirstRanker.com ---
1. List out the basic gate.2. Mention the universal gate.
3. How many gates presented in IC 7408?
4. What is IC?
5. What are the applications of gates?
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6. Write the truth table of AND gate.7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
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11. Write the truth table of EX- OR gate.12. What are the classifications of IC?
13. What are types of linear integrated circuit?
14. What is meant by etching?
15. What are the advantages of IC?
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16. Write the truth table of EX- NOR gate.Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.2:
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VERIFICATION OF BOOLEAN THEOREMS USING LOGICGATES
Aim: To verification of Boolean theorems using logic gates
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 3
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7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
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BASIC Boolean Laws
1. Commutative Law
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The binary operator OR, AND is said to be commutative if,1. A+B = B+A
2. A.B=B.A
2. Associative Law
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The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
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3. Distributive LawThe binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
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4. Absorption Law
1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
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1. A+A = A2. A.A = A
6. Complementary Law
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1. A+A' = 12. A.A' = 0
7. De Morgan ?s Theorem
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1. The complement of the sum is equal to the sum of the product of the individualcomplements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design
1. Absorption Law
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A+AB = A--- Content provided by FirstRanker.com ---
2. Involution (or) Double complement Law
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A = A--- Content provided by FirstRanker.com ---
3. Idempotent Law
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1. A+A = A
2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
A+B = A.B
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5. Distributive Law
A+(B.C) = (A+B).(A+C)
Procedure:
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1. Obtain the required IC along with the Digital trainer kit.2. Connect zero volts to GND pin and +5 volts to V
cc
.
3. Apply the inputs to the respective input pins.
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4. Verify the output with the truth table.Result:
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Thus the above stated Boolean laws are verified.Outcome:
At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?
2. What is associative law?
3. What is mean by compliment gate?
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4. Explain the basic laws in digital electronics5. What is double complement?
Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.3: HALF ADDER AND FULL ADDERAim:
To design and verify the truth table of the Half Adder & Full Adder circuits
Apparatus required:
--- Content provided by FirstRanker.com ---
S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
--- Content provided by FirstRanker.com ---
4. NOT gate IC 7404 15. EX-OR gate IC 7486 1
6. Connecting wires As required
--- Content provided by FirstRanker.com ---
Theory:The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
0 + 0 = 0
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0 + 1 = 1
1 + 0 = 1
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1 + 1 = 0 (with 1 as carry)The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
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Half adder:A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
Full adder:
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A combinational circuit which performs the arithmetic sum of three input bits is called full adder. Thethree input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
From the truth table, the expression for sum and carry bits of the output can be obtained as,
--- Content provided by FirstRanker.com ---
SUM = A?B?C + A?BC? + AB?C? + ABCCARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half Adder
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Truth table:--- Content provided by FirstRanker.com ---
From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
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S = A BCarry, C = A . B
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Circuit diagram:--- Content provided by FirstRanker.com ---
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Full adder
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Truth table:Sl.No. Input Output
A B C S C
1. 0 0 0 0 0
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2. 0 0 1 1 03. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
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7. 1 1 0 0 18. 1 1 1 1 1
Sl.No. Input Output
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A B S C1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,Sum:
--- Content provided by FirstRanker.com ---
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:--- Content provided by FirstRanker.com ---
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CARRY = AB + AC + BC
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Logic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
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1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
th
pin is grounded and 14
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thpin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
Result:
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The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
At the completion of an experiment student will able to design the half adder circuit and the
--- Content provided by FirstRanker.com ---
full adder circuit.--- Content provided by FirstRanker.com ---
19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
Aim:
--- Content provided by FirstRanker.com ---
To design and verify the truth table of the half subtractor & full subtractor circuitsApparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
--- Content provided by FirstRanker.com ---
2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
--- Content provided by FirstRanker.com ---
Theory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
subtrahend bit, hence 1 is borrowed.
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Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
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Full subtractor:A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
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From the truth table the expression for difference and borrow bits of the output can be obtainedas,
Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
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Borrow, BORR = A?BC + AB?C + ABC? +ABC--- Content provided by FirstRanker.com ---
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half subtractor
Truth table:
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Sl.No. Input OutputA B Difference Borrow
1. 0 0 0 0
2. 0 1 1 1
3. 1 0 1 0
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4. 1 1 0 0From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A B
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Borrow, BORR = A?. B
Logic diagram:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
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2. Full subtractorTruth table:
Sl.No.
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Input OutputA B C Difference Borrow
1. 0 0 0 0 0
2. 0 0 1 1 1
3. 0 1 0 1 1
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4. 0 1 1 0 15. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
8. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
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Borrow
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
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Borrow = A?B + A?C + BCCircuit diagram:
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--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
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Aim:
To design and implement 4-bit adder and subtractor using IC 7483
--- Content provided by FirstRanker.com ---
Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. IC IC 7483 1
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3. NOT gate IC 7404 14. EX-OR gate IC 7486 1
5. Connecting wires As required
Theory:
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4 BIT Binary adder:
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected to
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the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? aredesignated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
0
and it ripples through
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the full adder to the output carry C4
.
4 BIT Binary subtractor:
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The circuit for subtracting A-B consists of an adder with inverters, placed between each data input?B? and the corresponding input of full adder. The input carry C
0
must be equal to 1 when performing
subtraction.
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4 BIT Binary adder / subtractor:The addition and subtraction operation can be combined into one circuit with one common binary
adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
becomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PIN Diagram for IC 7483:Logic Diagram: 4-Bit Binary Diagram:
Logic diagram: 4-Bit Binary Subtractor:
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4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Truth table:
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Procedure:
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1. Connections are given as per the circuit diagrams.2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
.
Result:
--- Content provided by FirstRanker.com ---
The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table wasverified.
Outcome:
At the completion of an experiment student will able to design 4-bit binary adder and subtractor
--- Content provided by FirstRanker.com ---
Input Data A Input Data B Addition SubtractionA4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
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0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 01 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?
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2. Write the truth table for half adder.3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
5. Write the truth table for full subtrator.
6. Draw the logic diagram of full subtrator.
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7. What is adder?8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
10. What is combinational circuit?
11. What is different between combinational and sequential circuit?
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12. What are the gates involved for binary adder?13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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Viva ? Voce--- Content provided by FirstRanker.com ---
26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.6: MAGNITUDE COMPARATOR
Aim:
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To design, construct and study the performance of 2 bit magnitude comparatorApparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
--- Content provided by FirstRanker.com ---
3. OR gate IC 7432 14. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
--- Content provided by FirstRanker.com ---
Theory:
The comparison of two numbers is an operator that determines one number is greater than, less
than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
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numbers A and B and determines their relative magnitude. The outcome of the comparator is specified bythree binary variables that indicate whether A>B, A=B (or) A
Truth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:
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Pin Diagram for IC 7485:--- Content provided by FirstRanker.com ---
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:
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Truth table:
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Procedure:1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
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Result:Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
comparator using logic gates.
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--- Content provided by FirstRanker.com ---
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A B A>B A=B A0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
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0 1 00 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
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1 0 00 0 0 0
0 0 0 0
0 0 0 1
0 0 0 1
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0 0 1Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
1. What is magnitude comparator?
2. What is most significant bit?
3. Explain operation of AND gate.
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4. Explain truth table of a comparator.5. Explain magnitude comparator7485 IC.
6. What is 8-bit input Magnitude Comparator?
7. What is IC?
8. Explain the k-map simplification of A>B.
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9. Explain the k-map simplification of A=B.10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
12. What is the truth table of 1-bit magnitude comparator?
13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Aim:
To design, construct and study the performance of 4-bit different code converters
(i) Binary to gray code converter
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(ii) Gray to binary code converter(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:The availability of large variety of codes for the same discrete elements of information results in
the use of different codes by different systems. A conversion circuit must be inserted between the two
systems if each uses different codes for same information. Thus, code converter is a circuit that makes the
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two systems compatible even though each uses different binary code. The bit combination assigned tobinary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a
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circuit that makes the two systems compatible even though each uses a different binary code. To convertfrom binary code to Excess-3 code, the input lines must supply the bit combination of elements as
specified by code and the output lines generate the corresponding bit combination of code. Each one of the
four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are
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various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output isC+D has been used to implement partially each of three outputs.
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Logic diagram:32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(i) Binary to gray code converter
Logic Diagram:
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K map for G3:
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G3 = B3K map for G2:
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K map for G1:33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for G0:Truth table:
--- Content provided by FirstRanker.com ---
0
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
0
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
0
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
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11
0
0
1
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10
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(ii) Gray to binary code converter
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34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:K map for B3:
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B3=G3
K map for B2:
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
G3 G2 G1 G0 B3 B2 B1 B0
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0
0
0
0
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00
0
0
1
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11
1
1
1
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11
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
0
0
0
0
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11
1
1
0
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00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
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11
0
0
1
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10
0
1
1
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00
1
1
--- Content provided by FirstRanker.com ---
01
0
1
0
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10
1
0
1
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01
0
1
0
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1K map for B1:
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K map for B0:
Truth table:
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(iii) BCD to excess-3 code converterLogic Diagram:
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K map for E3:E3 = B3 + B2 (B0 + B1)
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K map for E2:--- Content provided by FirstRanker.com ---
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for E1:--- Content provided by FirstRanker.com ---
K map for E0:--- Content provided by FirstRanker.com ---
Truth table:
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(iv) Excess-3 toB3 B2 B1 B0 G3 G2 G1 G0
0
0
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00
0
0
0
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01
1
1
1
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11
1
1
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00
0
0
1
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11
1
0
0
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00
1
1
1
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10
0
1
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10
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1
1
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00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
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10
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1
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01
0
1
0
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10
1
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1
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0
0
0
0
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01
1
1
1
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1x
x
x
x
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xx
0
1
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11
1
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0
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00
1
x
x
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xx
x
x
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10
0
1
1
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00
1
1
0
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xx
x
x
x
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x1
0
1
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01
0
1
0
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10
x
x
x
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xx
x
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38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
BCD code converter
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Logic Diagram:K map for A:
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A = X1 X2 + X3 X4 X1
K map for B:
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39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
K map for C:--- Content provided by FirstRanker.com ---
K map for D:--- Content provided by FirstRanker.com ---
Truth table:--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
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B3 B2 B1 B0 G3 G2 G1 G0
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00
0
0
0
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11
1
1
1
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0
1
1
1
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10
0
0
0
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11
0
0
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11
0
0
1
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10
1
0
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10
1
0
1
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01
0
0
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00
0
0
0
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00
1
1
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00
0
0
1
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11
1
0
0
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0
0
1
1
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00
1
1
0
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00
1
0
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10
1
0
1
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01
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40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections were given as per circuit diagram.
2. Logical inputs were given as per truth table
3. Observe the logical output and verify with the truth tables.
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Result:
Thus the code converters were designed and verified using the corresponding truth table.
Outcome:
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At the completion of an experiment student will able to design the binary to gray converter.1. What is binary code?
2. What is gray code?
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3. What are the advantages of gray code?4. What is unit distance code?
5. What is sequential code?
6. How to convert binary to gray code?
7. How to convert gray to binary code?
--- Content provided by FirstRanker.com ---
8. What is reflective code?9. What are the advantages of EX ? 3 code?
10. Which code is used to arithmetic operation in digital circuits?
11. Explain the operation of EX ? OR.
12. What is K ? Map?
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13. Draw the truth table of EX- OR gate.14. What is SOP?
15. What is POS?
16. What is minterm?
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Viva ? Voce--- Content provided by FirstRanker.com ---
41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.8: PARITY GENERATORS AND CHECKERS
Aim:
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To implement the odd and even parity checkers using the logic gates and also to generate the odd parityand even parity numbers using the generators
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl. No Component Type Quantity1 Trainer Kit - 1
2 EX-OR IC7486 1
3 NOT gate IC 7404 1
4 Connecting wires - Required
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Theory:
Parity checking is used for error detection in data transmission.
Odd parity checkers:
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It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
odd.
Even parity checker:
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It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
even.
Odd parity generators:
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It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also
the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bits
which is an odd parity number.
Even parity generator:
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It generates an even parity number. The even parity checker circuit is used with the inverted output and
also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5
bits which is an even parity number.
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42 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:
Input Checker output Generator output
A B C D D odd even odd even
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0 0 0 1 1 0 00010 000110 0 1 0 1 0 00100 00101
0 0 1 1 0 1 00111 00110
0 1 0 0 1 0 01000 01001
0 1 0 1 0 1 01011 01010
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0 1 1 0 0 1 01101 011000 1 1 1 1 0 01110 01111
1 0 0 0 1 0 10000 10001
1 0 0 1 0 1 10011 10010
1 0 1 0 0 1 10101 10100
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1 0 1 1 1 0 10110 101111 1 0 0 0 1 11001 11000
1 1 0 1 1 0 11010 11011
1 1 1 0 1 0 11100 11101
1 1 1 1 0 1 11111 11110
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Procedure:
1. The circuit is implemented using logic gates.
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2. The inputs are given as per the truth table.
3. The corresponding outputs are noted.
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4. The theoretical and practical values were verified.Result:
The odd and even parity checkers are implemented using the logic gates and the odd parity and
even parity numbers are generated using the corresponding generators.
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Outcome:
At the completion of an experiment student will able to verify the odd and even parity checker
using logic gates.
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43 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
1. What is parity bit?
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2. Why parity bit is added to message?3. What is parity checker?
4. What is odd parity?
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5. What is even parity?6. What are the gates involved for parity generator?
7. List the procedures to convert gray code into binary.
8. Why weighted code is called as reflective codes?
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9. What is a sequential code?10. What is error deducting code?
11. What is ASCII code?
12. What is hamming code?
13. List the binary weighted code.
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14. List the binary non weighted code.15. Write the hamming code equation
16. List the procedures to convert binary code into gray
17. What are the applications of gray code?
18. What are the applications of Excess- 3 code?
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Viva ? Voce--- Content provided by FirstRanker.com ---
44 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.9: MULTIPLEXER AND DEMULTIPLEXER
Aim:
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To design and verify the truth table of a 4X1 multiplexer & 1X4 demultiplexerApparatus required:
Sl. No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. OR gate IC 7432 13. NOT gate IC 7404 1
4. AND gate ( three input ) IC 7411 1
5. Connecting wires As required
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Theory:Multiplexing means transmitting a large number of information units over a smaller number of channels or
lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input
lines and directs it to a single output line. The selection of particular input line is controlled by a set of
selection lines. Normally, there are 2
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ninput lines and n selection lines whose bit combinations determines
which input is selected. A multiplexer is called a data selector, since it selects one of many inputs and
steers the binary information to the output line. A Strobe is also provided to allow the designer to disable all
output data until a specified time. Then, by allowing the STROBE to go low, the proper lead can be
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selected. This feature is very useful where data might be changing the same time DATA SELECT leadschange. It is a very useful Medium Scale Integration (MSI) function and has a multitude of applications. It is
used for connecting two or more sources to a single destination among the computer units and it is useful
for constructing a common bus system. A decoder with an enable input can function as a demultiplexer. A
Demultiplexer is a circuit that receives information on a single line and transmits this information on one of
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2n
possible output lines. The selection of specific output line is controlled by the bit values of n selection
lines. The decoder and demultiplexer operations are obtained from the same circuit; a decoder with an
enable input is referred to as a decoder / de-multiplexer. The Strobe lead can be used to active or de-
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active the entire IC, allowing time for the address lines to change the information is fed to the output.Demultiplexers are useful anytime information from one source must be fed several places.
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45 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
4 X 1 MULTIPLEXER
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CIRCUIT DIAGRAM:--- Content provided by FirstRanker.com ---
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46 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
1X4 DEMULTIPLEXER
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CIRCUIT DIAGRAM:
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47 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Result:The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth tables
were verified.
Outcome:
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At the completion of an experiment student will able to design the multiplexer and thedemultiplexer
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1. What is multiplexer?
2. What is demultiplexer?
3. What are the advantages of multiplexer?
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4. What are the advantages of demultiplexer?5. What is select signal?
6. How to choose select signal in multiplexer?
7. How to choose select signal in demultiplexer?
8. Write the formula used in select signal.
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9. What is the difference between the multiplexer and demultiplexer?10. What is the application of multiplexer?
11. What is the application of demultiplexer?
12. Draw the truth table of multiplexer.
13. Draw the truth table of demultiplexer.
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14. How many select signals are needed in 8*1 multiplexer?15. How many select signals are needed in 8*1 demultiplexer?
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Viva ? Voce--- Content provided by FirstRanker.com ---
48 Format No.FirstRanker/stud/LM/34/issue:00/revision:00EXP NO: 11 SHIFT REGISTER
Aim:
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To design and implement the various shift register
Apparatus required:
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Sl. No Name of the Apparatus Range Quantity1. D flip flop IC 7474 2
2. OR gate IC 7432 1
3. IC Trainer kit 1
5. Connecting wires As required
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Theory:
A register is capable of shifting its binary information in one or both directions is
known as shift register. The logical configuration of shift register consist of a D-Flip flop
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cascaded with output of one flip flop connected to input of next flip flop. All flip flops receivecommon clock pulses which causes the shift in the output of the flip flop.The simplest possible
shift register is one that uses only flip flop. The output of a given flip flop is connected to the
input of next flip flop of the register. Each clock pulse shifts the content of register one bit position
to right.
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PIN Diagram:Logic Diagram:
SERIAL IN SERIAL OUT
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49 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Truth Table:
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CLK Serial in Serial out1 1 0
2 0 0
3 0 0
4 1 1
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5 X 06 X 0
7 X 1
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Logic Diagram:Serial in parallel out:
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Truth Table:
CLK DATA
OUTPUT
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QA
Q
B
Q
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CQ
D
1 1 1 0 0 0
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2 0 0 1 0 03 0 0 0 1 1
4 1 1 0 0 1
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Parallel in Serial Out:--- Content provided by FirstRanker.com ---
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50 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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CLK Q3 Q2 Q1 Q0 O/P0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1
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Truth Table:
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Parallel in Parallel Out:--- Content provided by FirstRanker.com ---
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PARALLEL IN PARALLEL OUT:--- Content provided by FirstRanker.com ---
Truth Table:
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Procedure:
1. Connections are given as per circuit diagram
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2. Logical inputs are given as per circuit diagram.3. Observe the output and verify the truth table.
Result:
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Thus the implementation of shift registers using flip flops was completed successfully.Outcome:
At the completion of an experiment student will able to design the various types of shift register.
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CLK
DATA INPUT OUTPUT
D
A D
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B DC D
D Q
A Q
B Q
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C QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
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51 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.12: SYNCHRONOUS UP/DOWN COUNTER
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Aim:
To design and implement 3 bit synchronous up/down counter
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Apparatus required:S.No Name of the Apparatus Range Quantity
1. JK Flip Flop IC 7474 2
2. OR gate IC 7432 1
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3. NOT gate IC 7404 14. AND gate ( three input ) IC 7411 1
5 XOR gate IC 7486 1
6 IC Trainer Kit 1
7. Connecting wires As required
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Theory:
A counter is a register capable of counting number of clock pulse arriving at its clock input.
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Counter represents the number of clock pulses arrived. An up/down counter is one that is capable ofprogressing in increasing order or decreasing order through a certain sequence. An up/down counter
is also called bidirectional counter. Usually up/down operation of the counter is controlled by up/down
signal. When this signal is high counter goes through up sequence and when up/down signal is low counter
follows reverse sequence.
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K map:
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52 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Q Q
t+1 J K
0 0 0 X
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0 1 1 X1 0 X 1
1 1 X 0
State Diagram:
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Characteristic Table:
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Logic Diagram:
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53 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Input
Up/Down
Present
State
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QA
Q
B
Q
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CNext State
Q
A+1
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QB+1
Q
C+1
A
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JA
K
A
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BJ
B
K
B
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C
J
C
K
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C0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
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0 1 0 1 1 0 0 X 0 0 X X 10 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
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1 0 0 0 0 0 1 0 X 0 X 1 X1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
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1 1 0 1 1 1 0 X 0 1 X X 11 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1
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Truth Table:--- Content provided by FirstRanker.com ---
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Procedure:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
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3. Observe the output and verify the truth table.Result:
Thus the 3-bit synchronous up/down counters was implemented successfully.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to design the synchronous up/down counter.--- Content provided by FirstRanker.com ---
54 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.12:
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SIMULATION OF COMBINATIONAL CIRCUITS USING HDL
Aim:
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To write a verilog code for half adder, full adder and multiplexerTools Required:
Xilinx 9.2
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Program:
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Simulation wave for half adder--- Content provided by FirstRanker.com ---
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55 Format No.FirstRanker/stud/LM/34/issue:00/revision:00MULTIPLEXER:
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Procedure:
1. Write and draw the Digital logic system.
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2. Write the Verilog code for above system.3. Enter the Verilog code in Xilinx software.
4. Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and verify the
output waveform as obtained.
5. Implement the above code in Spartan III using FPGA kit.
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Result:
Thus the verilog code for half adder, full adder and multiplexer were simulated and verified
successfully.
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Outcome:
At the completion of an experiment student will able to be known the verilog code for half adder,
full adder and multiplexer.
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56 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Expt.No.13:
SIMULATION OF SEQUENTIAL CIRCUITS USING HDL
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Aim:To write a verilog code for RS, D, JK flip flop and up counter
Tools required:
--- Content provided by FirstRanker.com ---
Xilinx 9.2
Program:
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RS Flip Flop:--- Content provided by FirstRanker.com ---
D Flip Flop:
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57 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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JK Flip Flop:
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Up Counter:
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FirstRanker.com - FirstRanker's Choice
--- Content provided by FirstRanker.com ---
1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
?
--- Content provided by FirstRanker.com ---
DEPARTMENT OFCOMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
--- Content provided by FirstRanker.com ---
CS8382 DIGITAL SYSTEMS LABORATORY--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
--- Content provided by FirstRanker.com ---
Section : _______________________________________--- Content provided by FirstRanker.com ---
LABORATORY MANUAL2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
training.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
--- Content provided by FirstRanker.com ---
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at differentlevels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
--- Content provided by FirstRanker.com ---
Engineering and thereby produce extremely well trained employable, socially responsible and innovativeElectrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
--- Content provided by FirstRanker.com ---
? To provide highest quality learning environment for the students emphasizing fundamentalconcepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
--- Content provided by FirstRanker.com ---
VISIONMISSION
VISION
--- Content provided by FirstRanker.com ---
MISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
--- Content provided by FirstRanker.com ---
engineering enabling them to solve complex problems in order to develop real time applications.2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
technologies.
--- Content provided by FirstRanker.com ---
3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
development of society.
--- Content provided by FirstRanker.com ---
4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
--- Content provided by FirstRanker.com ---
5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
--- Content provided by FirstRanker.com ---
d. Graduates will be able to design a system, component or process as per needs and specifications.e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
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h. Graduates will be able to communicate effectively by both verbal and written form.i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
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CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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SYLLABUS
Objectives:
The student should be made to:
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? Understand the various logic gates.? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
? Learn to use HDL
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List of experiments:1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
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a. 4 ? bit binary adder / subtractorb. Parity generator / checker
c. Magnitude Comparator
d. Application using multiplexers
4. Design and implementation of sequential circuits:
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a. Shift ?registersb. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
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Course Outcomes:? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
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? Design and Implement a simple digital system.--- Content provided by FirstRanker.com ---
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Content
Sl.No. Name of the Experiment Page No.
1.
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Verification of Boolean Theorems using Digital Logic Gates2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
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3.Implementation of half adder and full adder
4.
Implementation of half subtractor and full subtractor
5.
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Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates andMSI Devices
6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
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Devices7.
Design and Implementation of Magnitude Comparator.
8.
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Design and Implementation of Application using Multiplexers / Demultiplexers.9.
Design and Implementation of Shift Registers.
10.
Design and Implementation of Synchronous and Asynchronous Counters.
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11.Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
12.
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Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).--- Content provided by FirstRanker.com ---
7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.1: STUDY OF BASIC GATES
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Aim:To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. NAND gate IC 7400 16. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND gate
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The AND gate performs a logical multiplication commonly known as AND function. Theoutput is high when both the inputs are high. The output is low level when any one of the inputs is
low.
OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
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high when any one of the inputs is high. The output is low level when both the inputs are low.NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
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The NAND gate is a contraction of AND-NOT. The output is high when both inputs are lowand any one of the input is low .The output is low level when both inputs are high.
NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
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EX-OR gateAn Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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AND Gate Symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
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OR Gate:--- Content provided by FirstRanker.com ---
OR GATE:--- Content provided by FirstRanker.com ---
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00NAND Gate symbol: PIN Diagram:
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NOR Gate:--- Content provided by FirstRanker.com ---
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
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1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
th
pin is grounded and 14
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thpin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
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Result:The truth tables of all the basic logic gates were verified.
Outcome:
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At the completion of an experiment student will able to verify the truth
table of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
3. How many gates presented in IC 7408?
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4. What is IC?5. What are the applications of gates?
6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
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9. Write the truth table of NAND gate.10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
13. What are types of linear integrated circuit?
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14. What is meant by etching?15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.2:VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gates
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. NAND gate IC 7400 16. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
BASIC Boolean Laws
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1. Commutative LawThe binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A
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2. Associative Law
The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
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2. A.(B.C) = (A.B).C3. Distributive Law
The binary operator OR, AND is said to be distributive if,
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1. A+(B.C) = (A+B).(A+C)2. A.(B+C) = (A.B)+(A.C)
4. Absorption Law
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1. A+AB = A2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law1. A+A = A
2. A.A = A
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6. Complementary Law1. A+A' = 1
2. A.A' = 0
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7. De Morgan ?s Theorem1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
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2. The complement of the product is equal to the sum of the individual complements.A.B = A+B
Design
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1. Absorption LawA+AB = A
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2. Involution (or) Double complement LawA = A
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3. Idempotent Law
1. A+A = A
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2. A.A = A--- Content provided by FirstRanker.com ---
14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
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A+B = A.B5. Distributive Law
A+(B.C) = (A+B).(A+C)
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Procedure:
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
cc
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.3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
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Result:Thus the above stated Boolean laws are verified.
Outcome:
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At the completion of an experiment student will able to know the basic laws with their truth table.1. What is Demorgan?s law?
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2. What is associative law?3. What is mean by compliment gate?
4. Explain the basic laws in digital electronics
5. What is double complement?
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Viva ? Voce--- Content provided by FirstRanker.com ---
15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
To design and verify the truth table of the Half Adder & Full Adder circuits
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Apparatus required:
S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:
The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
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0 + 0 = 0
0 + 1 = 1
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1 + 0 = 11 + 1 = 0 (with 1 as carry)
The first three operations produce a sum of whose length is one digit, but when the last operation is
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performed the sum is two digits. The higher significant bit of this result is called a carry and lowersignificant bit is called the sum.
Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
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Full adder:
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
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From the truth table, the expression for sum and carry bits of the output can be obtained as,
SUM = A?B?C + A?BC? + AB?C? + ABC
CARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half Adder
Truth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
S = A B
Carry, C = A . B
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Circuit diagram:
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Full adder
Truth table:
Sl.No. Input Output
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A B C S C1. 0 0 0 0 0
2. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
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5. 1 0 0 1 06. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input Output
A B S C
1. 0 0 0 0
2. 0 1 1 0
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3. 1 0 1 04. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:
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CARRY = AB + AC + BC
Logic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
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thpin is grounded and 14
th
pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
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Result:
The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
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At the completion of an experiment student will able to design the half adder circuit and the
full adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
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Aim:
To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. EX-OR gate IC 7486 16. Connecting wires As required
Theory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
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is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than thesubtrahend bit, hence 1 is borrowed.
Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
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variables designate the minuend and the subtrahend bit, whereas the output variables produce thedifference and borrow bits.
Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
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implemented with two half subtractors and one OR gate.From the truth table the expression for difference and borrow bits of the output can be obtained
as,
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Difference, DIFF= A?B?C + A?BC? + AB?C? + ABCBorrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half subtractor
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Truth table:Sl.No. Input Output
A B Difference Borrow
1. 0 0 0 0
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2. 0 1 1 13. 1 0 1 0
4. 1 1 0 0
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From the truth table the expression for difference and borrow bits of the output can be obtained as,Difference, DIFF = A B
Borrow, BORR = A?. B
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Logic diagram:--- Content provided by FirstRanker.com ---
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2. Full subtractor
Truth table:
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Sl.No.
Input Output
A B C Difference Borrow
1. 0 0 0 0 0
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2. 0 0 1 1 13. 0 1 0 1 1
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 0
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7. 1 1 0 0 08. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
Borrow
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Borrow = A?B + A?C + BC
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Circuit diagram:--- Content provided by FirstRanker.com ---
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
Aim:
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To design and implement 4-bit adder and subtractor using IC 7483Apparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. IC IC 7483 1
3. NOT gate IC 7404 1
4. EX-OR gate IC 7486 1
5. Connecting wires As required
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Theory:
4 BIT Binary adder:
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A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can beconstructed with full adders connected in cascade, with the output carry from each full adder connected to
the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
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0and it ripples through
the full adder to the output carry C
4
.
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4 BIT Binary subtractor:The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
?B? and the corresponding input of full adder. The input carry C
0
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must be equal to 1 when performingsubtraction.
4 BIT Binary adder / subtractor:
The addition and subtraction operation can be combined into one circuit with one common binary
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adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, itbecomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PIN Diagram for IC 7483:
Logic Diagram: 4-Bit Binary Diagram:
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Logic diagram: 4-Bit Binary Subtractor:
4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:
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Procedure:
1. Connections are given as per the circuit diagrams.
2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
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.Result:
The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
verified.
Outcome:
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At the completion of an experiment student will able to design 4-bit binary adder and subtractorInput Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
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1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 00 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
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1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 125 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?
2. Write the truth table for half adder.
3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
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5. Write the truth table for full subtrator.6. Draw the logic diagram of full subtrator.
7. What is adder?
8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
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10. What is combinational circuit?11. What is different between combinational and sequential circuit?
12. What are the gates involved for binary adder?
13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.6: MAGNITUDE COMPARATOR
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Aim:
To design, construct and study the performance of 2 bit magnitude comparator
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
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6. EX-OR gate IC 7486 17. Connecting wires As required
Theory:
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The comparison of two numbers is an operator that determines one number is greater than, lessthan (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
three binary variables that indicate whether A>B, A=B (or) A
Truth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Logic Diagram:
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Pin Diagram for IC 7485:
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Logic Diagram:29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:Truth table:
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Procedure:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
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3. Observe the output and verify the truth table.Result:
Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
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Outcome:
At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
comparator using logic gates.
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A B A>B A=B A0 0 0 0
0 0 0 0
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0 0 0 00 0 0 0
0 1 0
0 0 0 1
0 0 0 1
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0 0 0 00 0 0 0
1 0 0
0 0 0 0
0 0 0 0
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0 0 0 10 0 0 1
0 0 1
Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
1. What is magnitude comparator?
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2. What is most significant bit?3. Explain operation of AND gate.
4. Explain truth table of a comparator.
5. Explain magnitude comparator7485 IC.
6. What is 8-bit input Magnitude Comparator?
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7. What is IC?8. Explain the k-map simplification of A>B.
9. Explain the k-map simplification of A=B.
10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
12. What is the truth table of 1-bit magnitude comparator?
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13. What is the use of magnitude comparator?--- Content provided by FirstRanker.com ---
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Expt.No.7: CODE CONVERSION
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31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Aim:
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To design, construct and study the performance of 4-bit different code converters(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
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7. Connecting wires As requiredTheory:
The availability of large variety of codes for the same discrete elements of information results in
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the use of different codes by different systems. A conversion circuit must be inserted between the twosystems if each uses different codes for same information. Thus, code converter is a circuit that makes the
two systems compatible even though each uses different binary code. The bit combination assigned to
binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
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and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit isdesigned. The Boolean functions are obtained from K-Map for each output variable. A code converter is a
circuit that makes the two systems compatible even though each uses a different binary code. To convert
from binary code to Excess-3 code, the input lines must supply the bit combination of elements as
specified by code and the output lines generate the corresponding bit combination of code. Each one of the
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four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are
various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is
C+D has been used to implement partially each of three outputs.
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Logic diagram:
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32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
(i) Binary to gray code converter
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Logic Diagram:
K map for G3:
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G3 = B3
K map for G2:
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K map for G1:
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33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for G0:
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Truth table:
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
0
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
0
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
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(ii) Gray to binary code converter34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:
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K map for B3:
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B3=G3K map for B2:
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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G3 G2 G1 G0 B3 B2 B1 B0
0
0
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00
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
0
0
0
0
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00
0
0
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
11
0
0
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00
1
1
1
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10
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
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11
0
0
1
--- Content provided by FirstRanker.com ---
10
1
0
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10
1
0
1
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01
0
1
0
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10
1
K map for B1:
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K map for B0:
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Truth table:
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00(iii) BCD to excess-3 code converter
Logic Diagram:
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K map for E3:
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E3 = B3 + B2 (B0 + B1)K map for E2:
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for E1:
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K map for E0:
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Truth table:
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(iv) Excess-3 to
B3 B2 B1 B0 G3 G2 G1 G0
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00
0
0
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
0
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
1
x
x
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xx
x
x
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
xx
x
x
x
--- Content provided by FirstRanker.com ---
x1
0
0
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11
0
0
1
--- Content provided by FirstRanker.com ---
10
x
x
x
--- Content provided by FirstRanker.com ---
xx
x
1
--- Content provided by FirstRanker.com ---
01
0
1
0
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10
1
0
x
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xx
x
x
x
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38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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BCD code converterLogic Diagram:
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K map for A:A = X1 X2 + X3 X4 X1
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K map for B:--- Content provided by FirstRanker.com ---
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39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for C:
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K map for D:
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Truth table:
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B3 B2 B1 B0 G3 G2 G1 G00
0
0
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00
1
1
1
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11
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
0
0
0
0
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
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40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections were given as per circuit diagram.
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2. Logical inputs were given as per truth table3. Observe the logical output and verify with the truth tables.
Result:
Thus the code converters were designed and verified using the corresponding truth table.
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Outcome:
At the completion of an experiment student will able to design the binary to gray converter.
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1. What is binary code?2. What is gray code?
3. What are the advantages of gray code?
4. What is unit distance code?
5. What is sequential code?
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6. How to convert binary to gray code?7. How to convert gray to binary code?
8. What is reflective code?
9. What are the advantages of EX ? 3 code?
10. Which code is used to arithmetic operation in digital circuits?
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11. Explain the operation of EX ? OR.12. What is K ? Map?
13. Draw the truth table of EX- OR gate.
14. What is SOP?
15. What is POS?
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16. What is minterm?--- Content provided by FirstRanker.com ---
Viva ? Voce
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41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.8: PARITY GENERATORS AND CHECKERS
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Aim:
To implement the odd and even parity checkers using the logic gates and also to generate the odd parity
and even parity numbers using the generators
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Apparatus required:Sl. No Component Type Quantity
1 Trainer Kit - 1
2 EX-OR IC7486 1
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3 NOT gate IC 7404 14 Connecting wires - Required
Theory:
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Parity checking is used for error detection in data transmission.Odd parity checkers:
It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
odd.
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Even parity checker:
It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
even.
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Odd parity generators:
It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also
the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bits
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which is an odd parity number.Even parity generator:
It generates an even parity number. The even parity checker circuit is used with the inverted output and
also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5
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bits which is an even parity number.--- Content provided by FirstRanker.com ---
42 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Truth table:
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Input Checker output Generator outputA B C D D odd even odd even
0 0 0 1 1 0 00010 00011
0 0 1 0 1 0 00100 00101
0 0 1 1 0 1 00111 00110
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0 1 0 0 1 0 01000 010010 1 0 1 0 1 01011 01010
0 1 1 0 0 1 01101 01100
0 1 1 1 1 0 01110 01111
1 0 0 0 1 0 10000 10001
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1 0 0 1 0 1 10011 100101 0 1 0 0 1 10101 10100
1 0 1 1 1 0 10110 10111
1 1 0 0 0 1 11001 11000
1 1 0 1 1 0 11010 11011
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1 1 1 0 1 0 11100 111011 1 1 1 0 1 11111 11110
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Procedure:1. The circuit is implemented using logic gates.
2. The inputs are given as per the truth table.
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3. The corresponding outputs are noted.4. The theoretical and practical values were verified.
Result:
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The odd and even parity checkers are implemented using the logic gates and the odd parity andeven parity numbers are generated using the corresponding generators.
Outcome:
At the completion of an experiment student will able to verify the odd and even parity checker
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using logic gates.--- Content provided by FirstRanker.com ---
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43 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
1. What is parity bit?2. Why parity bit is added to message?
3. What is parity checker?
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4. What is odd parity?
5. What is even parity?
6. What are the gates involved for parity generator?
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7. List the procedures to convert gray code into binary.8. Why weighted code is called as reflective codes?
9. What is a sequential code?
10. What is error deducting code?
11. What is ASCII code?
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12. What is hamming code?13. List the binary weighted code.
14. List the binary non weighted code.
15. Write the hamming code equation
16. List the procedures to convert binary code into gray
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17. What are the applications of gray code?18. What are the applications of Excess- 3 code?
Viva ? Voce
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44 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.9: MULTIPLEXER AND DEMULTIPLEXER
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Aim:
To design and verify the truth table of a 4X1 multiplexer & 1X4 demultiplexer
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl. No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. OR gate IC 7432 1
3. NOT gate IC 7404 1
4. AND gate ( three input ) IC 7411 1
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5. Connecting wires As requiredTheory:
Multiplexing means transmitting a large number of information units over a smaller number of channels or
lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input
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lines and directs it to a single output line. The selection of particular input line is controlled by a set ofselection lines. Normally, there are 2
n
input lines and n selection lines whose bit combinations determines
which input is selected. A multiplexer is called a data selector, since it selects one of many inputs and
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steers the binary information to the output line. A Strobe is also provided to allow the designer to disable alloutput data until a specified time. Then, by allowing the STROBE to go low, the proper lead can be
selected. This feature is very useful where data might be changing the same time DATA SELECT leads
change. It is a very useful Medium Scale Integration (MSI) function and has a multitude of applications. It is
used for connecting two or more sources to a single destination among the computer units and it is useful
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for constructing a common bus system. A decoder with an enable input can function as a demultiplexer. ADemultiplexer is a circuit that receives information on a single line and transmits this information on one of
2
n
possible output lines. The selection of specific output line is controlled by the bit values of n selection
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lines. The decoder and demultiplexer operations are obtained from the same circuit; a decoder with anenable input is referred to as a decoder / de-multiplexer. The Strobe lead can be used to active or de-
active the entire IC, allowing time for the address lines to change the information is fed to the output.
Demultiplexers are useful anytime information from one source must be fed several places.
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45 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
4 X 1 MULTIPLEXERCIRCUIT DIAGRAM:
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46 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
1X4 DEMULTIPLEXER
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
CIRCUIT DIAGRAM:
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47 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Result:
The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth tables
were verified.
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Outcome:
At the completion of an experiment student will able to design the multiplexer and the
demultiplexer
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1. What is multiplexer?
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2. What is demultiplexer?3. What are the advantages of multiplexer?
4. What are the advantages of demultiplexer?
5. What is select signal?
6. How to choose select signal in multiplexer?
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7. How to choose select signal in demultiplexer?8. Write the formula used in select signal.
9. What is the difference between the multiplexer and demultiplexer?
10. What is the application of multiplexer?
11. What is the application of demultiplexer?
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12. Draw the truth table of multiplexer.13. Draw the truth table of demultiplexer.
14. How many select signals are needed in 8*1 multiplexer?
15. How many select signals are needed in 8*1 demultiplexer?
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Viva ? Voce
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48 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
EXP NO: 11 SHIFT REGISTER
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Aim:
To design and implement the various shift register
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Apparatus required:Sl. No Name of the Apparatus Range Quantity
1. D flip flop IC 7474 2
2. OR gate IC 7432 1
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3. IC Trainer kit 15. Connecting wires As required
Theory:
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A register is capable of shifting its binary information in one or both directions isknown as shift register. The logical configuration of shift register consist of a D-Flip flop
cascaded with output of one flip flop connected to input of next flip flop. All flip flops receive
common clock pulses which causes the shift in the output of the flip flop.The simplest possible
shift register is one that uses only flip flop. The output of a given flip flop is connected to the
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input of next flip flop of the register. Each clock pulse shifts the content of register one bit positionto right.
PIN Diagram:
Logic Diagram:
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SERIAL IN SERIAL OUT--- Content provided by FirstRanker.com ---
49 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth Table:CLK Serial in Serial out
1 1 0
2 0 0
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3 0 04 1 1
5 X 0
6 X 0
7 X 1
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Logic Diagram:
Serial in parallel out:
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Truth Table:
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CLK DATAOUTPUT
Q
A
Q
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BQ
C
Q
D
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1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1
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Parallel in Serial Out:
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50 Format No.FirstRanker/stud/LM/34/issue:00/revision:00CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
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2 0 0 0 0 03 0 0 0 0 1
Truth Table:
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Parallel in Parallel Out:
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PARALLEL IN PARALLEL OUT:
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Truth Table:
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Procedure:
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1. Connections are given as per circuit diagram
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
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Result:Thus the implementation of shift registers using flip flops was completed successfully.
Outcome:
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At the completion of an experiment student will able to design the various types of shift register.--- Content provided by FirstRanker.com ---
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CLK
DATA INPUT OUTPUT
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DA D
B D
C D
D Q
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A QB Q
C Q
D
1 1 0 0 1 1 0 0 1
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2 1 0 1 0 1 0 1 051 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.12: SYNCHRONOUS UP/DOWN COUNTER
Aim:
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To design and implement 3 bit synchronous up/down counterApparatus required:
S.No Name of the Apparatus Range Quantity
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1. JK Flip Flop IC 7474 22. OR gate IC 7432 1
3. NOT gate IC 7404 1
4. AND gate ( three input ) IC 7411 1
5 XOR gate IC 7486 1
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6 IC Trainer Kit 17. Connecting wires As required
Theory:
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A counter is a register capable of counting number of clock pulse arriving at its clock input.
Counter represents the number of clock pulses arrived. An up/down counter is one that is capable of
progressing in increasing order or decreasing order through a certain sequence. An up/down counter
is also called bidirectional counter. Usually up/down operation of the counter is controlled by up/down
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signal. When this signal is high counter goes through up sequence and when up/down signal is low counterfollows reverse sequence.
K map:
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52 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Q Q
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t+1 J K0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
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State Diagram:
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Characteristic Table:
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Logic Diagram:
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53 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Input
Up/Down
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PresentState
Q
A
Q
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BQ
C
Next State
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QA+1
Q
B+1
Q
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C+1A
J
A
K
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AB
J
B
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KB
C
J
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CK
C
0 0 0 0 1 1 1 1 X 1 X 1 X
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0 1 1 1 1 1 0 X 0 X 0 X 10 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
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0 0 1 0 0 0 1 0 X X 1 1 X0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
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1 0 1 1 1 0 0 1 X X 1 X 11 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1
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Truth Table:
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Procedure:
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1. Connections are given as per circuit diagram.2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
Result:
Thus the 3-bit synchronous up/down counters was implemented successfully.
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Outcome:At the completion of an experiment student will able to design the synchronous up/down counter.
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54 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.12:
SIMULATION OF COMBINATIONAL CIRCUITS USING HDL
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Aim:To write a verilog code for half adder, full adder and multiplexer
Tools Required:
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Xilinx 9.2Program:
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Simulation wave for half adder
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55 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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MULTIPLEXER:--- Content provided by FirstRanker.com ---
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Procedure:
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1. Write and draw the Digital logic system.
2. Write the Verilog code for above system.
3. Enter the Verilog code in Xilinx software.
4. Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and verify the
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output waveform as obtained.5. Implement the above code in Spartan III using FPGA kit.
Result:
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Thus the verilog code for half adder, full adder and multiplexer were simulated and verifiedsuccessfully.
Outcome:
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At the completion of an experiment student will able to be known the verilog code for half adder,full adder and multiplexer.
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56 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.13:
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SIMULATION OF SEQUENTIAL CIRCUITS USING HDLAim:
To write a verilog code for RS, D, JK flip flop and up counter
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Tools required:
Xilinx 9.2
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Program:RS Flip Flop:
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D Flip Flop:--- Content provided by FirstRanker.com ---
57 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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JK Flip Flop:
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Up Counter:--- Content provided by FirstRanker.com ---
58 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Result:
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Thus the verilog code for RS,D,JK Filp Flop and up counter were simulated and verified
successfully.
Outcome:
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At the completion of an experiment student will able to be known the verilog code for RS, D, JK
Filp Flop and up counter .
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FirstRanker.com - FirstRanker's Choice
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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
?DEPARTMENT OF
--- Content provided by FirstRanker.com ---
COMPUTER SCIENCE ENGINEERINGIII SEMESTER - R 2017
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
Section : _______________________________________
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LABORATORY MANUAL
--- Content provided by FirstRanker.com ---
2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious andenterprising professionals conforming to global standards through value based quality education and
training.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
--- Content provided by FirstRanker.com ---
levels? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
--- Content provided by FirstRanker.com ---
Electrical and Electronics Engineers.--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?sneeds.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
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concepts with strongly supported laboratory and prepare them to meet the global needs of theindustry by continuous assessment and training.
VISION
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MISSION
VISION
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MISSION--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
--- Content provided by FirstRanker.com ---
1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
--- Content provided by FirstRanker.com ---
2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
technologies.
--- Content provided by FirstRanker.com ---
3. BreadthTo provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
development of society.
--- Content provided by FirstRanker.com ---
4. ProfessionalismTo inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
--- Content provided by FirstRanker.com ---
5. Lifelong Learning/EthicsTo practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PROGRAM OUTCOMES (POs)
--- Content provided by FirstRanker.com ---
a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
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e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
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i. Graduates will show the understanding of impact of engineering solutions on the society and alsowill be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
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CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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SYLLABUSObjectives:
The student should be made to:
? Understand the various logic gates.
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? Be familiar with various combinational circuits.? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
? Learn to use HDL
List of experiments:
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1. Verification of Boolean Theorems using basic gates.2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
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b. Parity generator / checkerc. Magnitude Comparator
d. Application using multiplexers
4. Design and implementation of sequential circuits:
a. Shift ?registers
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b. Synchronous and asynchronous counters5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
Course Outcomes:
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? Use Boolean simplification techniques to design a combinational hardware circuit.? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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ContentSl.No. Name of the Experiment Page No.
1.
Verification of Boolean Theorems using Digital Logic Gates
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2.Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
3.
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Implementation of half adder and full adder4.
Implementation of half subtractor and full subtractor
5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
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MSI Devices6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
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7.
Design and Implementation of Magnitude Comparator.
8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
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9.Design and Implementation of Shift Registers.
10.
Design and Implementation of Synchronous and Asynchronous Counters.
11.
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Simulation of Combinational Circuits using Hardware Description Language (VHDL / VerilogHDL Software Required).
12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.1: STUDY OF BASIC GATES
Aim:
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To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gatesApparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
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6. NOR gate IC 7402 17. EX-OR gate IC 7486 1
8. Connecting wires As required
Theory:
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Circuit that takes the logical decision and the process are called logic gates. Each gate has one ormore input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
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output is high when both the inputs are high. The output is low level when any one of the inputs islow.
OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
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NOT gateA NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
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and any one of the input is low .The output is low level when both inputs are high.NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
EX-OR gate
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An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It issimilar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
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1. Connections are given as per the circuit diagram.2. For all the IC?s 7
th
pin is grounded and 14
th
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pin is given +5 supply.3. Apply the inputs and verify the truth table for all gates.
Result:
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The truth tables of all the basic logic gates were verified.
Outcome:
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At the completion of an experiment student will able to verify the truthtable of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
3. How many gates presented in IC 7408?
4. What is IC?
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5. What are the applications of gates?6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
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10. Write the truth table of NOR gate.11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
13. What are types of linear integrated circuit?
14. What is meant by etching?
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15. What are the advantages of IC?16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.2:
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VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gatesApparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
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6. NOR gate IC 7402 37. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:BASIC Boolean Laws
1. Commutative Law
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The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A
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2. Associative LawThe binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
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3. Distributive Law
The binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
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2. A.(B+C) = (A.B)+(A.C)4. Absorption Law
1. A+AB = A
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:005. Idempotent Law
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1. A+A = A
2. A.A = A
6. Complementary Law
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1. A+A' = 1
2. A.A' = 0
7. De Morgan ?s Theorem
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1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
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A.B = A+BDesign
1. Absorption Law
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A+AB = A
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2. Involution (or) Double complement Law
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A = A
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3. Idempotent Law1. A+A = A
2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
A+B = A.B
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5. Distributive Law
A+(B.C) = (A+B).(A+C)
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Procedure:1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
cc
.
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3. Apply the inputs to the respective input pins.4. Verify the output with the truth table.
Result:
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Thus the above stated Boolean laws are verified.
Outcome:
At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?
2. What is associative law?
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3. What is mean by compliment gate?4. Explain the basic laws in digital electronics
5. What is double complement?
Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
To design and verify the truth table of the Half Adder & Full Adder circuits
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Apparatus required:S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:
The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
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0 + 0 = 00 + 1 = 1
1 + 0 = 1
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1 + 1 = 0 (with 1 as carry)
The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
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significant bit is called the sum.Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
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Full adder:A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
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From the truth table, the expression for sum and carry bits of the output can be obtained as,SUM = A?B?C + A?BC? + AB?C? + ABC
CARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half AdderTruth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,S = A B
Carry, C = A . B
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Circuit diagram:
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Full adderTruth table:
Sl.No. Input Output
A B C S C
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1. 0 0 0 0 02. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
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6. 1 0 1 0 17. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input OutputA B S C
1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
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4. 1 1 1 117 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:
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CARRY = AB + AC + BCLogic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
th
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pin is grounded and 14th
pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
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Result:The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to design the half adder circuit and thefull adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
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Aim:To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
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6. Connecting wires As requiredTheory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
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subtrahend bit, hence 1 is borrowed.Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
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difference and borrow bits.Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
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From the truth table the expression for difference and borrow bits of the output can be obtained
as,
Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
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Borrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Half subtractor
Truth table:
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Sl.No. Input Output
A B Difference Borrow
1. 0 0 0 0
2. 0 1 1 1
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3. 1 0 1 04. 1 1 0 0
From the truth table the expression for difference and borrow bits of the output can be obtained as,
--- Content provided by FirstRanker.com ---
Difference, DIFF = A BBorrow, BORR = A?. B
Logic diagram:
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--- Content provided by FirstRanker.com ---
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2. Full subtractor
Truth table:
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Sl.No.Input Output
A B C Difference Borrow
1. 0 0 0 0 0
2. 0 0 1 1 1
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3. 0 1 0 1 14. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
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8. 1 1 1 1 1--- Content provided by FirstRanker.com ---
21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
--- Content provided by FirstRanker.com ---
Difference--- Content provided by FirstRanker.com ---
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Difference = A?B?C + A?BC? + AB?C? + ABCBorrow
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--- Content provided by FirstRanker.com ---
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Borrow = A?B + A?C + BC
Circuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.5: 4-BIT ADDER AND SUBTRACTORAim:
To design and implement 4-bit adder and subtractor using IC 7483
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. IC IC 7483 13. NOT gate IC 7404 1
4. EX-OR gate IC 7486 1
5. Connecting wires As required
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Theory:4 BIT Binary adder:
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
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constructed with full adders connected in cascade, with the output carry from each full adder connected tothe input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
0
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and it ripples throughthe full adder to the output carry C
4
.
4 BIT Binary subtractor:
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The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
?B? and the corresponding input of full adder. The input carry C
0
must be equal to 1 when performing
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subtraction.4 BIT Binary adder / subtractor:
The addition and subtraction operation can be combined into one circuit with one common binary
adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
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becomes subtractor.23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PIN Diagram for IC 7483:
Logic Diagram: 4-Bit Binary Diagram:
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Logic diagram: 4-Bit Binary Subtractor:4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:--- Content provided by FirstRanker.com ---
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Procedure:1. Connections are given as per the circuit diagrams.
2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
.
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Result:The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
verified.
Outcome:
At the completion of an experiment student will able to design 4-bit binary adder and subtractor
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Input Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
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0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 00 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?2. Write the truth table for half adder.
3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
5. Write the truth table for full subtrator.
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6. Draw the logic diagram of full subtrator.7. What is adder?
8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
10. What is combinational circuit?
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11. What is different between combinational and sequential circuit?12. What are the gates involved for binary adder?
13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.6: MAGNITUDE COMPARATOR
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Aim:To design, construct and study the performance of 2 bit magnitude comparator
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
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7. Connecting wires As requiredTheory:
The comparison of two numbers is an operator that determines one number is greater than, less
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than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares twonumbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
three binary variables that indicate whether A>B, A=B (or) A
Truth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Logic Diagram:
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Pin Diagram for IC 7485:
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:
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Truth table:
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Procedure:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
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Result:
Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
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Outcome:At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
comparator using logic gates.
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--- Content provided by FirstRanker.com ---
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A B A>B A=B A0 0 0 0
0 0 0 0
0 0 0 0
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0 0 0 00 1 0
0 0 0 1
0 0 0 1
0 0 0 0
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0 0 0 01 0 0
0 0 0 0
0 0 0 0
0 0 0 1
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0 0 0 10 0 1
Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is magnitude comparator?
2. What is most significant bit?
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3. Explain operation of AND gate.4. Explain truth table of a comparator.
5. Explain magnitude comparator7485 IC.
6. What is 8-bit input Magnitude Comparator?
7. What is IC?
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8. Explain the k-map simplification of A>B.9. Explain the k-map simplification of A=B.
10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
12. What is the truth table of 1-bit magnitude comparator?
13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION
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31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Aim:
To design, construct and study the performance of 4-bit different code converters
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(i) Binary to gray code converter(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:
The availability of large variety of codes for the same discrete elements of information results in
the use of different codes by different systems. A conversion circuit must be inserted between the two
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systems if each uses different codes for same information. Thus, code converter is a circuit that makes thetwo systems compatible even though each uses different binary code. The bit combination assigned to
binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
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designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is acircuit that makes the two systems compatible even though each uses a different binary code. To convert
from binary code to Excess-3 code, the input lines must supply the bit combination of elements as
specified by code and the output lines generate the corresponding bit combination of code. Each one of the
four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
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level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These arevarious other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is
C+D has been used to implement partially each of three outputs.
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Logic diagram:
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32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00(i) Binary to gray code converter
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Logic Diagram:K map for G3:
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G3 = B3
K map for G2:
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K map for G1:
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33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
K map for G0:
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Truth table:0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
0
0
0
0
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
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11
0
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(ii) Gray to binary code converter
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34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:
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K map for B3:B3=G3
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K map for B2:--- Content provided by FirstRanker.com ---
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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G3 G2 G1 G0 B3 B2 B1 B00
0
0
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00
0
0
0
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11
1
1
1
--- Content provided by FirstRanker.com ---
11
1
0
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00
0
1
1
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11
1
1
1
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10
0
0
0
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0
0
1
1
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11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
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00
0
0
0
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00
0
1
1
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11
1
1
1
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10
0
0
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01
1
1
1
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00
0
0
1
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11
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
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11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
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0
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
K map for B1:
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K map for B0:
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Truth table:--- Content provided by FirstRanker.com ---
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(iii) BCD to excess-3 code converter
Logic Diagram:
--- Content provided by FirstRanker.com ---
K map for E3:
E3 = B3 + B2 (B0 + B1)
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K map for E2:
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for E1:
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K map for E0:
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Truth table:
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(iv) Excess-3 to
B3 B2 B1 B0 G3 G2 G1 G0
0
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00
0
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
0
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
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10
0
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--- Content provided by FirstRanker.com ---
00
1
1
1
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11
x
x
x
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xx
x
0
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11
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00
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1
x
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xx
x
x
x
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1
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1
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10
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0x
x
x
x
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xx
1
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10
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01
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x
x
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xx
x
x
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38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
BCD code converter
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Logic Diagram:
K map for A:
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A = X1 X2 + X3 X4 X1
K map for B:
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39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for C:
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K map for D:
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Truth table:
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B3 B2 B1 B0 G3 G2 G1 G0
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0
0
0
0
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01
1
1
1
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10
1
1
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11
0
0
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01
1
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01
1
0
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11
0
1
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01
0
1
0
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10
1
0
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00
0
0
0
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00
0
1
1
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0
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0
0
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11
1
1
0
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00
0
1
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10
0
1
1
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00
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1
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01
0
1
0
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10
1
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40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections were given as per circuit diagram.
2. Logical inputs were given as per truth table
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3. Observe the logical output and verify with the truth tables.Result:
Thus the code converters were designed and verified using the corresponding truth table.
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Outcome:At the completion of an experiment student will able to design the binary to gray converter.
1. What is binary code?
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2. What is gray code?3. What are the advantages of gray code?
4. What is unit distance code?
5. What is sequential code?
6. How to convert binary to gray code?
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7. How to convert gray to binary code?8. What is reflective code?
9. What are the advantages of EX ? 3 code?
10. Which code is used to arithmetic operation in digital circuits?
11. Explain the operation of EX ? OR.
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12. What is K ? Map?13. Draw the truth table of EX- OR gate.
14. What is SOP?
15. What is POS?
16. What is minterm?
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Viva ? Voce
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41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.8: PARITY GENERATORS AND CHECKERS
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Aim:To implement the odd and even parity checkers using the logic gates and also to generate the odd parity
and even parity numbers using the generators
Apparatus required:
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Sl. No Component Type Quantity
1 Trainer Kit - 1
2 EX-OR IC7486 1
3 NOT gate IC 7404 1
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4 Connecting wires - RequiredTheory:
Parity checking is used for error detection in data transmission.
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Odd parity checkers:It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
odd.
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Even parity checker:It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
even.
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Odd parity generators:It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also
the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bits
which is an odd parity number.
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Even parity generator:It generates an even parity number. The even parity checker circuit is used with the inverted output and
also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5
bits which is an even parity number.
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42 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Truth table:
Input Checker output Generator output
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A B C D D odd even odd even0 0 0 1 1 0 00010 00011
0 0 1 0 1 0 00100 00101
0 0 1 1 0 1 00111 00110
0 1 0 0 1 0 01000 01001
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0 1 0 1 0 1 01011 010100 1 1 0 0 1 01101 01100
0 1 1 1 1 0 01110 01111
1 0 0 0 1 0 10000 10001
1 0 0 1 0 1 10011 10010
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1 0 1 0 0 1 10101 101001 0 1 1 1 0 10110 10111
1 1 0 0 0 1 11001 11000
1 1 0 1 1 0 11010 11011
1 1 1 0 1 0 11100 11101
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1 1 1 1 0 1 11111 11110Procedure:
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1. The circuit is implemented using logic gates.2. The inputs are given as per the truth table.
3. The corresponding outputs are noted.
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4. The theoretical and practical values were verified.
Result:
The odd and even parity checkers are implemented using the logic gates and the odd parity and
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even parity numbers are generated using the corresponding generators.Outcome:
At the completion of an experiment student will able to verify the odd and even parity checker
using logic gates.
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43 Format No.FirstRanker/stud/LM/34/issue:00/revision:001. What is parity bit?
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2. Why parity bit is added to message?
3. What is parity checker?
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4. What is odd parity?5. What is even parity?
6. What are the gates involved for parity generator?
7. List the procedures to convert gray code into binary.
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8. Why weighted code is called as reflective codes?9. What is a sequential code?
10. What is error deducting code?
11. What is ASCII code?
12. What is hamming code?
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13. List the binary weighted code.14. List the binary non weighted code.
15. Write the hamming code equation
16. List the procedures to convert binary code into gray
17. What are the applications of gray code?
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18. What are the applications of Excess- 3 code?Viva ? Voce
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44 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.9: MULTIPLEXER AND DEMULTIPLEXER
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Aim:To design and verify the truth table of a 4X1 multiplexer & 1X4 demultiplexer
Apparatus required:
Sl. No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. OR gate IC 7432 1
3. NOT gate IC 7404 1
4. AND gate ( three input ) IC 7411 1
5. Connecting wires As required
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Theory:
Multiplexing means transmitting a large number of information units over a smaller number of channels or
lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input
lines and directs it to a single output line. The selection of particular input line is controlled by a set of
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selection lines. Normally, there are 2n
input lines and n selection lines whose bit combinations determines
which input is selected. A multiplexer is called a data selector, since it selects one of many inputs and
steers the binary information to the output line. A Strobe is also provided to allow the designer to disable all
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output data until a specified time. Then, by allowing the STROBE to go low, the proper lead can beselected. This feature is very useful where data might be changing the same time DATA SELECT leads
change. It is a very useful Medium Scale Integration (MSI) function and has a multitude of applications. It is
used for connecting two or more sources to a single destination among the computer units and it is useful
for constructing a common bus system. A decoder with an enable input can function as a demultiplexer. A
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Demultiplexer is a circuit that receives information on a single line and transmits this information on one of2
n
possible output lines. The selection of specific output line is controlled by the bit values of n selection
lines. The decoder and demultiplexer operations are obtained from the same circuit; a decoder with an
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enable input is referred to as a decoder / de-multiplexer. The Strobe lead can be used to active or de-active the entire IC, allowing time for the address lines to change the information is fed to the output.
Demultiplexers are useful anytime information from one source must be fed several places.
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45 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
4 X 1 MULTIPLEXER
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CIRCUIT DIAGRAM:
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46 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1X4 DEMULTIPLEXER--- Content provided by FirstRanker.com ---
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CIRCUIT DIAGRAM:--- Content provided by FirstRanker.com ---
47 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Result:
The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth tables
were verified.
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Outcome:At the completion of an experiment student will able to design the multiplexer and the
demultiplexer
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1. What is multiplexer?
2. What is demultiplexer?
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3. What are the advantages of multiplexer?4. What are the advantages of demultiplexer?
5. What is select signal?
6. How to choose select signal in multiplexer?
7. How to choose select signal in demultiplexer?
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8. Write the formula used in select signal.9. What is the difference between the multiplexer and demultiplexer?
10. What is the application of multiplexer?
11. What is the application of demultiplexer?
12. Draw the truth table of multiplexer.
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13. Draw the truth table of demultiplexer.14. How many select signals are needed in 8*1 multiplexer?
15. How many select signals are needed in 8*1 demultiplexer?
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Viva ? Voce
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48 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
EXP NO: 11 SHIFT REGISTER
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Aim:To design and implement the various shift register
Apparatus required:
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Sl. No Name of the Apparatus Range Quantity
1. D flip flop IC 7474 2
2. OR gate IC 7432 1
3. IC Trainer kit 1
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5. Connecting wires As requiredTheory:
A register is capable of shifting its binary information in one or both directions is
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known as shift register. The logical configuration of shift register consist of a D-Flip flopcascaded with output of one flip flop connected to input of next flip flop. All flip flops receive
common clock pulses which causes the shift in the output of the flip flop.The simplest possible
shift register is one that uses only flip flop. The output of a given flip flop is connected to the
input of next flip flop of the register. Each clock pulse shifts the content of register one bit position
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to right.PIN Diagram:
Logic Diagram:
SERIAL IN SERIAL OUT
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49 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Truth Table:
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CLK Serial in Serial out
1 1 0
2 0 0
3 0 0
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4 1 15 X 0
6 X 0
7 X 1
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Logic Diagram:
Serial in parallel out:
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Truth Table:
CLK DATA
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OUTPUTQ
A
Q
B
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QC
Q
D
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1 1 1 0 0 02 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1
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Parallel in Serial Out:
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50 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
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3 0 0 0 0 1Truth Table:
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Parallel in Parallel Out:
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PARALLEL IN PARALLEL OUT:
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Truth Table:
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Procedure:
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1. Connections are given as per circuit diagram2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
Result:
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Thus the implementation of shift registers using flip flops was completed successfully.
Outcome:
At the completion of an experiment student will able to design the various types of shift register.
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CLK
DATA INPUT OUTPUT
D
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A DB D
C D
D Q
A Q
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B QC Q
D
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
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51 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.12: SYNCHRONOUS UP/DOWN COUNTERAim:
To design and implement 3 bit synchronous up/down counter
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Apparatus required:
S.No Name of the Apparatus Range Quantity
1. JK Flip Flop IC 7474 2
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2. OR gate IC 7432 13. NOT gate IC 7404 1
4. AND gate ( three input ) IC 7411 1
5 XOR gate IC 7486 1
6 IC Trainer Kit 1
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7. Connecting wires As requiredTheory:
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A counter is a register capable of counting number of clock pulse arriving at its clock input.Counter represents the number of clock pulses arrived. An up/down counter is one that is capable of
progressing in increasing order or decreasing order through a certain sequence. An up/down counter
is also called bidirectional counter. Usually up/down operation of the counter is controlled by up/down
signal. When this signal is high counter goes through up sequence and when up/down signal is low counter
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follows reverse sequence.K map:
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52 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Q Q
t+1 J K
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0 0 0 X0 1 1 X
1 0 X 1
1 1 X 0
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State Diagram:--- Content provided by FirstRanker.com ---
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Characteristic Table:
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Logic Diagram:
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53 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Input
Up/Down
Present
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StateQ
A
Q
B
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QC
Next State
Q
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A+1Q
B+1
Q
C+1
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AJ
A
K
A
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B
J
B
K
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BC
J
C
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KC
0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
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0 1 1 0 1 0 1 X 0 X 1 1 X0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
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0 0 0 1 0 0 0 0 X 0 X X 11 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
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1 1 0 0 1 0 1 X 0 0 X 1 X1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1
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Truth Table:
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Procedure:
1. Connections are given as per circuit diagram.
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2. Logical inputs are given as per circuit diagram.3. Observe the output and verify the truth table.
Result:
Thus the 3-bit synchronous up/down counters was implemented successfully.
Outcome:
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At the completion of an experiment student will able to design the synchronous up/down counter.
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54 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.12:SIMULATION OF COMBINATIONAL CIRCUITS USING HDL
Aim:
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To write a verilog code for half adder, full adder and multiplexer
Tools Required:
Xilinx 9.2
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Program:
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Simulation wave for half adder
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55 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
MULTIPLEXER:
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Procedure:
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1. Write and draw the Digital logic system.2. Write the Verilog code for above system.
3. Enter the Verilog code in Xilinx software.
4. Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and verify the
output waveform as obtained.
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5. Implement the above code in Spartan III using FPGA kit.Result:
Thus the verilog code for half adder, full adder and multiplexer were simulated and verified
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successfully.Outcome:
At the completion of an experiment student will able to be known the verilog code for half adder,
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full adder and multiplexer.--- Content provided by FirstRanker.com ---
56 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.13:
SIMULATION OF SEQUENTIAL CIRCUITS USING HDL
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Aim:
To write a verilog code for RS, D, JK flip flop and up counter
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Tools required:Xilinx 9.2
Program:
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RS Flip Flop:
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D Flip Flop:
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57 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
JK Flip Flop:
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Up Counter:
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58 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Result:
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Thus the verilog code for RS,D,JK Filp Flop and up counter were simulated and verifiedsuccessfully.
Outcome:
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At the completion of an experiment student will able to be known the verilog code for RS, D, JKFilp Flop and up counter .
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59 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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ADDITIONAL EXPERIMENTS
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FirstRanker.com - FirstRanker's Choice
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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OFCOMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
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CS8382 DIGITAL SYSTEMS LABORATORY--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
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Section : _______________________________________--- Content provided by FirstRanker.com ---
LABORATORY MANUAL2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
training.
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? To provide competent technical manpower capable of meeting requirements of the industry
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? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at differentlevels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
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DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
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Engineering and thereby produce extremely well trained employable, socially responsible and innovativeElectrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
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? To provide highest quality learning environment for the students emphasizing fundamentalconcepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
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VISIONMISSION
VISION
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MISSION
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3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM EDUCATIONAL OBJECTIVES (PEOs)1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
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engineering enabling them to solve complex problems in order to develop real time applications.2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
technologies.
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3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
development of society.
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4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
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5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
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d. Graduates will be able to design a system, component or process as per needs and specifications.e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
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h. Graduates will be able to communicate effectively by both verbal and written form.i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
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CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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SYLLABUS
Objectives:
The student should be made to:
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? Understand the various logic gates.? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
? Learn to use HDL
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List of experiments:1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
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a. 4 ? bit binary adder / subtractorb. Parity generator / checker
c. Magnitude Comparator
d. Application using multiplexers
4. Design and implementation of sequential circuits:
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a. Shift ?registersb. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
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Course Outcomes:? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
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? Design and Implement a simple digital system.--- Content provided by FirstRanker.com ---
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Content
Sl.No. Name of the Experiment Page No.
1.
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Verification of Boolean Theorems using Digital Logic Gates2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
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3.Implementation of half adder and full adder
4.
Implementation of half subtractor and full subtractor
5.
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Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates andMSI Devices
6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
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Devices7.
Design and Implementation of Magnitude Comparator.
8.
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Design and Implementation of Application using Multiplexers / Demultiplexers.9.
Design and Implementation of Shift Registers.
10.
Design and Implementation of Synchronous and Asynchronous Counters.
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11.Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
12.
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Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).--- Content provided by FirstRanker.com ---
7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.1: STUDY OF BASIC GATES
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Aim:To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. NAND gate IC 7400 16. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND gate
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The AND gate performs a logical multiplication commonly known as AND function. Theoutput is high when both the inputs are high. The output is low level when any one of the inputs is
low.
OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
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high when any one of the inputs is high. The output is low level when both the inputs are low.NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
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The NAND gate is a contraction of AND-NOT. The output is high when both inputs are lowand any one of the input is low .The output is low level when both inputs are high.
NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
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EX-OR gateAn Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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AND Gate Symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
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OR Gate:--- Content provided by FirstRanker.com ---
OR GATE:--- Content provided by FirstRanker.com ---
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00NAND Gate symbol: PIN Diagram:
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NOR Gate:--- Content provided by FirstRanker.com ---
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
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1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
th
pin is grounded and 14
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thpin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
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Result:The truth tables of all the basic logic gates were verified.
Outcome:
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At the completion of an experiment student will able to verify the truth
table of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
3. How many gates presented in IC 7408?
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4. What is IC?5. What are the applications of gates?
6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
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9. Write the truth table of NAND gate.10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
13. What are types of linear integrated circuit?
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14. What is meant by etching?15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.2:VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gates
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. NAND gate IC 7400 16. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
BASIC Boolean Laws
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1. Commutative LawThe binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A
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2. Associative Law
The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
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2. A.(B.C) = (A.B).C3. Distributive Law
The binary operator OR, AND is said to be distributive if,
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1. A+(B.C) = (A+B).(A+C)2. A.(B+C) = (A.B)+(A.C)
4. Absorption Law
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1. A+AB = A2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law1. A+A = A
2. A.A = A
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6. Complementary Law1. A+A' = 1
2. A.A' = 0
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7. De Morgan ?s Theorem1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
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2. The complement of the product is equal to the sum of the individual complements.A.B = A+B
Design
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1. Absorption LawA+AB = A
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2. Involution (or) Double complement LawA = A
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3. Idempotent Law
1. A+A = A
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2. A.A = A--- Content provided by FirstRanker.com ---
14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
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A+B = A.B5. Distributive Law
A+(B.C) = (A+B).(A+C)
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Procedure:
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
cc
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.3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
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Result:Thus the above stated Boolean laws are verified.
Outcome:
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At the completion of an experiment student will able to know the basic laws with their truth table.1. What is Demorgan?s law?
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2. What is associative law?3. What is mean by compliment gate?
4. Explain the basic laws in digital electronics
5. What is double complement?
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Viva ? Voce--- Content provided by FirstRanker.com ---
15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
To design and verify the truth table of the Half Adder & Full Adder circuits
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Apparatus required:
S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:
The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
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0 + 0 = 0
0 + 1 = 1
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1 + 0 = 11 + 1 = 0 (with 1 as carry)
The first three operations produce a sum of whose length is one digit, but when the last operation is
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performed the sum is two digits. The higher significant bit of this result is called a carry and lowersignificant bit is called the sum.
Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
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Full adder:
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
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From the truth table, the expression for sum and carry bits of the output can be obtained as,
SUM = A?B?C + A?BC? + AB?C? + ABC
CARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half Adder
Truth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
S = A B
Carry, C = A . B
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Circuit diagram:
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Full adder
Truth table:
Sl.No. Input Output
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A B C S C1. 0 0 0 0 0
2. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
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5. 1 0 0 1 06. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input Output
A B S C
1. 0 0 0 0
2. 0 1 1 0
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3. 1 0 1 04. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:
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CARRY = AB + AC + BC
Logic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
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thpin is grounded and 14
th
pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
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Result:
The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
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At the completion of an experiment student will able to design the half adder circuit and the
full adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
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Aim:
To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. EX-OR gate IC 7486 16. Connecting wires As required
Theory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
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is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than thesubtrahend bit, hence 1 is borrowed.
Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
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variables designate the minuend and the subtrahend bit, whereas the output variables produce thedifference and borrow bits.
Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
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implemented with two half subtractors and one OR gate.From the truth table the expression for difference and borrow bits of the output can be obtained
as,
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Difference, DIFF= A?B?C + A?BC? + AB?C? + ABCBorrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half subtractor
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Truth table:Sl.No. Input Output
A B Difference Borrow
1. 0 0 0 0
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2. 0 1 1 13. 1 0 1 0
4. 1 1 0 0
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From the truth table the expression for difference and borrow bits of the output can be obtained as,Difference, DIFF = A B
Borrow, BORR = A?. B
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Logic diagram:--- Content provided by FirstRanker.com ---
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2. Full subtractor
Truth table:
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Sl.No.
Input Output
A B C Difference Borrow
1. 0 0 0 0 0
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2. 0 0 1 1 13. 0 1 0 1 1
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 0
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7. 1 1 0 0 08. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
Borrow
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Borrow = A?B + A?C + BC
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Circuit diagram:--- Content provided by FirstRanker.com ---
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
Aim:
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To design and implement 4-bit adder and subtractor using IC 7483Apparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. IC IC 7483 1
3. NOT gate IC 7404 1
4. EX-OR gate IC 7486 1
5. Connecting wires As required
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Theory:
4 BIT Binary adder:
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A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can beconstructed with full adders connected in cascade, with the output carry from each full adder connected to
the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
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0and it ripples through
the full adder to the output carry C
4
.
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4 BIT Binary subtractor:The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
?B? and the corresponding input of full adder. The input carry C
0
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must be equal to 1 when performingsubtraction.
4 BIT Binary adder / subtractor:
The addition and subtraction operation can be combined into one circuit with one common binary
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adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, itbecomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PIN Diagram for IC 7483:
Logic Diagram: 4-Bit Binary Diagram:
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Logic diagram: 4-Bit Binary Subtractor:
4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:
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Procedure:
1. Connections are given as per the circuit diagrams.
2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
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.Result:
The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
verified.
Outcome:
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At the completion of an experiment student will able to design 4-bit binary adder and subtractorInput Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
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1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 00 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
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1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 125 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?
2. Write the truth table for half adder.
3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
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5. Write the truth table for full subtrator.6. Draw the logic diagram of full subtrator.
7. What is adder?
8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
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10. What is combinational circuit?11. What is different between combinational and sequential circuit?
12. What are the gates involved for binary adder?
13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.6: MAGNITUDE COMPARATOR
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Aim:
To design, construct and study the performance of 2 bit magnitude comparator
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
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6. EX-OR gate IC 7486 17. Connecting wires As required
Theory:
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The comparison of two numbers is an operator that determines one number is greater than, lessthan (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
three binary variables that indicate whether A>B, A=B (or) A
Truth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Logic Diagram:
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Pin Diagram for IC 7485:
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Logic Diagram:29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:Truth table:
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Procedure:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
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3. Observe the output and verify the truth table.Result:
Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
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Outcome:
At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
comparator using logic gates.
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A B A>B A=B A0 0 0 0
0 0 0 0
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0 0 0 00 0 0 0
0 1 0
0 0 0 1
0 0 0 1
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0 0 0 00 0 0 0
1 0 0
0 0 0 0
0 0 0 0
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0 0 0 10 0 0 1
0 0 1
Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is magnitude comparator?
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2. What is most significant bit?3. Explain operation of AND gate.
4. Explain truth table of a comparator.
5. Explain magnitude comparator7485 IC.
6. What is 8-bit input Magnitude Comparator?
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7. What is IC?8. Explain the k-map simplification of A>B.
9. Explain the k-map simplification of A=B.
10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
12. What is the truth table of 1-bit magnitude comparator?
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13. What is the use of magnitude comparator?--- Content provided by FirstRanker.com ---
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Expt.No.7: CODE CONVERSION
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31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Aim:
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To design, construct and study the performance of 4-bit different code converters(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
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7. Connecting wires As requiredTheory:
The availability of large variety of codes for the same discrete elements of information results in
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the use of different codes by different systems. A conversion circuit must be inserted between the twosystems if each uses different codes for same information. Thus, code converter is a circuit that makes the
two systems compatible even though each uses different binary code. The bit combination assigned to
binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
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and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit isdesigned. The Boolean functions are obtained from K-Map for each output variable. A code converter is a
circuit that makes the two systems compatible even though each uses a different binary code. To convert
from binary code to Excess-3 code, the input lines must supply the bit combination of elements as
specified by code and the output lines generate the corresponding bit combination of code. Each one of the
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four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are
various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is
C+D has been used to implement partially each of three outputs.
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Logic diagram:
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32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
(i) Binary to gray code converter
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Logic Diagram:
K map for G3:
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G3 = B3
K map for G2:
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K map for G1:
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33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for G0:
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Truth table:
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
0
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
0
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
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(ii) Gray to binary code converter34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:
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K map for B3:
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B3=G3K map for B2:
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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G3 G2 G1 G0 B3 B2 B1 B0
0
0
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00
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
0
0
0
0
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
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11
0
0
1
--- Content provided by FirstRanker.com ---
10
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
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01
0
1
0
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10
1
K map for B1:
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K map for B0:
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Truth table:
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00(iii) BCD to excess-3 code converter
Logic Diagram:
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K map for E3:
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E3 = B3 + B2 (B0 + B1)K map for E2:
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for E1:
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K map for E0:
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Truth table:
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(iv) Excess-3 to
B3 B2 B1 B0 G3 G2 G1 G0
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00
0
0
0
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00
0
1
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
0
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
1
x
x
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xx
x
x
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
xx
x
x
x
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x1
0
0
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11
0
0
1
--- Content provided by FirstRanker.com ---
10
x
x
x
--- Content provided by FirstRanker.com ---
xx
x
1
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01
0
1
0
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10
1
0
x
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xx
x
x
x
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38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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BCD code converterLogic Diagram:
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K map for A:A = X1 X2 + X3 X4 X1
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K map for B:--- Content provided by FirstRanker.com ---
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39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for C:
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K map for D:
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Truth table:
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B3 B2 B1 B0 G3 G2 G1 G00
0
0
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00
1
1
1
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11
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
0
0
0
0
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
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40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections were given as per circuit diagram.
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2. Logical inputs were given as per truth table3. Observe the logical output and verify with the truth tables.
Result:
Thus the code converters were designed and verified using the corresponding truth table.
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Outcome:
At the completion of an experiment student will able to design the binary to gray converter.
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1. What is binary code?2. What is gray code?
3. What are the advantages of gray code?
4. What is unit distance code?
5. What is sequential code?
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6. How to convert binary to gray code?7. How to convert gray to binary code?
8. What is reflective code?
9. What are the advantages of EX ? 3 code?
10. Which code is used to arithmetic operation in digital circuits?
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11. Explain the operation of EX ? OR.12. What is K ? Map?
13. Draw the truth table of EX- OR gate.
14. What is SOP?
15. What is POS?
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16. What is minterm?--- Content provided by FirstRanker.com ---
Viva ? Voce
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41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.8: PARITY GENERATORS AND CHECKERS
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Aim:
To implement the odd and even parity checkers using the logic gates and also to generate the odd parity
and even parity numbers using the generators
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Apparatus required:Sl. No Component Type Quantity
1 Trainer Kit - 1
2 EX-OR IC7486 1
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3 NOT gate IC 7404 14 Connecting wires - Required
Theory:
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Parity checking is used for error detection in data transmission.Odd parity checkers:
It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
odd.
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Even parity checker:
It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
even.
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Odd parity generators:
It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also
the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bits
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which is an odd parity number.Even parity generator:
It generates an even parity number. The even parity checker circuit is used with the inverted output and
also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5
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bits which is an even parity number.--- Content provided by FirstRanker.com ---
42 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Truth table:
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Input Checker output Generator outputA B C D D odd even odd even
0 0 0 1 1 0 00010 00011
0 0 1 0 1 0 00100 00101
0 0 1 1 0 1 00111 00110
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0 1 0 0 1 0 01000 010010 1 0 1 0 1 01011 01010
0 1 1 0 0 1 01101 01100
0 1 1 1 1 0 01110 01111
1 0 0 0 1 0 10000 10001
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1 0 0 1 0 1 10011 100101 0 1 0 0 1 10101 10100
1 0 1 1 1 0 10110 10111
1 1 0 0 0 1 11001 11000
1 1 0 1 1 0 11010 11011
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1 1 1 0 1 0 11100 111011 1 1 1 0 1 11111 11110
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Procedure:1. The circuit is implemented using logic gates.
2. The inputs are given as per the truth table.
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3. The corresponding outputs are noted.4. The theoretical and practical values were verified.
Result:
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The odd and even parity checkers are implemented using the logic gates and the odd parity andeven parity numbers are generated using the corresponding generators.
Outcome:
At the completion of an experiment student will able to verify the odd and even parity checker
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using logic gates.--- Content provided by FirstRanker.com ---
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43 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
1. What is parity bit?2. Why parity bit is added to message?
3. What is parity checker?
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4. What is odd parity?
5. What is even parity?
6. What are the gates involved for parity generator?
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7. List the procedures to convert gray code into binary.8. Why weighted code is called as reflective codes?
9. What is a sequential code?
10. What is error deducting code?
11. What is ASCII code?
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12. What is hamming code?13. List the binary weighted code.
14. List the binary non weighted code.
15. Write the hamming code equation
16. List the procedures to convert binary code into gray
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17. What are the applications of gray code?18. What are the applications of Excess- 3 code?
Viva ? Voce
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44 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.9: MULTIPLEXER AND DEMULTIPLEXER
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Aim:
To design and verify the truth table of a 4X1 multiplexer & 1X4 demultiplexer
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl. No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. OR gate IC 7432 1
3. NOT gate IC 7404 1
4. AND gate ( three input ) IC 7411 1
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5. Connecting wires As requiredTheory:
Multiplexing means transmitting a large number of information units over a smaller number of channels or
lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input
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lines and directs it to a single output line. The selection of particular input line is controlled by a set ofselection lines. Normally, there are 2
n
input lines and n selection lines whose bit combinations determines
which input is selected. A multiplexer is called a data selector, since it selects one of many inputs and
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steers the binary information to the output line. A Strobe is also provided to allow the designer to disable alloutput data until a specified time. Then, by allowing the STROBE to go low, the proper lead can be
selected. This feature is very useful where data might be changing the same time DATA SELECT leads
change. It is a very useful Medium Scale Integration (MSI) function and has a multitude of applications. It is
used for connecting two or more sources to a single destination among the computer units and it is useful
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for constructing a common bus system. A decoder with an enable input can function as a demultiplexer. ADemultiplexer is a circuit that receives information on a single line and transmits this information on one of
2
n
possible output lines. The selection of specific output line is controlled by the bit values of n selection
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lines. The decoder and demultiplexer operations are obtained from the same circuit; a decoder with anenable input is referred to as a decoder / de-multiplexer. The Strobe lead can be used to active or de-
active the entire IC, allowing time for the address lines to change the information is fed to the output.
Demultiplexers are useful anytime information from one source must be fed several places.
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45 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
4 X 1 MULTIPLEXERCIRCUIT DIAGRAM:
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46 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1X4 DEMULTIPLEXER
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--- Content provided by FirstRanker.com ---
CIRCUIT DIAGRAM:
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47 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Result:
The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth tables
were verified.
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Outcome:
At the completion of an experiment student will able to design the multiplexer and the
demultiplexer
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1. What is multiplexer?
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2. What is demultiplexer?3. What are the advantages of multiplexer?
4. What are the advantages of demultiplexer?
5. What is select signal?
6. How to choose select signal in multiplexer?
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7. How to choose select signal in demultiplexer?8. Write the formula used in select signal.
9. What is the difference between the multiplexer and demultiplexer?
10. What is the application of multiplexer?
11. What is the application of demultiplexer?
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12. Draw the truth table of multiplexer.13. Draw the truth table of demultiplexer.
14. How many select signals are needed in 8*1 multiplexer?
15. How many select signals are needed in 8*1 demultiplexer?
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Viva ? Voce
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48 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
EXP NO: 11 SHIFT REGISTER
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Aim:
To design and implement the various shift register
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Apparatus required:Sl. No Name of the Apparatus Range Quantity
1. D flip flop IC 7474 2
2. OR gate IC 7432 1
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3. IC Trainer kit 15. Connecting wires As required
Theory:
--- Content provided by FirstRanker.com ---
A register is capable of shifting its binary information in one or both directions isknown as shift register. The logical configuration of shift register consist of a D-Flip flop
cascaded with output of one flip flop connected to input of next flip flop. All flip flops receive
common clock pulses which causes the shift in the output of the flip flop.The simplest possible
shift register is one that uses only flip flop. The output of a given flip flop is connected to the
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input of next flip flop of the register. Each clock pulse shifts the content of register one bit positionto right.
PIN Diagram:
Logic Diagram:
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SERIAL IN SERIAL OUT--- Content provided by FirstRanker.com ---
49 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth Table:CLK Serial in Serial out
1 1 0
2 0 0
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3 0 04 1 1
5 X 0
6 X 0
7 X 1
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Logic Diagram:
Serial in parallel out:
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Truth Table:
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CLK DATAOUTPUT
Q
A
Q
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BQ
C
Q
D
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1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1
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Parallel in Serial Out:
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50 Format No.FirstRanker/stud/LM/34/issue:00/revision:00CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
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2 0 0 0 0 03 0 0 0 0 1
Truth Table:
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Parallel in Parallel Out:
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PARALLEL IN PARALLEL OUT:
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Truth Table:
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Procedure:
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1. Connections are given as per circuit diagram
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
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Result:Thus the implementation of shift registers using flip flops was completed successfully.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to design the various types of shift register.--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
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CLK
DATA INPUT OUTPUT
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DA D
B D
C D
D Q
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A QB Q
C Q
D
1 1 0 0 1 1 0 0 1
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2 1 0 1 0 1 0 1 051 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.12: SYNCHRONOUS UP/DOWN COUNTER
Aim:
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To design and implement 3 bit synchronous up/down counterApparatus required:
S.No Name of the Apparatus Range Quantity
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1. JK Flip Flop IC 7474 22. OR gate IC 7432 1
3. NOT gate IC 7404 1
4. AND gate ( three input ) IC 7411 1
5 XOR gate IC 7486 1
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6 IC Trainer Kit 17. Connecting wires As required
Theory:
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A counter is a register capable of counting number of clock pulse arriving at its clock input.
Counter represents the number of clock pulses arrived. An up/down counter is one that is capable of
progressing in increasing order or decreasing order through a certain sequence. An up/down counter
is also called bidirectional counter. Usually up/down operation of the counter is controlled by up/down
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signal. When this signal is high counter goes through up sequence and when up/down signal is low counterfollows reverse sequence.
K map:
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52 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Q Q
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t+1 J K0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
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State Diagram:
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Characteristic Table:
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Logic Diagram:
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53 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Input
Up/Down
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PresentState
Q
A
Q
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BQ
C
Next State
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QA+1
Q
B+1
Q
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C+1A
J
A
K
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AB
J
B
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KB
C
J
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CK
C
0 0 0 0 1 1 1 1 X 1 X 1 X
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0 1 1 1 1 1 0 X 0 X 0 X 10 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
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0 0 1 0 0 0 1 0 X X 1 1 X0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
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1 0 1 1 1 0 0 1 X X 1 X 11 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1
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Truth Table:
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Procedure:
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1. Connections are given as per circuit diagram.2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
Result:
Thus the 3-bit synchronous up/down counters was implemented successfully.
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Outcome:At the completion of an experiment student will able to design the synchronous up/down counter.
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54 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.12:
SIMULATION OF COMBINATIONAL CIRCUITS USING HDL
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Aim:To write a verilog code for half adder, full adder and multiplexer
Tools Required:
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Xilinx 9.2Program:
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Simulation wave for half adder
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55 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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MULTIPLEXER:--- Content provided by FirstRanker.com ---
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Procedure:
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1. Write and draw the Digital logic system.
2. Write the Verilog code for above system.
3. Enter the Verilog code in Xilinx software.
4. Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and verify the
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output waveform as obtained.5. Implement the above code in Spartan III using FPGA kit.
Result:
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Thus the verilog code for half adder, full adder and multiplexer were simulated and verifiedsuccessfully.
Outcome:
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At the completion of an experiment student will able to be known the verilog code for half adder,full adder and multiplexer.
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56 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.13:
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SIMULATION OF SEQUENTIAL CIRCUITS USING HDLAim:
To write a verilog code for RS, D, JK flip flop and up counter
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Tools required:
Xilinx 9.2
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Program:RS Flip Flop:
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D Flip Flop:--- Content provided by FirstRanker.com ---
57 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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JK Flip Flop:
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Up Counter:--- Content provided by FirstRanker.com ---
58 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Result:
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Thus the verilog code for RS,D,JK Filp Flop and up counter were simulated and verified
successfully.
Outcome:
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At the completion of an experiment student will able to be known the verilog code for RS, D, JK
Filp Flop and up counter .
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59 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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ADDITIONAL EXPERIMENTS--- Content provided by FirstRanker.com ---
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60 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.8: ENCODER AND DECODER
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Aim:
To study the operation of encoder and decoder circuits using logic gates
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Apparatus required:S. No Name of the Apparatus Range Quantity
1. Digital IC trainer 1
2. NOT Gate IC 7404 1
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3. OR Gate IC 7432 14. AND Gate IC7408 1
5. Bread Board 1
6. NOT Gate IC7404 1
8. Connecting wires and probes As required
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Theory:
Decoder
In digital electronics, a decoder can take the form of a multiple-input, multiple-output logic circuit that
converts coded inputs into coded outputs, where the input and output codes are different e.g. n-to-2n ,
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binary-coded decimal decoders. Decoding is necessary in applications such as data multiplexing, 7segment display and memory address decoding.
The example decoder circuit would be an AND gate because the output of an AND gate is "High" (1) only
when all its inputs are "High." Such output is called as "active High output". If instead of AND gate, the
NAND gate is connected the output will be "Low" (0) only when all its inputs are "High". Such output is
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called as "active low output".A slightly more complex decoder would be the n-to-2n type binary decoders. These types of decoders are
combinational circuits that convert binary information from 'n' coded inputs to a maximum of 2n unique
outputs. In case the 'n' bit coded information has unused bit combinations, the decoder may have less than
2n outputs. 2-to-4 decoder, 3-to-8 decoder or 4-to-16 decoder are other examples.
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The input to a decoder is parallel binary number and it is used to detect the presence of a particularbinary number at the input. The output indicates presence or absence of specific number at the decoder
input. An encoder is a device, circuit, transducer, software program, algorithm or person that converts
information from one format or code to another. The purpose of encoder is standardization, speed,
secrecy, security, or saving space by shrinking size. Encoders are combinational logic circuits and they are
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exactly opposite of decoders. They accept one or more inputs and generate a multibit output code.Encoders perform exactly reverse operation than decoder. An encoder has M input and N output lines. Out
FirstRanker.com - FirstRanker's Choice
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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OFCOMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
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CS8382 DIGITAL SYSTEMS LABORATORY--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
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Section : _______________________________________--- Content provided by FirstRanker.com ---
LABORATORY MANUAL2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
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is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
training.
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? To provide competent technical manpower capable of meeting requirements of the industry
--- Content provided by FirstRanker.com ---
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at differentlevels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
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DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
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Engineering and thereby produce extremely well trained employable, socially responsible and innovativeElectrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
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? To provide highest quality learning environment for the students emphasizing fundamentalconcepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
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VISIONMISSION
VISION
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MISSION
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3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM EDUCATIONAL OBJECTIVES (PEOs)1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
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engineering enabling them to solve complex problems in order to develop real time applications.2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
technologies.
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3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
development of society.
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4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
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5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
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d. Graduates will be able to design a system, component or process as per needs and specifications.e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
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h. Graduates will be able to communicate effectively by both verbal and written form.i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
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CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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SYLLABUS
Objectives:
The student should be made to:
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? Understand the various logic gates.? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
? Learn to use HDL
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List of experiments:1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
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a. 4 ? bit binary adder / subtractorb. Parity generator / checker
c. Magnitude Comparator
d. Application using multiplexers
4. Design and implementation of sequential circuits:
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a. Shift ?registersb. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
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Course Outcomes:? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
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? Design and Implement a simple digital system.--- Content provided by FirstRanker.com ---
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Content
Sl.No. Name of the Experiment Page No.
1.
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Verification of Boolean Theorems using Digital Logic Gates2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
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3.Implementation of half adder and full adder
4.
Implementation of half subtractor and full subtractor
5.
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Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates andMSI Devices
6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
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Devices7.
Design and Implementation of Magnitude Comparator.
8.
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Design and Implementation of Application using Multiplexers / Demultiplexers.9.
Design and Implementation of Shift Registers.
10.
Design and Implementation of Synchronous and Asynchronous Counters.
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11.Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
12.
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Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).--- Content provided by FirstRanker.com ---
7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.1: STUDY OF BASIC GATES
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Aim:To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. NAND gate IC 7400 16. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND gate
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The AND gate performs a logical multiplication commonly known as AND function. Theoutput is high when both the inputs are high. The output is low level when any one of the inputs is
low.
OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
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high when any one of the inputs is high. The output is low level when both the inputs are low.NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
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The NAND gate is a contraction of AND-NOT. The output is high when both inputs are lowand any one of the input is low .The output is low level when both inputs are high.
NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
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EX-OR gateAn Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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AND Gate Symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
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OR Gate:--- Content provided by FirstRanker.com ---
OR GATE:--- Content provided by FirstRanker.com ---
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00NAND Gate symbol: PIN Diagram:
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NOR Gate:--- Content provided by FirstRanker.com ---
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
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1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
th
pin is grounded and 14
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thpin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
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Result:The truth tables of all the basic logic gates were verified.
Outcome:
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At the completion of an experiment student will able to verify the truth
table of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
3. How many gates presented in IC 7408?
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4. What is IC?5. What are the applications of gates?
6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
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9. Write the truth table of NAND gate.10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
13. What are types of linear integrated circuit?
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14. What is meant by etching?15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.2:VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gates
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. NAND gate IC 7400 16. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
BASIC Boolean Laws
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1. Commutative LawThe binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A
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2. Associative Law
The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
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2. A.(B.C) = (A.B).C3. Distributive Law
The binary operator OR, AND is said to be distributive if,
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1. A+(B.C) = (A+B).(A+C)2. A.(B+C) = (A.B)+(A.C)
4. Absorption Law
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1. A+AB = A2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law1. A+A = A
2. A.A = A
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6. Complementary Law1. A+A' = 1
2. A.A' = 0
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7. De Morgan ?s Theorem1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
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2. The complement of the product is equal to the sum of the individual complements.A.B = A+B
Design
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1. Absorption LawA+AB = A
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2. Involution (or) Double complement LawA = A
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3. Idempotent Law
1. A+A = A
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2. A.A = A--- Content provided by FirstRanker.com ---
14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
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A+B = A.B5. Distributive Law
A+(B.C) = (A+B).(A+C)
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Procedure:
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
cc
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.3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
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Result:Thus the above stated Boolean laws are verified.
Outcome:
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At the completion of an experiment student will able to know the basic laws with their truth table.1. What is Demorgan?s law?
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2. What is associative law?3. What is mean by compliment gate?
4. Explain the basic laws in digital electronics
5. What is double complement?
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Viva ? Voce--- Content provided by FirstRanker.com ---
15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
To design and verify the truth table of the Half Adder & Full Adder circuits
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Apparatus required:
S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:
The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
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0 + 0 = 0
0 + 1 = 1
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1 + 0 = 11 + 1 = 0 (with 1 as carry)
The first three operations produce a sum of whose length is one digit, but when the last operation is
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performed the sum is two digits. The higher significant bit of this result is called a carry and lowersignificant bit is called the sum.
Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
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Full adder:
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
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From the truth table, the expression for sum and carry bits of the output can be obtained as,
SUM = A?B?C + A?BC? + AB?C? + ABC
CARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half Adder
Truth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
S = A B
Carry, C = A . B
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Circuit diagram:
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Full adder
Truth table:
Sl.No. Input Output
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A B C S C1. 0 0 0 0 0
2. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
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5. 1 0 0 1 06. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input Output
A B S C
1. 0 0 0 0
2. 0 1 1 0
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3. 1 0 1 04. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:
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CARRY = AB + AC + BC
Logic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
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thpin is grounded and 14
th
pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
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Result:
The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to design the half adder circuit and the
full adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
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Aim:
To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
--- Content provided by FirstRanker.com ---
5. EX-OR gate IC 7486 16. Connecting wires As required
Theory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
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is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than thesubtrahend bit, hence 1 is borrowed.
Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
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variables designate the minuend and the subtrahend bit, whereas the output variables produce thedifference and borrow bits.
Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
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implemented with two half subtractors and one OR gate.From the truth table the expression for difference and borrow bits of the output can be obtained
as,
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Difference, DIFF= A?B?C + A?BC? + AB?C? + ABCBorrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half subtractor
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Truth table:Sl.No. Input Output
A B Difference Borrow
1. 0 0 0 0
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2. 0 1 1 13. 1 0 1 0
4. 1 1 0 0
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From the truth table the expression for difference and borrow bits of the output can be obtained as,Difference, DIFF = A B
Borrow, BORR = A?. B
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Logic diagram:--- Content provided by FirstRanker.com ---
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2. Full subtractor
Truth table:
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Sl.No.
Input Output
A B C Difference Borrow
1. 0 0 0 0 0
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2. 0 0 1 1 13. 0 1 0 1 1
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 0
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7. 1 1 0 0 08. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
Borrow
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Borrow = A?B + A?C + BC
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Circuit diagram:--- Content provided by FirstRanker.com ---
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
Aim:
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To design and implement 4-bit adder and subtractor using IC 7483Apparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. IC IC 7483 1
3. NOT gate IC 7404 1
4. EX-OR gate IC 7486 1
5. Connecting wires As required
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Theory:
4 BIT Binary adder:
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A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can beconstructed with full adders connected in cascade, with the output carry from each full adder connected to
the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
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0and it ripples through
the full adder to the output carry C
4
.
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4 BIT Binary subtractor:The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
?B? and the corresponding input of full adder. The input carry C
0
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must be equal to 1 when performingsubtraction.
4 BIT Binary adder / subtractor:
The addition and subtraction operation can be combined into one circuit with one common binary
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adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, itbecomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PIN Diagram for IC 7483:
Logic Diagram: 4-Bit Binary Diagram:
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Logic diagram: 4-Bit Binary Subtractor:
4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:
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Procedure:
1. Connections are given as per the circuit diagrams.
2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
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.Result:
The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
verified.
Outcome:
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At the completion of an experiment student will able to design 4-bit binary adder and subtractorInput Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
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1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 00 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
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1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 125 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?
2. Write the truth table for half adder.
3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
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5. Write the truth table for full subtrator.6. Draw the logic diagram of full subtrator.
7. What is adder?
8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
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10. What is combinational circuit?11. What is different between combinational and sequential circuit?
12. What are the gates involved for binary adder?
13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.6: MAGNITUDE COMPARATOR
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Aim:
To design, construct and study the performance of 2 bit magnitude comparator
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
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6. EX-OR gate IC 7486 17. Connecting wires As required
Theory:
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The comparison of two numbers is an operator that determines one number is greater than, lessthan (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
three binary variables that indicate whether A>B, A=B (or) A
Truth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Logic Diagram:
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Pin Diagram for IC 7485:
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Logic Diagram:29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:Truth table:
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Procedure:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
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3. Observe the output and verify the truth table.Result:
Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
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Outcome:
At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
comparator using logic gates.
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A B A>B A=B A0 0 0 0
0 0 0 0
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0 0 0 00 0 0 0
0 1 0
0 0 0 1
0 0 0 1
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0 0 0 00 0 0 0
1 0 0
0 0 0 0
0 0 0 0
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0 0 0 10 0 0 1
0 0 1
Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is magnitude comparator?
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2. What is most significant bit?3. Explain operation of AND gate.
4. Explain truth table of a comparator.
5. Explain magnitude comparator7485 IC.
6. What is 8-bit input Magnitude Comparator?
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7. What is IC?8. Explain the k-map simplification of A>B.
9. Explain the k-map simplification of A=B.
10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
12. What is the truth table of 1-bit magnitude comparator?
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13. What is the use of magnitude comparator?--- Content provided by FirstRanker.com ---
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Expt.No.7: CODE CONVERSION
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31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Aim:
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To design, construct and study the performance of 4-bit different code converters(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
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7. Connecting wires As requiredTheory:
The availability of large variety of codes for the same discrete elements of information results in
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the use of different codes by different systems. A conversion circuit must be inserted between the twosystems if each uses different codes for same information. Thus, code converter is a circuit that makes the
two systems compatible even though each uses different binary code. The bit combination assigned to
binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
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and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit isdesigned. The Boolean functions are obtained from K-Map for each output variable. A code converter is a
circuit that makes the two systems compatible even though each uses a different binary code. To convert
from binary code to Excess-3 code, the input lines must supply the bit combination of elements as
specified by code and the output lines generate the corresponding bit combination of code. Each one of the
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four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are
various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is
C+D has been used to implement partially each of three outputs.
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Logic diagram:
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32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
(i) Binary to gray code converter
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Logic Diagram:
K map for G3:
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G3 = B3
K map for G2:
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K map for G1:
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33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for G0:
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Truth table:
0
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00
0
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
0
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
0
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
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(ii) Gray to binary code converter34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:
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K map for B3:
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B3=G3K map for B2:
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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G3 G2 G1 G0 B3 B2 B1 B0
0
0
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00
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
0
0
0
0
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00
0
0
1
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11
1
1
1
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11
0
0
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00
1
1
1
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10
0
0
0
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11
1
1
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00
1
1
0
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01
1
0
0
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11
0
0
1
--- Content provided by FirstRanker.com ---
10
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
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01
0
1
0
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10
1
K map for B1:
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K map for B0:
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Truth table:
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00(iii) BCD to excess-3 code converter
Logic Diagram:
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K map for E3:
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E3 = B3 + B2 (B0 + B1)K map for E2:
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for E1:
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K map for E0:
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Truth table:
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(iv) Excess-3 to
B3 B2 B1 B0 G3 G2 G1 G0
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00
0
0
0
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00
0
1
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
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01
1
1
1
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00
0
0
1
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11
1
0
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01
1
0
0
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11
0
0
1
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10
0
1
1
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0
1
0
1
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01
0
1
0
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10
1
0
1
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01
0
0
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00
0
1
1
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11
1
x
x
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xx
x
x
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01
1
1
1
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00
0
0
1
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xx
x
x
x
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x1
0
0
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11
0
0
1
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10
x
x
x
--- Content provided by FirstRanker.com ---
xx
x
1
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01
0
1
0
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10
1
0
x
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xx
x
x
x
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38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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BCD code converterLogic Diagram:
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K map for A:A = X1 X2 + X3 X4 X1
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K map for B:--- Content provided by FirstRanker.com ---
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39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for C:
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K map for D:
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Truth table:
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B3 B2 B1 B0 G3 G2 G1 G00
0
0
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00
1
1
1
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11
0
1
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11
1
0
0
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00
1
1
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00
1
1
0
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01
1
0
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10
1
0
1
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01
0
1
0
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0
0
0
0
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00
0
0
1
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10
0
0
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01
1
1
1
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00
0
0
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11
0
0
1
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10
0
0
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10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
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40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections were given as per circuit diagram.
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2. Logical inputs were given as per truth table3. Observe the logical output and verify with the truth tables.
Result:
Thus the code converters were designed and verified using the corresponding truth table.
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Outcome:
At the completion of an experiment student will able to design the binary to gray converter.
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1. What is binary code?2. What is gray code?
3. What are the advantages of gray code?
4. What is unit distance code?
5. What is sequential code?
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6. How to convert binary to gray code?7. How to convert gray to binary code?
8. What is reflective code?
9. What are the advantages of EX ? 3 code?
10. Which code is used to arithmetic operation in digital circuits?
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11. Explain the operation of EX ? OR.12. What is K ? Map?
13. Draw the truth table of EX- OR gate.
14. What is SOP?
15. What is POS?
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16. What is minterm?--- Content provided by FirstRanker.com ---
Viva ? Voce
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41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.8: PARITY GENERATORS AND CHECKERS
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Aim:
To implement the odd and even parity checkers using the logic gates and also to generate the odd parity
and even parity numbers using the generators
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Apparatus required:Sl. No Component Type Quantity
1 Trainer Kit - 1
2 EX-OR IC7486 1
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3 NOT gate IC 7404 14 Connecting wires - Required
Theory:
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Parity checking is used for error detection in data transmission.Odd parity checkers:
It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
odd.
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Even parity checker:
It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
even.
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Odd parity generators:
It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also
the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bits
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which is an odd parity number.Even parity generator:
It generates an even parity number. The even parity checker circuit is used with the inverted output and
also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5
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bits which is an even parity number.--- Content provided by FirstRanker.com ---
42 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Truth table:
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Input Checker output Generator outputA B C D D odd even odd even
0 0 0 1 1 0 00010 00011
0 0 1 0 1 0 00100 00101
0 0 1 1 0 1 00111 00110
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0 1 0 0 1 0 01000 010010 1 0 1 0 1 01011 01010
0 1 1 0 0 1 01101 01100
0 1 1 1 1 0 01110 01111
1 0 0 0 1 0 10000 10001
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1 0 0 1 0 1 10011 100101 0 1 0 0 1 10101 10100
1 0 1 1 1 0 10110 10111
1 1 0 0 0 1 11001 11000
1 1 0 1 1 0 11010 11011
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1 1 1 0 1 0 11100 111011 1 1 1 0 1 11111 11110
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Procedure:1. The circuit is implemented using logic gates.
2. The inputs are given as per the truth table.
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3. The corresponding outputs are noted.4. The theoretical and practical values were verified.
Result:
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The odd and even parity checkers are implemented using the logic gates and the odd parity andeven parity numbers are generated using the corresponding generators.
Outcome:
At the completion of an experiment student will able to verify the odd and even parity checker
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using logic gates.--- Content provided by FirstRanker.com ---
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43 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
1. What is parity bit?2. Why parity bit is added to message?
3. What is parity checker?
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4. What is odd parity?
5. What is even parity?
6. What are the gates involved for parity generator?
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7. List the procedures to convert gray code into binary.8. Why weighted code is called as reflective codes?
9. What is a sequential code?
10. What is error deducting code?
11. What is ASCII code?
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12. What is hamming code?13. List the binary weighted code.
14. List the binary non weighted code.
15. Write the hamming code equation
16. List the procedures to convert binary code into gray
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17. What are the applications of gray code?18. What are the applications of Excess- 3 code?
Viva ? Voce
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44 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.9: MULTIPLEXER AND DEMULTIPLEXER
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Aim:
To design and verify the truth table of a 4X1 multiplexer & 1X4 demultiplexer
Apparatus required:
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Sl. No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. OR gate IC 7432 1
3. NOT gate IC 7404 1
4. AND gate ( three input ) IC 7411 1
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5. Connecting wires As requiredTheory:
Multiplexing means transmitting a large number of information units over a smaller number of channels or
lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input
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lines and directs it to a single output line. The selection of particular input line is controlled by a set ofselection lines. Normally, there are 2
n
input lines and n selection lines whose bit combinations determines
which input is selected. A multiplexer is called a data selector, since it selects one of many inputs and
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steers the binary information to the output line. A Strobe is also provided to allow the designer to disable alloutput data until a specified time. Then, by allowing the STROBE to go low, the proper lead can be
selected. This feature is very useful where data might be changing the same time DATA SELECT leads
change. It is a very useful Medium Scale Integration (MSI) function and has a multitude of applications. It is
used for connecting two or more sources to a single destination among the computer units and it is useful
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for constructing a common bus system. A decoder with an enable input can function as a demultiplexer. ADemultiplexer is a circuit that receives information on a single line and transmits this information on one of
2
n
possible output lines. The selection of specific output line is controlled by the bit values of n selection
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lines. The decoder and demultiplexer operations are obtained from the same circuit; a decoder with anenable input is referred to as a decoder / de-multiplexer. The Strobe lead can be used to active or de-
active the entire IC, allowing time for the address lines to change the information is fed to the output.
Demultiplexers are useful anytime information from one source must be fed several places.
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45 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4 X 1 MULTIPLEXERCIRCUIT DIAGRAM:
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46 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1X4 DEMULTIPLEXER
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CIRCUIT DIAGRAM:
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47 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Result:
The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth tables
were verified.
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Outcome:
At the completion of an experiment student will able to design the multiplexer and the
demultiplexer
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1. What is multiplexer?
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2. What is demultiplexer?3. What are the advantages of multiplexer?
4. What are the advantages of demultiplexer?
5. What is select signal?
6. How to choose select signal in multiplexer?
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7. How to choose select signal in demultiplexer?8. Write the formula used in select signal.
9. What is the difference between the multiplexer and demultiplexer?
10. What is the application of multiplexer?
11. What is the application of demultiplexer?
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12. Draw the truth table of multiplexer.13. Draw the truth table of demultiplexer.
14. How many select signals are needed in 8*1 multiplexer?
15. How many select signals are needed in 8*1 demultiplexer?
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Viva ? Voce
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48 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
EXP NO: 11 SHIFT REGISTER
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Aim:
To design and implement the various shift register
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Apparatus required:Sl. No Name of the Apparatus Range Quantity
1. D flip flop IC 7474 2
2. OR gate IC 7432 1
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3. IC Trainer kit 15. Connecting wires As required
Theory:
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A register is capable of shifting its binary information in one or both directions isknown as shift register. The logical configuration of shift register consist of a D-Flip flop
cascaded with output of one flip flop connected to input of next flip flop. All flip flops receive
common clock pulses which causes the shift in the output of the flip flop.The simplest possible
shift register is one that uses only flip flop. The output of a given flip flop is connected to the
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input of next flip flop of the register. Each clock pulse shifts the content of register one bit positionto right.
PIN Diagram:
Logic Diagram:
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SERIAL IN SERIAL OUT--- Content provided by FirstRanker.com ---
49 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth Table:CLK Serial in Serial out
1 1 0
2 0 0
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3 0 04 1 1
5 X 0
6 X 0
7 X 1
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Logic Diagram:
Serial in parallel out:
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Truth Table:
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CLK DATAOUTPUT
Q
A
Q
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BQ
C
Q
D
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1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1
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Parallel in Serial Out:
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50 Format No.FirstRanker/stud/LM/34/issue:00/revision:00CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
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2 0 0 0 0 03 0 0 0 0 1
Truth Table:
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Parallel in Parallel Out:
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PARALLEL IN PARALLEL OUT:
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Truth Table:
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Procedure:
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1. Connections are given as per circuit diagram
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
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Result:Thus the implementation of shift registers using flip flops was completed successfully.
Outcome:
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At the completion of an experiment student will able to design the various types of shift register.--- Content provided by FirstRanker.com ---
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CLK
DATA INPUT OUTPUT
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DA D
B D
C D
D Q
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A QB Q
C Q
D
1 1 0 0 1 1 0 0 1
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2 1 0 1 0 1 0 1 051 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.12: SYNCHRONOUS UP/DOWN COUNTER
Aim:
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To design and implement 3 bit synchronous up/down counterApparatus required:
S.No Name of the Apparatus Range Quantity
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1. JK Flip Flop IC 7474 22. OR gate IC 7432 1
3. NOT gate IC 7404 1
4. AND gate ( three input ) IC 7411 1
5 XOR gate IC 7486 1
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6 IC Trainer Kit 17. Connecting wires As required
Theory:
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A counter is a register capable of counting number of clock pulse arriving at its clock input.
Counter represents the number of clock pulses arrived. An up/down counter is one that is capable of
progressing in increasing order or decreasing order through a certain sequence. An up/down counter
is also called bidirectional counter. Usually up/down operation of the counter is controlled by up/down
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signal. When this signal is high counter goes through up sequence and when up/down signal is low counterfollows reverse sequence.
K map:
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52 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Q Q
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t+1 J K0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
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State Diagram:
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Characteristic Table:
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Logic Diagram:
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53 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Input
Up/Down
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PresentState
Q
A
Q
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BQ
C
Next State
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QA+1
Q
B+1
Q
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C+1A
J
A
K
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AB
J
B
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KB
C
J
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CK
C
0 0 0 0 1 1 1 1 X 1 X 1 X
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0 1 1 1 1 1 0 X 0 X 0 X 10 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
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0 0 1 0 0 0 1 0 X X 1 1 X0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
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1 0 1 1 1 0 0 1 X X 1 X 11 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1
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Truth Table:
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Procedure:
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1. Connections are given as per circuit diagram.2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
Result:
Thus the 3-bit synchronous up/down counters was implemented successfully.
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Outcome:At the completion of an experiment student will able to design the synchronous up/down counter.
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54 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.12:
SIMULATION OF COMBINATIONAL CIRCUITS USING HDL
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Aim:To write a verilog code for half adder, full adder and multiplexer
Tools Required:
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Xilinx 9.2Program:
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Simulation wave for half adder
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55 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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MULTIPLEXER:--- Content provided by FirstRanker.com ---
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Procedure:
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1. Write and draw the Digital logic system.
2. Write the Verilog code for above system.
3. Enter the Verilog code in Xilinx software.
4. Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and verify the
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output waveform as obtained.5. Implement the above code in Spartan III using FPGA kit.
Result:
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Thus the verilog code for half adder, full adder and multiplexer were simulated and verifiedsuccessfully.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to be known the verilog code for half adder,full adder and multiplexer.
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56 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.13:
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SIMULATION OF SEQUENTIAL CIRCUITS USING HDLAim:
To write a verilog code for RS, D, JK flip flop and up counter
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Tools required:
Xilinx 9.2
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Program:RS Flip Flop:
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D Flip Flop:--- Content provided by FirstRanker.com ---
57 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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JK Flip Flop:
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Up Counter:--- Content provided by FirstRanker.com ---
58 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Result:
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Thus the verilog code for RS,D,JK Filp Flop and up counter were simulated and verified
successfully.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to be known the verilog code for RS, D, JK
Filp Flop and up counter .
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59 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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ADDITIONAL EXPERIMENTS--- Content provided by FirstRanker.com ---
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60 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.8: ENCODER AND DECODER
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Aim:
To study the operation of encoder and decoder circuits using logic gates
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Apparatus required:S. No Name of the Apparatus Range Quantity
1. Digital IC trainer 1
2. NOT Gate IC 7404 1
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3. OR Gate IC 7432 14. AND Gate IC7408 1
5. Bread Board 1
6. NOT Gate IC7404 1
8. Connecting wires and probes As required
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Theory:
Decoder
In digital electronics, a decoder can take the form of a multiple-input, multiple-output logic circuit that
converts coded inputs into coded outputs, where the input and output codes are different e.g. n-to-2n ,
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binary-coded decimal decoders. Decoding is necessary in applications such as data multiplexing, 7segment display and memory address decoding.
The example decoder circuit would be an AND gate because the output of an AND gate is "High" (1) only
when all its inputs are "High." Such output is called as "active High output". If instead of AND gate, the
NAND gate is connected the output will be "Low" (0) only when all its inputs are "High". Such output is
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called as "active low output".A slightly more complex decoder would be the n-to-2n type binary decoders. These types of decoders are
combinational circuits that convert binary information from 'n' coded inputs to a maximum of 2n unique
outputs. In case the 'n' bit coded information has unused bit combinations, the decoder may have less than
2n outputs. 2-to-4 decoder, 3-to-8 decoder or 4-to-16 decoder are other examples.
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The input to a decoder is parallel binary number and it is used to detect the presence of a particularbinary number at the input. The output indicates presence or absence of specific number at the decoder
input. An encoder is a device, circuit, transducer, software program, algorithm or person that converts
information from one format or code to another. The purpose of encoder is standardization, speed,
secrecy, security, or saving space by shrinking size. Encoders are combinational logic circuits and they are
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exactly opposite of decoders. They accept one or more inputs and generate a multibit output code.Encoders perform exactly reverse operation than decoder. An encoder has M input and N output lines. Out
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61 Format No.FirstRanker/stud/LM/34/issue:00/revision:00of M input lines only one is activated at a time and produces equivalent code on output N lines. If a device
output code has fewer bits than the input code has, the device is usually called an encoder
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Sl.No. Inputs Outputs
D7 D6 D5 D4 D3 D2 D1 D0 A B C
1. 0 0 0 0 0 0 0 1 0 0 0
2. 0 0 0 0 0 0 1 0 0 0 1
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3. 0 0 0 0 0 1 0 0 0 1 04. 0 0 0 0 1 0 0 0 0 1 1
5. 0 0 0 1 0 0 0 0 1 0 0
6. 0 0 1 0 0 0 0 0 1 0 1
7. 0 1 0 0 0 0 0 0 1 1 0
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8. 1 0 0 0 0 0 0 0 1 1 1Procedure:
1. Make the circuit connections as shown in the figure.
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2. Check the corresponding truth table.Result:
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The design of the Encoder and Decoder circuit was done and the input and output were obtainedOutcome:
At the completion of an experiment student will able to design the encoder circuit and the decoder circuit
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Sl.No.
Inputs Outputs
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A B Y3 Y2 Y1 Y01. 0 0 0 0 0 1
2. 0 1 0 0 1 0
3. 1 0 0 1 0 0
4. 1 1 1 0 0 0
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FirstRanker.com - FirstRanker's Choice1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
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III SEMESTER - R 2017
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
Section : _______________________________________
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LABORATORY MANUAL
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2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious and
--- Content provided by FirstRanker.com ---
enterprising professionals conforming to global standards through value based quality education andtraining.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
--- Content provided by FirstRanker.com ---
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
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DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
--- Content provided by FirstRanker.com ---
needs.? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
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industry by continuous assessment and training.VISION
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MISSIONVISION
MISSION
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3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
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1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
--- Content provided by FirstRanker.com ---
2. Core CompetenceTo train the students to meet the needs of core industry with an attitude of learning new
technologies.
3. Breadth
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To provide relevant training and experience to bridge the gap between theory and practice whichenable them to find solutions to problems in industry and research that contributes to the overall
development of society.
4. Professionalism
--- Content provided by FirstRanker.com ---
To inculcate professional and effective communication skills to the students to make them lead ateam and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
5. Lifelong Learning/Ethics
--- Content provided by FirstRanker.com ---
To practice ethical and professional responsibilities in the organization and society withcommitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
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f. Graduates will demonstrate skills to use modern engineering tools, software and equipment toanalyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
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will be aware of contemporary issues.j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
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CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
SYLLABUS
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Objectives:
The student should be made to:
? Understand the various logic gates.
? Be familiar with various combinational circuits.
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? Understand the various components used in the design of digital computers.? Be exposed to sequential circuits
? Learn to use HDL
List of experiments:
1. Verification of Boolean Theorems using basic gates.
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2. Design and implementation of combinational circuits using basic gates for arbitraryfunctions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
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c. Magnitude Comparatord. Application using multiplexers
4. Design and implementation of sequential circuits:
a. Shift ?registers
b. Synchronous and asynchronous counters
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5. Coding combinational / sequential circuits using HDL.6. Design and implementation of a simple digital system (Mini Project).
Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
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? Design and Implement combinational and sequential circuits.? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Content
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Sl.No. Name of the Experiment Page No.
1.
Verification of Boolean Theorems using Digital Logic Gates
2.
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Design and Implementation of Combinational Circuits using Basic Gates for ArbitraryFunctions, Code Converters
3.
Implementation of half adder and full adder
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4.Implementation of half subtractor and full subtractor
5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
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6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
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7.Design and Implementation of Magnitude Comparator.
8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
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Design and Implementation of Shift Registers.10.
Design and Implementation of Synchronous and Asynchronous Counters.
11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
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HDL Software Required).12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.1: STUDY OF BASIC GATES
Aim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
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7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
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more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known asuniversal gates. Basic gates form these gates.
AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
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low.OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
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A NOT gate is the physical realization of the complementation operation. The NOT gate iscalled an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
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NOR gateThe NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
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similar to OR gate but excludes the combination of both A and B being equal to one. The exclusiveOR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Procedure:
1. Connections are given as per the circuit diagram.
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2. For all the IC?s 7th
pin is grounded and 14
th
pin is given +5 supply.
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3. Apply the inputs and verify the truth table for all gates.Result:
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The truth tables of all the basic logic gates were verified.Outcome:
At the completion of an experiment student will able to verify the truth
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table of all basic gates--- Content provided by FirstRanker.com ---
1. List out the basic gate.2. Mention the universal gate.
3. How many gates presented in IC 7408?
4. What is IC?
5. What are the applications of gates?
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6. Write the truth table of AND gate.7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
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11. Write the truth table of EX- OR gate.12. What are the classifications of IC?
13. What are types of linear integrated circuit?
14. What is meant by etching?
15. What are the advantages of IC?
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16. Write the truth table of EX- NOR gate.Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.2:
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VERIFICATION OF BOOLEAN THEOREMS USING LOGICGATES
Aim: To verification of Boolean theorems using logic gates
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 3
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7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
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BASIC Boolean Laws
1. Commutative Law
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The binary operator OR, AND is said to be commutative if,1. A+B = B+A
2. A.B=B.A
2. Associative Law
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The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
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3. Distributive LawThe binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
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4. Absorption Law
1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
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1. A+A = A2. A.A = A
6. Complementary Law
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1. A+A' = 12. A.A' = 0
7. De Morgan ?s Theorem
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1. The complement of the sum is equal to the sum of the product of the individualcomplements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design
1. Absorption Law
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A+AB = A--- Content provided by FirstRanker.com ---
2. Involution (or) Double complement Law
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A = A--- Content provided by FirstRanker.com ---
3. Idempotent Law
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1. A+A = A
2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
A+B = A.B
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5. Distributive Law
A+(B.C) = (A+B).(A+C)
Procedure:
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1. Obtain the required IC along with the Digital trainer kit.2. Connect zero volts to GND pin and +5 volts to V
cc
.
3. Apply the inputs to the respective input pins.
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4. Verify the output with the truth table.Result:
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Thus the above stated Boolean laws are verified.Outcome:
At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?
2. What is associative law?
3. What is mean by compliment gate?
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4. Explain the basic laws in digital electronics5. What is double complement?
Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.3: HALF ADDER AND FULL ADDERAim:
To design and verify the truth table of the Half Adder & Full Adder circuits
Apparatus required:
--- Content provided by FirstRanker.com ---
S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
0 + 0 = 0
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0 + 1 = 1
1 + 0 = 1
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1 + 1 = 0 (with 1 as carry)The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
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Half adder:A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
Full adder:
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A combinational circuit which performs the arithmetic sum of three input bits is called full adder. Thethree input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
From the truth table, the expression for sum and carry bits of the output can be obtained as,
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SUM = A?B?C + A?BC? + AB?C? + ABCCARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half Adder
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Truth table:--- Content provided by FirstRanker.com ---
From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
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S = A BCarry, C = A . B
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Circuit diagram:--- Content provided by FirstRanker.com ---
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Full adder
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Truth table:Sl.No. Input Output
A B C S C
1. 0 0 0 0 0
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2. 0 0 1 1 03. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
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7. 1 1 0 0 18. 1 1 1 1 1
Sl.No. Input Output
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A B S C1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:--- Content provided by FirstRanker.com ---
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CARRY = AB + AC + BC
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Logic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
--- Content provided by FirstRanker.com ---
1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
th
pin is grounded and 14
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thpin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
Result:
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The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
At the completion of an experiment student will able to design the half adder circuit and the
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full adder circuit.--- Content provided by FirstRanker.com ---
19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
Aim:
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To design and verify the truth table of the half subtractor & full subtractor circuitsApparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
--- Content provided by FirstRanker.com ---
2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
subtrahend bit, hence 1 is borrowed.
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Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
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Full subtractor:A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
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From the truth table the expression for difference and borrow bits of the output can be obtainedas,
Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
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Borrow, BORR = A?BC + AB?C + ABC? +ABC--- Content provided by FirstRanker.com ---
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half subtractor
Truth table:
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Sl.No. Input OutputA B Difference Borrow
1. 0 0 0 0
2. 0 1 1 1
3. 1 0 1 0
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4. 1 1 0 0From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A B
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Borrow, BORR = A?. B
Logic diagram:
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2. Full subtractorTruth table:
Sl.No.
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Input OutputA B C Difference Borrow
1. 0 0 0 0 0
2. 0 0 1 1 1
3. 0 1 0 1 1
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4. 0 1 1 0 15. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
8. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
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Borrow
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
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Borrow = A?B + A?C + BCCircuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
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Aim:
To design and implement 4-bit adder and subtractor using IC 7483
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. IC IC 7483 1
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3. NOT gate IC 7404 14. EX-OR gate IC 7486 1
5. Connecting wires As required
Theory:
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4 BIT Binary adder:
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected to
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the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? aredesignated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
0
and it ripples through
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the full adder to the output carry C4
.
4 BIT Binary subtractor:
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The circuit for subtracting A-B consists of an adder with inverters, placed between each data input?B? and the corresponding input of full adder. The input carry C
0
must be equal to 1 when performing
subtraction.
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4 BIT Binary adder / subtractor:The addition and subtraction operation can be combined into one circuit with one common binary
adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
becomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PIN Diagram for IC 7483:Logic Diagram: 4-Bit Binary Diagram:
Logic diagram: 4-Bit Binary Subtractor:
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4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Truth table:
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Procedure:
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1. Connections are given as per the circuit diagrams.2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
.
Result:
--- Content provided by FirstRanker.com ---
The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table wasverified.
Outcome:
At the completion of an experiment student will able to design 4-bit binary adder and subtractor
--- Content provided by FirstRanker.com ---
Input Data A Input Data B Addition SubtractionA4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
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0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 01 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?
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2. Write the truth table for half adder.3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
5. Write the truth table for full subtrator.
6. Draw the logic diagram of full subtrator.
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7. What is adder?8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
10. What is combinational circuit?
11. What is different between combinational and sequential circuit?
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12. What are the gates involved for binary adder?13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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Viva ? Voce--- Content provided by FirstRanker.com ---
26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.6: MAGNITUDE COMPARATOR
Aim:
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To design, construct and study the performance of 2 bit magnitude comparatorApparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:
The comparison of two numbers is an operator that determines one number is greater than, less
than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
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numbers A and B and determines their relative magnitude. The outcome of the comparator is specified bythree binary variables that indicate whether A>B, A=B (or) A
Truth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:
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Pin Diagram for IC 7485:--- Content provided by FirstRanker.com ---
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:
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Truth table:
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Procedure:1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
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Result:Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
comparator using logic gates.
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A B A>B A=B A0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
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0 1 00 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
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1 0 00 0 0 0
0 0 0 0
0 0 0 1
0 0 0 1
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0 0 1Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is magnitude comparator?
2. What is most significant bit?
3. Explain operation of AND gate.
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4. Explain truth table of a comparator.5. Explain magnitude comparator7485 IC.
6. What is 8-bit input Magnitude Comparator?
7. What is IC?
8. Explain the k-map simplification of A>B.
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9. Explain the k-map simplification of A=B.10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
12. What is the truth table of 1-bit magnitude comparator?
13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Aim:
To design, construct and study the performance of 4-bit different code converters
(i) Binary to gray code converter
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(ii) Gray to binary code converter(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:The availability of large variety of codes for the same discrete elements of information results in
the use of different codes by different systems. A conversion circuit must be inserted between the two
systems if each uses different codes for same information. Thus, code converter is a circuit that makes the
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two systems compatible even though each uses different binary code. The bit combination assigned tobinary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a
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circuit that makes the two systems compatible even though each uses a different binary code. To convertfrom binary code to Excess-3 code, the input lines must supply the bit combination of elements as
specified by code and the output lines generate the corresponding bit combination of code. Each one of the
four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are
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various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output isC+D has been used to implement partially each of three outputs.
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Logic diagram:32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(i) Binary to gray code converter
Logic Diagram:
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K map for G3:
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G3 = B3K map for G2:
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K map for G1:33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for G0:Truth table:
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0
0
0
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00
0
0
0
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11
1
1
1
--- Content provided by FirstRanker.com ---
11
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
0
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
1
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01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
--- Content provided by FirstRanker.com ---
00
0
0
0
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00
0
1
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
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01
1
1
1
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11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
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00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
0
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
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11
0
0
1
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10
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(ii) Gray to binary code converter
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34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:K map for B3:
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B3=G3
K map for B2:
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
G3 G2 G1 G0 B3 B2 B1 B0
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0
0
0
0
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00
0
0
1
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11
1
1
1
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11
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
1
1
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00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
0
0
0
0
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11
1
1
0
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00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
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11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
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00
1
1
--- Content provided by FirstRanker.com ---
01
0
1
0
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10
1
0
1
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01
0
1
0
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1K map for B1:
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K map for B0:
Truth table:
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(iii) BCD to excess-3 code converterLogic Diagram:
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K map for E3:E3 = B3 + B2 (B0 + B1)
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K map for E2:--- Content provided by FirstRanker.com ---
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for E1:--- Content provided by FirstRanker.com ---
K map for E0:--- Content provided by FirstRanker.com ---
Truth table:
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(iv) Excess-3 toB3 B2 B1 B0 G3 G2 G1 G0
0
0
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00
0
0
0
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01
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
0
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
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1x
x
x
x
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xx
0
1
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11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
x
x
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xx
x
x
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10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
xx
x
x
x
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x1
0
1
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01
0
1
0
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10
x
x
x
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xx
x
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38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
BCD code converter
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Logic Diagram:K map for A:
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A = X1 X2 + X3 X4 X1
K map for B:
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39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for C:--- Content provided by FirstRanker.com ---
K map for D:--- Content provided by FirstRanker.com ---
Truth table:--- Content provided by FirstRanker.com ---
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B3 B2 B1 B0 G3 G2 G1 G0
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00
0
0
0
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11
1
1
1
--- Content provided by FirstRanker.com ---
0
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
0
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
00
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
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40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections were given as per circuit diagram.
2. Logical inputs were given as per truth table
3. Observe the logical output and verify with the truth tables.
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Result:
Thus the code converters were designed and verified using the corresponding truth table.
Outcome:
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At the completion of an experiment student will able to design the binary to gray converter.1. What is binary code?
2. What is gray code?
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3. What are the advantages of gray code?4. What is unit distance code?
5. What is sequential code?
6. How to convert binary to gray code?
7. How to convert gray to binary code?
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8. What is reflective code?9. What are the advantages of EX ? 3 code?
10. Which code is used to arithmetic operation in digital circuits?
11. Explain the operation of EX ? OR.
12. What is K ? Map?
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13. Draw the truth table of EX- OR gate.14. What is SOP?
15. What is POS?
16. What is minterm?
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Viva ? Voce--- Content provided by FirstRanker.com ---
41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.8: PARITY GENERATORS AND CHECKERS
Aim:
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To implement the odd and even parity checkers using the logic gates and also to generate the odd parityand even parity numbers using the generators
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl. No Component Type Quantity1 Trainer Kit - 1
2 EX-OR IC7486 1
3 NOT gate IC 7404 1
4 Connecting wires - Required
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Theory:
Parity checking is used for error detection in data transmission.
Odd parity checkers:
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It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
odd.
Even parity checker:
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It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
even.
Odd parity generators:
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It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also
the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bits
which is an odd parity number.
Even parity generator:
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It generates an even parity number. The even parity checker circuit is used with the inverted output and
also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5
bits which is an even parity number.
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42 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:
Input Checker output Generator output
A B C D D odd even odd even
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0 0 0 1 1 0 00010 000110 0 1 0 1 0 00100 00101
0 0 1 1 0 1 00111 00110
0 1 0 0 1 0 01000 01001
0 1 0 1 0 1 01011 01010
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0 1 1 0 0 1 01101 011000 1 1 1 1 0 01110 01111
1 0 0 0 1 0 10000 10001
1 0 0 1 0 1 10011 10010
1 0 1 0 0 1 10101 10100
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1 0 1 1 1 0 10110 101111 1 0 0 0 1 11001 11000
1 1 0 1 1 0 11010 11011
1 1 1 0 1 0 11100 11101
1 1 1 1 0 1 11111 11110
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Procedure:
1. The circuit is implemented using logic gates.
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2. The inputs are given as per the truth table.
3. The corresponding outputs are noted.
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4. The theoretical and practical values were verified.Result:
The odd and even parity checkers are implemented using the logic gates and the odd parity and
even parity numbers are generated using the corresponding generators.
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Outcome:
At the completion of an experiment student will able to verify the odd and even parity checker
using logic gates.
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43 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
1. What is parity bit?
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2. Why parity bit is added to message?3. What is parity checker?
4. What is odd parity?
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5. What is even parity?6. What are the gates involved for parity generator?
7. List the procedures to convert gray code into binary.
8. Why weighted code is called as reflective codes?
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9. What is a sequential code?10. What is error deducting code?
11. What is ASCII code?
12. What is hamming code?
13. List the binary weighted code.
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14. List the binary non weighted code.15. Write the hamming code equation
16. List the procedures to convert binary code into gray
17. What are the applications of gray code?
18. What are the applications of Excess- 3 code?
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Viva ? Voce--- Content provided by FirstRanker.com ---
44 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.9: MULTIPLEXER AND DEMULTIPLEXER
Aim:
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To design and verify the truth table of a 4X1 multiplexer & 1X4 demultiplexerApparatus required:
Sl. No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. OR gate IC 7432 13. NOT gate IC 7404 1
4. AND gate ( three input ) IC 7411 1
5. Connecting wires As required
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Theory:Multiplexing means transmitting a large number of information units over a smaller number of channels or
lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input
lines and directs it to a single output line. The selection of particular input line is controlled by a set of
selection lines. Normally, there are 2
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ninput lines and n selection lines whose bit combinations determines
which input is selected. A multiplexer is called a data selector, since it selects one of many inputs and
steers the binary information to the output line. A Strobe is also provided to allow the designer to disable all
output data until a specified time. Then, by allowing the STROBE to go low, the proper lead can be
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selected. This feature is very useful where data might be changing the same time DATA SELECT leadschange. It is a very useful Medium Scale Integration (MSI) function and has a multitude of applications. It is
used for connecting two or more sources to a single destination among the computer units and it is useful
for constructing a common bus system. A decoder with an enable input can function as a demultiplexer. A
Demultiplexer is a circuit that receives information on a single line and transmits this information on one of
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2n
possible output lines. The selection of specific output line is controlled by the bit values of n selection
lines. The decoder and demultiplexer operations are obtained from the same circuit; a decoder with an
enable input is referred to as a decoder / de-multiplexer. The Strobe lead can be used to active or de-
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active the entire IC, allowing time for the address lines to change the information is fed to the output.Demultiplexers are useful anytime information from one source must be fed several places.
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45 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
4 X 1 MULTIPLEXER
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CIRCUIT DIAGRAM:--- Content provided by FirstRanker.com ---
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46 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
1X4 DEMULTIPLEXER
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CIRCUIT DIAGRAM:
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47 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Result:The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth tables
were verified.
Outcome:
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At the completion of an experiment student will able to design the multiplexer and thedemultiplexer
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1. What is multiplexer?
2. What is demultiplexer?
3. What are the advantages of multiplexer?
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4. What are the advantages of demultiplexer?5. What is select signal?
6. How to choose select signal in multiplexer?
7. How to choose select signal in demultiplexer?
8. Write the formula used in select signal.
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9. What is the difference between the multiplexer and demultiplexer?10. What is the application of multiplexer?
11. What is the application of demultiplexer?
12. Draw the truth table of multiplexer.
13. Draw the truth table of demultiplexer.
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14. How many select signals are needed in 8*1 multiplexer?15. How many select signals are needed in 8*1 demultiplexer?
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Viva ? Voce--- Content provided by FirstRanker.com ---
48 Format No.FirstRanker/stud/LM/34/issue:00/revision:00EXP NO: 11 SHIFT REGISTER
Aim:
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To design and implement the various shift register
Apparatus required:
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Sl. No Name of the Apparatus Range Quantity1. D flip flop IC 7474 2
2. OR gate IC 7432 1
3. IC Trainer kit 1
5. Connecting wires As required
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Theory:
A register is capable of shifting its binary information in one or both directions is
known as shift register. The logical configuration of shift register consist of a D-Flip flop
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cascaded with output of one flip flop connected to input of next flip flop. All flip flops receivecommon clock pulses which causes the shift in the output of the flip flop.The simplest possible
shift register is one that uses only flip flop. The output of a given flip flop is connected to the
input of next flip flop of the register. Each clock pulse shifts the content of register one bit position
to right.
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PIN Diagram:Logic Diagram:
SERIAL IN SERIAL OUT
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49 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Truth Table:
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CLK Serial in Serial out1 1 0
2 0 0
3 0 0
4 1 1
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5 X 06 X 0
7 X 1
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Logic Diagram:Serial in parallel out:
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Truth Table:
CLK DATA
OUTPUT
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QA
Q
B
Q
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CQ
D
1 1 1 0 0 0
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2 0 0 1 0 03 0 0 0 1 1
4 1 1 0 0 1
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Parallel in Serial Out:--- Content provided by FirstRanker.com ---
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50 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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CLK Q3 Q2 Q1 Q0 O/P0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1
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Truth Table:
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Parallel in Parallel Out:--- Content provided by FirstRanker.com ---
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PARALLEL IN PARALLEL OUT:--- Content provided by FirstRanker.com ---
Truth Table:
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Procedure:
1. Connections are given as per circuit diagram
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2. Logical inputs are given as per circuit diagram.3. Observe the output and verify the truth table.
Result:
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Thus the implementation of shift registers using flip flops was completed successfully.Outcome:
At the completion of an experiment student will able to design the various types of shift register.
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CLK
DATA INPUT OUTPUT
D
A D
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B DC D
D Q
A Q
B Q
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C QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
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51 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.12: SYNCHRONOUS UP/DOWN COUNTER
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Aim:
To design and implement 3 bit synchronous up/down counter
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Apparatus required:S.No Name of the Apparatus Range Quantity
1. JK Flip Flop IC 7474 2
2. OR gate IC 7432 1
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3. NOT gate IC 7404 14. AND gate ( three input ) IC 7411 1
5 XOR gate IC 7486 1
6 IC Trainer Kit 1
7. Connecting wires As required
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Theory:
A counter is a register capable of counting number of clock pulse arriving at its clock input.
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Counter represents the number of clock pulses arrived. An up/down counter is one that is capable ofprogressing in increasing order or decreasing order through a certain sequence. An up/down counter
is also called bidirectional counter. Usually up/down operation of the counter is controlled by up/down
signal. When this signal is high counter goes through up sequence and when up/down signal is low counter
follows reverse sequence.
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K map:
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52 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Q Q
t+1 J K
0 0 0 X
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0 1 1 X1 0 X 1
1 1 X 0
State Diagram:
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Characteristic Table:
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Logic Diagram:
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53 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Input
Up/Down
Present
State
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QA
Q
B
Q
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CNext State
Q
A+1
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QB+1
Q
C+1
A
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JA
K
A
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BJ
B
K
B
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C
J
C
K
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C0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
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0 1 0 1 1 0 0 X 0 0 X X 10 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
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1 0 0 0 0 0 1 0 X 0 X 1 X1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
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1 1 0 1 1 1 0 X 0 1 X X 11 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1
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Truth Table:--- Content provided by FirstRanker.com ---
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Procedure:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
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3. Observe the output and verify the truth table.Result:
Thus the 3-bit synchronous up/down counters was implemented successfully.
Outcome:
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At the completion of an experiment student will able to design the synchronous up/down counter.--- Content provided by FirstRanker.com ---
54 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.12:
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SIMULATION OF COMBINATIONAL CIRCUITS USING HDL
Aim:
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To write a verilog code for half adder, full adder and multiplexerTools Required:
Xilinx 9.2
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Program:
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Simulation wave for half adder--- Content provided by FirstRanker.com ---
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55 Format No.FirstRanker/stud/LM/34/issue:00/revision:00MULTIPLEXER:
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Procedure:
1. Write and draw the Digital logic system.
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2. Write the Verilog code for above system.3. Enter the Verilog code in Xilinx software.
4. Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and verify the
output waveform as obtained.
5. Implement the above code in Spartan III using FPGA kit.
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Result:
Thus the verilog code for half adder, full adder and multiplexer were simulated and verified
successfully.
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Outcome:
At the completion of an experiment student will able to be known the verilog code for half adder,
full adder and multiplexer.
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56 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.13:
SIMULATION OF SEQUENTIAL CIRCUITS USING HDL
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Aim:To write a verilog code for RS, D, JK flip flop and up counter
Tools required:
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Xilinx 9.2
Program:
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RS Flip Flop:--- Content provided by FirstRanker.com ---
D Flip Flop:
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57 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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JK Flip Flop:
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Up Counter:
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58 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
Result:
Thus the verilog code for RS,D,JK Filp Flop and up counter were simulated and verified
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successfully.Outcome:
At the completion of an experiment student will able to be known the verilog code for RS, D, JK
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Filp Flop and up counter .--- Content provided by FirstRanker.com ---
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59 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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ADDITIONAL EXPERIMENTS
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60 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.8: ENCODER AND DECODER
Aim:
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To study the operation of encoder and decoder circuits using logic gates
Apparatus required:
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S. No Name of the Apparatus Range Quantity1. Digital IC trainer 1
2. NOT Gate IC 7404 1
3. OR Gate IC 7432 1
4. AND Gate IC7408 1
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5. Bread Board 16. NOT Gate IC7404 1
8. Connecting wires and probes As required
Theory:
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DecoderIn digital electronics, a decoder can take the form of a multiple-input, multiple-output logic circuit that
converts coded inputs into coded outputs, where the input and output codes are different e.g. n-to-2n ,
binary-coded decimal decoders. Decoding is necessary in applications such as data multiplexing, 7
segment display and memory address decoding.
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The example decoder circuit would be an AND gate because the output of an AND gate is "High" (1) onlywhen all its inputs are "High." Such output is called as "active High output". If instead of AND gate, the
NAND gate is connected the output will be "Low" (0) only when all its inputs are "High". Such output is
called as "active low output".
A slightly more complex decoder would be the n-to-2n type binary decoders. These types of decoders are
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combinational circuits that convert binary information from 'n' coded inputs to a maximum of 2n uniqueoutputs. In case the 'n' bit coded information has unused bit combinations, the decoder may have less than
2n outputs. 2-to-4 decoder, 3-to-8 decoder or 4-to-16 decoder are other examples.
The input to a decoder is parallel binary number and it is used to detect the presence of a particular
binary number at the input. The output indicates presence or absence of specific number at the decoder
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input. An encoder is a device, circuit, transducer, software program, algorithm or person that convertsinformation from one format or code to another. The purpose of encoder is standardization, speed,
secrecy, security, or saving space by shrinking size. Encoders are combinational logic circuits and they are
exactly opposite of decoders. They accept one or more inputs and generate a multibit output code.
Encoders perform exactly reverse operation than decoder. An encoder has M input and N output lines. Out
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61 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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of M input lines only one is activated at a time and produces equivalent code on output N lines. If a deviceoutput code has fewer bits than the input code has, the device is usually called an encoder
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Sl.No. Inputs Outputs
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D7 D6 D5 D4 D3 D2 D1 D0 A B C1. 0 0 0 0 0 0 0 1 0 0 0
2. 0 0 0 0 0 0 1 0 0 0 1
3. 0 0 0 0 0 1 0 0 0 1 0
4. 0 0 0 0 1 0 0 0 0 1 1
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5. 0 0 0 1 0 0 0 0 1 0 06. 0 0 1 0 0 0 0 0 1 0 1
7. 0 1 0 0 0 0 0 0 1 1 0
8. 1 0 0 0 0 0 0 0 1 1 1
Procedure:
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1. Make the circuit connections as shown in the figure.
2. Check the corresponding truth table.
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Result:
The design of the Encoder and Decoder circuit was done and the input and output were obtained
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Outcome:At the completion of an experiment student will able to design the encoder circuit and the decoder circuit
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Sl.No.
Inputs Outputs
A B Y3 Y2 Y1 Y0
1. 0 0 0 0 0 1
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2. 0 1 0 0 1 03. 1 0 0 1 0 0
4. 1 1 1 0 0 0
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62 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
1. What is Encoder?
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2. What is decoder?3. List the application of encoder.
4. List the application of decoder.
5. Draw the truth table of encoder.
6. Draw the truth table of decoder.
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7. What are logic gates used encoder?8. What are logic gates used encoder?
9. What is the difference between decoder with demultiplexer?
10. What is the difference between encoder with multiplexer?
11. How to choose the select signal in encoder?
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12. How to choose the select signal in decoder?13. Draw the logic diagram of encoder.
14. Draw the logic diagram of encoder.
15. What is the difference between encoder with decoder?
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Viva ? VoceFirstRanker.com - FirstRanker's Choice
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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OFCOMPUTER SCIENCE ENGINEERING
III SEMESTER - R 2017
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CS8382 DIGITAL SYSTEMS LABORATORY--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
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Section : _______________________________________--- Content provided by FirstRanker.com ---
LABORATORY MANUAL2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
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is committed to provide highly disciplined, conscientious and
enterprising professionals conforming to global standards through value based quality education and
training.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
--- Content provided by FirstRanker.com ---
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at differentlevels
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
--- Content provided by FirstRanker.com ---
Engineering and thereby produce extremely well trained employable, socially responsible and innovativeElectrical and Electronics Engineers.
--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?s
needs.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
--- Content provided by FirstRanker.com ---
? To provide highest quality learning environment for the students emphasizing fundamentalconcepts with strongly supported laboratory and prepare them to meet the global needs of the
industry by continuous assessment and training.
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VISIONMISSION
VISION
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MISSION
--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM EDUCATIONAL OBJECTIVES (PEOs)1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
--- Content provided by FirstRanker.com ---
engineering enabling them to solve complex problems in order to develop real time applications.2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
technologies.
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3. Breadth
To provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
development of society.
--- Content provided by FirstRanker.com ---
4. Professionalism
To inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
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5. Lifelong Learning/Ethics
To practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
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d. Graduates will be able to design a system, component or process as per needs and specifications.e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
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h. Graduates will be able to communicate effectively by both verbal and written form.i. Graduates will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
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CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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SYLLABUS
Objectives:
The student should be made to:
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? Understand the various logic gates.? Be familiar with various combinational circuits.
? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
? Learn to use HDL
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List of experiments:1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
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a. 4 ? bit binary adder / subtractorb. Parity generator / checker
c. Magnitude Comparator
d. Application using multiplexers
4. Design and implementation of sequential circuits:
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a. Shift ?registersb. Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
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Course Outcomes:? Use Boolean simplification techniques to design a combinational hardware circuit.
? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
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? Design and Implement a simple digital system.--- Content provided by FirstRanker.com ---
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Content
Sl.No. Name of the Experiment Page No.
1.
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Verification of Boolean Theorems using Digital Logic Gates2.
Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
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3.Implementation of half adder and full adder
4.
Implementation of half subtractor and full subtractor
5.
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Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates andMSI Devices
6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
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Devices7.
Design and Implementation of Magnitude Comparator.
8.
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Design and Implementation of Application using Multiplexers / Demultiplexers.9.
Design and Implementation of Shift Registers.
10.
Design and Implementation of Synchronous and Asynchronous Counters.
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11.Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
HDL Software Required).
12.
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Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).--- Content provided by FirstRanker.com ---
7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.1: STUDY OF BASIC GATES
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Aim:To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. NAND gate IC 7400 16. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND gate
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The AND gate performs a logical multiplication commonly known as AND function. Theoutput is high when both the inputs are high. The output is low level when any one of the inputs is
low.
OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
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high when any one of the inputs is high. The output is low level when both the inputs are low.NOT gate
A NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
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The NAND gate is a contraction of AND-NOT. The output is high when both inputs are lowand any one of the input is low .The output is low level when both inputs are high.
NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
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EX-OR gateAn Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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AND Gate Symbol: PIN Diagram:--- Content provided by FirstRanker.com ---
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OR Gate:--- Content provided by FirstRanker.com ---
OR GATE:--- Content provided by FirstRanker.com ---
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00NAND Gate symbol: PIN Diagram:
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NOR Gate:--- Content provided by FirstRanker.com ---
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
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1. Connections are given as per the circuit diagram.
2. For all the IC?s 7
th
pin is grounded and 14
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thpin is given +5 supply.
3. Apply the inputs and verify the truth table for all gates.
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Result:The truth tables of all the basic logic gates were verified.
Outcome:
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At the completion of an experiment student will able to verify the truth
table of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
3. How many gates presented in IC 7408?
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4. What is IC?5. What are the applications of gates?
6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
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9. Write the truth table of NAND gate.10. Write the truth table of NOR gate.
11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
13. What are types of linear integrated circuit?
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14. What is meant by etching?15. What are the advantages of IC?
16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.2:VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gates
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. NAND gate IC 7400 16. NOR gate IC 7402 3
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:
BASIC Boolean Laws
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1. Commutative LawThe binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A
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2. Associative Law
The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
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2. A.(B.C) = (A.B).C3. Distributive Law
The binary operator OR, AND is said to be distributive if,
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1. A+(B.C) = (A+B).(A+C)2. A.(B+C) = (A.B)+(A.C)
4. Absorption Law
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1. A+AB = A2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law1. A+A = A
2. A.A = A
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6. Complementary Law1. A+A' = 1
2. A.A' = 0
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7. De Morgan ?s Theorem1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
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2. The complement of the product is equal to the sum of the individual complements.A.B = A+B
Design
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1. Absorption LawA+AB = A
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2. Involution (or) Double complement LawA = A
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3. Idempotent Law
1. A+A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
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A+B = A.B5. Distributive Law
A+(B.C) = (A+B).(A+C)
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Procedure:
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
cc
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.3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
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Result:Thus the above stated Boolean laws are verified.
Outcome:
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At the completion of an experiment student will able to know the basic laws with their truth table.1. What is Demorgan?s law?
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2. What is associative law?3. What is mean by compliment gate?
4. Explain the basic laws in digital electronics
5. What is double complement?
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Viva ? Voce--- Content provided by FirstRanker.com ---
15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
To design and verify the truth table of the Half Adder & Full Adder circuits
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Apparatus required:
S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:
The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
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0 + 0 = 0
0 + 1 = 1
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1 + 0 = 11 + 1 = 0 (with 1 as carry)
The first three operations produce a sum of whose length is one digit, but when the last operation is
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performed the sum is two digits. The higher significant bit of this result is called a carry and lowersignificant bit is called the sum.
Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
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Full adder:
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
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From the truth table, the expression for sum and carry bits of the output can be obtained as,
SUM = A?B?C + A?BC? + AB?C? + ABC
CARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half Adder
Truth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
S = A B
Carry, C = A . B
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Circuit diagram:
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Full adder
Truth table:
Sl.No. Input Output
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A B C S C1. 0 0 0 0 0
2. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
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5. 1 0 0 1 06. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input Output
A B S C
1. 0 0 0 0
2. 0 1 1 0
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3. 1 0 1 04. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:
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CARRY = AB + AC + BC
Logic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
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thpin is grounded and 14
th
pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
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Result:
The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
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At the completion of an experiment student will able to design the half adder circuit and the
full adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
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Aim:
To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
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Sl.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
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5. EX-OR gate IC 7486 16. Connecting wires As required
Theory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
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is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than thesubtrahend bit, hence 1 is borrowed.
Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
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variables designate the minuend and the subtrahend bit, whereas the output variables produce thedifference and borrow bits.
Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
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implemented with two half subtractors and one OR gate.From the truth table the expression for difference and borrow bits of the output can be obtained
as,
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Difference, DIFF= A?B?C + A?BC? + AB?C? + ABCBorrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half subtractor
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Truth table:Sl.No. Input Output
A B Difference Borrow
1. 0 0 0 0
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2. 0 1 1 13. 1 0 1 0
4. 1 1 0 0
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From the truth table the expression for difference and borrow bits of the output can be obtained as,Difference, DIFF = A B
Borrow, BORR = A?. B
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2. Full subtractor
Truth table:
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Sl.No.
Input Output
A B C Difference Borrow
1. 0 0 0 0 0
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2. 0 0 1 1 13. 0 1 0 1 1
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 0
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7. 1 1 0 0 08. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
Borrow
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Borrow = A?B + A?C + BC
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
Aim:
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To design and implement 4-bit adder and subtractor using IC 7483Apparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. IC IC 7483 1
3. NOT gate IC 7404 1
4. EX-OR gate IC 7486 1
5. Connecting wires As required
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Theory:
4 BIT Binary adder:
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A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can beconstructed with full adders connected in cascade, with the output carry from each full adder connected to
the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
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0and it ripples through
the full adder to the output carry C
4
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4 BIT Binary subtractor:The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
?B? and the corresponding input of full adder. The input carry C
0
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must be equal to 1 when performingsubtraction.
4 BIT Binary adder / subtractor:
The addition and subtraction operation can be combined into one circuit with one common binary
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adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, itbecomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PIN Diagram for IC 7483:
Logic Diagram: 4-Bit Binary Diagram:
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Logic diagram: 4-Bit Binary Subtractor:
4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:
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Procedure:
1. Connections are given as per the circuit diagrams.
2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
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.Result:
The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
verified.
Outcome:
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At the completion of an experiment student will able to design 4-bit binary adder and subtractorInput Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
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1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 00 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
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1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 125 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?
2. Write the truth table for half adder.
3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
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5. Write the truth table for full subtrator.6. Draw the logic diagram of full subtrator.
7. What is adder?
8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
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10. What is combinational circuit?11. What is different between combinational and sequential circuit?
12. What are the gates involved for binary adder?
13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.6: MAGNITUDE COMPARATOR
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Aim:
To design, construct and study the performance of 2 bit magnitude comparator
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
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6. EX-OR gate IC 7486 17. Connecting wires As required
Theory:
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The comparison of two numbers is an operator that determines one number is greater than, lessthan (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
three binary variables that indicate whether A>B, A=B (or) A
Truth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Logic Diagram:
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Pin Diagram for IC 7485:
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Logic Diagram:29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:Truth table:
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Procedure:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
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3. Observe the output and verify the truth table.Result:
Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
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Outcome:
At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
comparator using logic gates.
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A B A>B A=B A0 0 0 0
0 0 0 0
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0 0 0 00 0 0 0
0 1 0
0 0 0 1
0 0 0 1
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0 0 0 00 0 0 0
1 0 0
0 0 0 0
0 0 0 0
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0 0 0 10 0 0 1
0 0 1
Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is magnitude comparator?
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2. What is most significant bit?3. Explain operation of AND gate.
4. Explain truth table of a comparator.
5. Explain magnitude comparator7485 IC.
6. What is 8-bit input Magnitude Comparator?
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7. What is IC?8. Explain the k-map simplification of A>B.
9. Explain the k-map simplification of A=B.
10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
12. What is the truth table of 1-bit magnitude comparator?
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Expt.No.7: CODE CONVERSION
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31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Aim:
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To design, construct and study the performance of 4-bit different code converters(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
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7. Connecting wires As requiredTheory:
The availability of large variety of codes for the same discrete elements of information results in
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the use of different codes by different systems. A conversion circuit must be inserted between the twosystems if each uses different codes for same information. Thus, code converter is a circuit that makes the
two systems compatible even though each uses different binary code. The bit combination assigned to
binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
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and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit isdesigned. The Boolean functions are obtained from K-Map for each output variable. A code converter is a
circuit that makes the two systems compatible even though each uses a different binary code. To convert
from binary code to Excess-3 code, the input lines must supply the bit combination of elements as
specified by code and the output lines generate the corresponding bit combination of code. Each one of the
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four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are
various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is
C+D has been used to implement partially each of three outputs.
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Logic diagram:
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32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
(i) Binary to gray code converter
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Logic Diagram:
K map for G3:
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G3 = B3
K map for G2:
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K map for G1:
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33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for G0:
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Truth table:
0
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00
0
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
0
0
0
0
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11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
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11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
01
0
1
0
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10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
1
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11
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
0
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
1
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10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
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(ii) Gray to binary code converter34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:
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K map for B3:
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B3=G3K map for B2:
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
G3 G2 G1 G0 B3 B2 B1 B0
0
0
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00
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
00
0
1
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11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
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11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
0
0
0
0
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00
0
0
1
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11
1
1
1
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11
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
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10
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
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01
1
0
0
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11
0
0
1
--- Content provided by FirstRanker.com ---
10
1
0
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10
1
0
1
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01
0
1
0
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10
1
K map for B1:
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K map for B0:
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Truth table:
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00(iii) BCD to excess-3 code converter
Logic Diagram:
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K map for E3:
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E3 = B3 + B2 (B0 + B1)K map for E2:
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for E1:
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K map for E0:
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Truth table:
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(iv) Excess-3 to
B3 B2 B1 B0 G3 G2 G1 G0
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00
0
0
0
--- Content provided by FirstRanker.com ---
00
0
1
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
0
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
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10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
1
x
x
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xx
x
x
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01
1
1
1
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00
0
0
1
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xx
x
x
x
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x1
0
0
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11
0
0
1
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10
x
x
x
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xx
x
1
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01
0
1
0
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10
1
0
x
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xx
x
x
x
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38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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BCD code converterLogic Diagram:
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K map for A:A = X1 X2 + X3 X4 X1
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K map for B:--- Content provided by FirstRanker.com ---
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39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for C:
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K map for D:
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Truth table:
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B3 B2 B1 B0 G3 G2 G1 G00
0
0
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00
1
1
1
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11
0
1
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11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
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10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
0
0
0
0
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
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40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections were given as per circuit diagram.
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2. Logical inputs were given as per truth table3. Observe the logical output and verify with the truth tables.
Result:
Thus the code converters were designed and verified using the corresponding truth table.
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Outcome:
At the completion of an experiment student will able to design the binary to gray converter.
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1. What is binary code?2. What is gray code?
3. What are the advantages of gray code?
4. What is unit distance code?
5. What is sequential code?
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6. How to convert binary to gray code?7. How to convert gray to binary code?
8. What is reflective code?
9. What are the advantages of EX ? 3 code?
10. Which code is used to arithmetic operation in digital circuits?
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11. Explain the operation of EX ? OR.12. What is K ? Map?
13. Draw the truth table of EX- OR gate.
14. What is SOP?
15. What is POS?
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16. What is minterm?--- Content provided by FirstRanker.com ---
Viva ? Voce
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41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.8: PARITY GENERATORS AND CHECKERS
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Aim:
To implement the odd and even parity checkers using the logic gates and also to generate the odd parity
and even parity numbers using the generators
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Apparatus required:Sl. No Component Type Quantity
1 Trainer Kit - 1
2 EX-OR IC7486 1
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3 NOT gate IC 7404 14 Connecting wires - Required
Theory:
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Parity checking is used for error detection in data transmission.Odd parity checkers:
It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
odd.
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Even parity checker:
It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
even.
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Odd parity generators:
It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also
the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bits
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which is an odd parity number.Even parity generator:
It generates an even parity number. The even parity checker circuit is used with the inverted output and
also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5
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bits which is an even parity number.--- Content provided by FirstRanker.com ---
42 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Truth table:
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Input Checker output Generator outputA B C D D odd even odd even
0 0 0 1 1 0 00010 00011
0 0 1 0 1 0 00100 00101
0 0 1 1 0 1 00111 00110
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0 1 0 0 1 0 01000 010010 1 0 1 0 1 01011 01010
0 1 1 0 0 1 01101 01100
0 1 1 1 1 0 01110 01111
1 0 0 0 1 0 10000 10001
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1 0 0 1 0 1 10011 100101 0 1 0 0 1 10101 10100
1 0 1 1 1 0 10110 10111
1 1 0 0 0 1 11001 11000
1 1 0 1 1 0 11010 11011
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1 1 1 0 1 0 11100 111011 1 1 1 0 1 11111 11110
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Procedure:1. The circuit is implemented using logic gates.
2. The inputs are given as per the truth table.
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3. The corresponding outputs are noted.4. The theoretical and practical values were verified.
Result:
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The odd and even parity checkers are implemented using the logic gates and the odd parity andeven parity numbers are generated using the corresponding generators.
Outcome:
At the completion of an experiment student will able to verify the odd and even parity checker
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using logic gates.--- Content provided by FirstRanker.com ---
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43 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
1. What is parity bit?2. Why parity bit is added to message?
3. What is parity checker?
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4. What is odd parity?
5. What is even parity?
6. What are the gates involved for parity generator?
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7. List the procedures to convert gray code into binary.8. Why weighted code is called as reflective codes?
9. What is a sequential code?
10. What is error deducting code?
11. What is ASCII code?
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12. What is hamming code?13. List the binary weighted code.
14. List the binary non weighted code.
15. Write the hamming code equation
16. List the procedures to convert binary code into gray
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17. What are the applications of gray code?18. What are the applications of Excess- 3 code?
Viva ? Voce
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44 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.9: MULTIPLEXER AND DEMULTIPLEXER
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Aim:
To design and verify the truth table of a 4X1 multiplexer & 1X4 demultiplexer
Apparatus required:
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Sl. No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1
2. OR gate IC 7432 1
3. NOT gate IC 7404 1
4. AND gate ( three input ) IC 7411 1
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5. Connecting wires As requiredTheory:
Multiplexing means transmitting a large number of information units over a smaller number of channels or
lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input
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lines and directs it to a single output line. The selection of particular input line is controlled by a set ofselection lines. Normally, there are 2
n
input lines and n selection lines whose bit combinations determines
which input is selected. A multiplexer is called a data selector, since it selects one of many inputs and
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steers the binary information to the output line. A Strobe is also provided to allow the designer to disable alloutput data until a specified time. Then, by allowing the STROBE to go low, the proper lead can be
selected. This feature is very useful where data might be changing the same time DATA SELECT leads
change. It is a very useful Medium Scale Integration (MSI) function and has a multitude of applications. It is
used for connecting two or more sources to a single destination among the computer units and it is useful
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for constructing a common bus system. A decoder with an enable input can function as a demultiplexer. ADemultiplexer is a circuit that receives information on a single line and transmits this information on one of
2
n
possible output lines. The selection of specific output line is controlled by the bit values of n selection
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lines. The decoder and demultiplexer operations are obtained from the same circuit; a decoder with anenable input is referred to as a decoder / de-multiplexer. The Strobe lead can be used to active or de-
active the entire IC, allowing time for the address lines to change the information is fed to the output.
Demultiplexers are useful anytime information from one source must be fed several places.
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45 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4 X 1 MULTIPLEXERCIRCUIT DIAGRAM:
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46 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1X4 DEMULTIPLEXER
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CIRCUIT DIAGRAM:
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47 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Result:
The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth tables
were verified.
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Outcome:
At the completion of an experiment student will able to design the multiplexer and the
demultiplexer
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1. What is multiplexer?
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2. What is demultiplexer?3. What are the advantages of multiplexer?
4. What are the advantages of demultiplexer?
5. What is select signal?
6. How to choose select signal in multiplexer?
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7. How to choose select signal in demultiplexer?8. Write the formula used in select signal.
9. What is the difference between the multiplexer and demultiplexer?
10. What is the application of multiplexer?
11. What is the application of demultiplexer?
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12. Draw the truth table of multiplexer.13. Draw the truth table of demultiplexer.
14. How many select signals are needed in 8*1 multiplexer?
15. How many select signals are needed in 8*1 demultiplexer?
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Viva ? Voce
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48 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
EXP NO: 11 SHIFT REGISTER
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Aim:
To design and implement the various shift register
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Apparatus required:Sl. No Name of the Apparatus Range Quantity
1. D flip flop IC 7474 2
2. OR gate IC 7432 1
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3. IC Trainer kit 15. Connecting wires As required
Theory:
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A register is capable of shifting its binary information in one or both directions isknown as shift register. The logical configuration of shift register consist of a D-Flip flop
cascaded with output of one flip flop connected to input of next flip flop. All flip flops receive
common clock pulses which causes the shift in the output of the flip flop.The simplest possible
shift register is one that uses only flip flop. The output of a given flip flop is connected to the
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input of next flip flop of the register. Each clock pulse shifts the content of register one bit positionto right.
PIN Diagram:
Logic Diagram:
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SERIAL IN SERIAL OUT--- Content provided by FirstRanker.com ---
49 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth Table:CLK Serial in Serial out
1 1 0
2 0 0
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3 0 04 1 1
5 X 0
6 X 0
7 X 1
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Logic Diagram:
Serial in parallel out:
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Truth Table:
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CLK DATAOUTPUT
Q
A
Q
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BQ
C
Q
D
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1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1
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Parallel in Serial Out:
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50 Format No.FirstRanker/stud/LM/34/issue:00/revision:00CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
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2 0 0 0 0 03 0 0 0 0 1
Truth Table:
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Parallel in Parallel Out:
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PARALLEL IN PARALLEL OUT:
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Truth Table:
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Procedure:
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1. Connections are given as per circuit diagram
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
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Result:Thus the implementation of shift registers using flip flops was completed successfully.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to design the various types of shift register.--- Content provided by FirstRanker.com ---
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CLK
DATA INPUT OUTPUT
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DA D
B D
C D
D Q
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A QB Q
C Q
D
1 1 0 0 1 1 0 0 1
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2 1 0 1 0 1 0 1 051 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.12: SYNCHRONOUS UP/DOWN COUNTER
Aim:
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To design and implement 3 bit synchronous up/down counterApparatus required:
S.No Name of the Apparatus Range Quantity
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1. JK Flip Flop IC 7474 22. OR gate IC 7432 1
3. NOT gate IC 7404 1
4. AND gate ( three input ) IC 7411 1
5 XOR gate IC 7486 1
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6 IC Trainer Kit 17. Connecting wires As required
Theory:
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A counter is a register capable of counting number of clock pulse arriving at its clock input.
Counter represents the number of clock pulses arrived. An up/down counter is one that is capable of
progressing in increasing order or decreasing order through a certain sequence. An up/down counter
is also called bidirectional counter. Usually up/down operation of the counter is controlled by up/down
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signal. When this signal is high counter goes through up sequence and when up/down signal is low counterfollows reverse sequence.
K map:
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52 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Q Q
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t+1 J K0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
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State Diagram:
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Characteristic Table:
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Logic Diagram:
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53 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Input
Up/Down
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PresentState
Q
A
Q
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BQ
C
Next State
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QA+1
Q
B+1
Q
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C+1A
J
A
K
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AB
J
B
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KB
C
J
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CK
C
0 0 0 0 1 1 1 1 X 1 X 1 X
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0 1 1 1 1 1 0 X 0 X 0 X 10 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
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0 0 1 0 0 0 1 0 X X 1 1 X0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
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1 0 1 1 1 0 0 1 X X 1 X 11 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1
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Truth Table:
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Procedure:
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1. Connections are given as per circuit diagram.2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
Result:
Thus the 3-bit synchronous up/down counters was implemented successfully.
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Outcome:At the completion of an experiment student will able to design the synchronous up/down counter.
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54 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.12:
SIMULATION OF COMBINATIONAL CIRCUITS USING HDL
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Aim:To write a verilog code for half adder, full adder and multiplexer
Tools Required:
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Xilinx 9.2Program:
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Simulation wave for half adder
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55 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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MULTIPLEXER:--- Content provided by FirstRanker.com ---
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Procedure:
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1. Write and draw the Digital logic system.
2. Write the Verilog code for above system.
3. Enter the Verilog code in Xilinx software.
4. Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and verify the
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output waveform as obtained.5. Implement the above code in Spartan III using FPGA kit.
Result:
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Thus the verilog code for half adder, full adder and multiplexer were simulated and verifiedsuccessfully.
Outcome:
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At the completion of an experiment student will able to be known the verilog code for half adder,full adder and multiplexer.
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56 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.13:
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SIMULATION OF SEQUENTIAL CIRCUITS USING HDLAim:
To write a verilog code for RS, D, JK flip flop and up counter
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Tools required:
Xilinx 9.2
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Program:RS Flip Flop:
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D Flip Flop:--- Content provided by FirstRanker.com ---
57 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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JK Flip Flop:
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Up Counter:--- Content provided by FirstRanker.com ---
58 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Result:
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Thus the verilog code for RS,D,JK Filp Flop and up counter were simulated and verified
successfully.
Outcome:
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At the completion of an experiment student will able to be known the verilog code for RS, D, JK
Filp Flop and up counter .
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59 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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ADDITIONAL EXPERIMENTS--- Content provided by FirstRanker.com ---
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60 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.8: ENCODER AND DECODER
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Aim:
To study the operation of encoder and decoder circuits using logic gates
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Apparatus required:S. No Name of the Apparatus Range Quantity
1. Digital IC trainer 1
2. NOT Gate IC 7404 1
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3. OR Gate IC 7432 14. AND Gate IC7408 1
5. Bread Board 1
6. NOT Gate IC7404 1
8. Connecting wires and probes As required
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Theory:
Decoder
In digital electronics, a decoder can take the form of a multiple-input, multiple-output logic circuit that
converts coded inputs into coded outputs, where the input and output codes are different e.g. n-to-2n ,
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binary-coded decimal decoders. Decoding is necessary in applications such as data multiplexing, 7segment display and memory address decoding.
The example decoder circuit would be an AND gate because the output of an AND gate is "High" (1) only
when all its inputs are "High." Such output is called as "active High output". If instead of AND gate, the
NAND gate is connected the output will be "Low" (0) only when all its inputs are "High". Such output is
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called as "active low output".A slightly more complex decoder would be the n-to-2n type binary decoders. These types of decoders are
combinational circuits that convert binary information from 'n' coded inputs to a maximum of 2n unique
outputs. In case the 'n' bit coded information has unused bit combinations, the decoder may have less than
2n outputs. 2-to-4 decoder, 3-to-8 decoder or 4-to-16 decoder are other examples.
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The input to a decoder is parallel binary number and it is used to detect the presence of a particularbinary number at the input. The output indicates presence or absence of specific number at the decoder
input. An encoder is a device, circuit, transducer, software program, algorithm or person that converts
information from one format or code to another. The purpose of encoder is standardization, speed,
secrecy, security, or saving space by shrinking size. Encoders are combinational logic circuits and they are
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exactly opposite of decoders. They accept one or more inputs and generate a multibit output code.Encoders perform exactly reverse operation than decoder. An encoder has M input and N output lines. Out
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61 Format No.FirstRanker/stud/LM/34/issue:00/revision:00of M input lines only one is activated at a time and produces equivalent code on output N lines. If a device
output code has fewer bits than the input code has, the device is usually called an encoder
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Sl.No. Inputs Outputs
D7 D6 D5 D4 D3 D2 D1 D0 A B C
1. 0 0 0 0 0 0 0 1 0 0 0
2. 0 0 0 0 0 0 1 0 0 0 1
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3. 0 0 0 0 0 1 0 0 0 1 04. 0 0 0 0 1 0 0 0 0 1 1
5. 0 0 0 1 0 0 0 0 1 0 0
6. 0 0 1 0 0 0 0 0 1 0 1
7. 0 1 0 0 0 0 0 0 1 1 0
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8. 1 0 0 0 0 0 0 0 1 1 1Procedure:
1. Make the circuit connections as shown in the figure.
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2. Check the corresponding truth table.Result:
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The design of the Encoder and Decoder circuit was done and the input and output were obtainedOutcome:
At the completion of an experiment student will able to design the encoder circuit and the decoder circuit
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Sl.No.
Inputs Outputs
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A B Y3 Y2 Y1 Y01. 0 0 0 0 0 1
2. 0 1 0 0 1 0
3. 1 0 0 1 0 0
4. 1 1 1 0 0 0
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62 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is Encoder?
2. What is decoder?
3. List the application of encoder.
4. List the application of decoder.
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5. Draw the truth table of encoder.6. Draw the truth table of decoder.
7. What are logic gates used encoder?
8. What are logic gates used encoder?
9. What is the difference between decoder with demultiplexer?
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10. What is the difference between encoder with multiplexer?11. How to choose the select signal in encoder?
12. How to choose the select signal in decoder?
13. Draw the logic diagram of encoder.
14. Draw the logic diagram of encoder.
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15. What is the difference between encoder with decoder?--- Content provided by FirstRanker.com ---
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Viva ? Voce
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63 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.2: IMPLEMENTATION OF BOOLEAN FUNCTIONS
Aim:
To design the logic circuit and verify the truth table of the given Boolean expression,
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F (A, B, C, D) = ? (0, 1, 2, 5, 8, 9, 10)Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
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7. EX-OR gate IC 7486 18. Connecting wires As required
Circuit diagram:
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Design:Given , F (A,B,C,D) = ? (0,1,2,5,8,9,10)
Truth table:
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FirstRanker.com - FirstRanker's Choice1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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?
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DEPARTMENT OF
COMPUTER SCIENCE ENGINEERING
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III SEMESTER - R 2017
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
Section : _______________________________________
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LABORATORY MANUAL
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2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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is committed to provide highly disciplined, conscientious and
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enterprising professionals conforming to global standards through value based quality education andtraining.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
levels
--- Content provided by FirstRanker.com ---
? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
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DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
Electrical and Electronics Engineers.
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? To provide the students rigorous learning experience to produce creative solutions to society?s
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needs.? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
concepts with strongly supported laboratory and prepare them to meet the global needs of the
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industry by continuous assessment and training.VISION
--- Content provided by FirstRanker.com ---
MISSIONVISION
MISSION
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3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
--- Content provided by FirstRanker.com ---
1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
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2. Core CompetenceTo train the students to meet the needs of core industry with an attitude of learning new
technologies.
3. Breadth
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To provide relevant training and experience to bridge the gap between theory and practice whichenable them to find solutions to problems in industry and research that contributes to the overall
development of society.
4. Professionalism
--- Content provided by FirstRanker.com ---
To inculcate professional and effective communication skills to the students to make them lead ateam and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
5. Lifelong Learning/Ethics
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To practice ethical and professional responsibilities in the organization and society withcommitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.
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f. Graduates will demonstrate skills to use modern engineering tools, software and equipment toanalyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
i. Graduates will show the understanding of impact of engineering solutions on the society and also
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will be aware of contemporary issues.j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
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--- Content provided by FirstRanker.com ---
CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
SYLLABUS
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Objectives:
The student should be made to:
? Understand the various logic gates.
? Be familiar with various combinational circuits.
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? Understand the various components used in the design of digital computers.? Be exposed to sequential circuits
? Learn to use HDL
List of experiments:
1. Verification of Boolean Theorems using basic gates.
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2. Design and implementation of combinational circuits using basic gates for arbitraryfunctions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
b. Parity generator / checker
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c. Magnitude Comparatord. Application using multiplexers
4. Design and implementation of sequential circuits:
a. Shift ?registers
b. Synchronous and asynchronous counters
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5. Coding combinational / sequential circuits using HDL.6. Design and implementation of a simple digital system (Mini Project).
Course Outcomes:
? Use Boolean simplification techniques to design a combinational hardware circuit.
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? Design and Implement combinational and sequential circuits.? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Content
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Sl.No. Name of the Experiment Page No.
1.
Verification of Boolean Theorems using Digital Logic Gates
2.
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Design and Implementation of Combinational Circuits using Basic Gates for ArbitraryFunctions, Code Converters
3.
Implementation of half adder and full adder
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4.Implementation of half subtractor and full subtractor
5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
MSI Devices
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6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
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7.Design and Implementation of Magnitude Comparator.
8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
9.
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Design and Implementation of Shift Registers.10.
Design and Implementation of Synchronous and Asynchronous Counters.
11.
Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog
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HDL Software Required).12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.1: STUDY OF BASIC GATES
Aim:
To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
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7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
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more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known asuniversal gates. Basic gates form these gates.
AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
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low.OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT gate
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A NOT gate is the physical realization of the complementation operation. The NOT gate iscalled an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
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NOR gateThe NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
EX-OR gate
An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is
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similar to OR gate but excludes the combination of both A and B being equal to one. The exclusiveOR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Procedure:
1. Connections are given as per the circuit diagram.
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2. For all the IC?s 7th
pin is grounded and 14
th
pin is given +5 supply.
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3. Apply the inputs and verify the truth table for all gates.Result:
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The truth tables of all the basic logic gates were verified.Outcome:
At the completion of an experiment student will able to verify the truth
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table of all basic gates--- Content provided by FirstRanker.com ---
1. List out the basic gate.2. Mention the universal gate.
3. How many gates presented in IC 7408?
4. What is IC?
5. What are the applications of gates?
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6. Write the truth table of AND gate.7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
10. Write the truth table of NOR gate.
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11. Write the truth table of EX- OR gate.12. What are the classifications of IC?
13. What are types of linear integrated circuit?
14. What is meant by etching?
15. What are the advantages of IC?
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16. Write the truth table of EX- NOR gate.Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.2:
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VERIFICATION OF BOOLEAN THEOREMS USING LOGICGATES
Aim: To verification of Boolean theorems using logic gates
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
--- Content provided by FirstRanker.com ---
2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 3
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7. EX-OR gate IC 7486 18. Connecting wires As required
Theory:
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BASIC Boolean Laws
1. Commutative Law
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The binary operator OR, AND is said to be commutative if,1. A+B = B+A
2. A.B=B.A
2. Associative Law
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The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
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3. Distributive LawThe binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
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4. Absorption Law
1. A+AB = A
2. A+AB =A+B
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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5. Idempotent Law
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1. A+A = A2. A.A = A
6. Complementary Law
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1. A+A' = 12. A.A' = 0
7. De Morgan ?s Theorem
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1. The complement of the sum is equal to the sum of the product of the individualcomplements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
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Design
1. Absorption Law
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A+AB = A--- Content provided by FirstRanker.com ---
2. Involution (or) Double complement Law
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A = A--- Content provided by FirstRanker.com ---
3. Idempotent Law
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1. A+A = A
2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
A+B = A.B
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5. Distributive Law
A+(B.C) = (A+B).(A+C)
Procedure:
--- Content provided by FirstRanker.com ---
1. Obtain the required IC along with the Digital trainer kit.2. Connect zero volts to GND pin and +5 volts to V
cc
.
3. Apply the inputs to the respective input pins.
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4. Verify the output with the truth table.Result:
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Thus the above stated Boolean laws are verified.Outcome:
At the completion of an experiment student will able to know the basic laws with their truth table.
--- Content provided by FirstRanker.com ---
1. What is Demorgan?s law?
2. What is associative law?
3. What is mean by compliment gate?
--- Content provided by FirstRanker.com ---
4. Explain the basic laws in digital electronics5. What is double complement?
Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.3: HALF ADDER AND FULL ADDERAim:
To design and verify the truth table of the Half Adder & Full Adder circuits
Apparatus required:
--- Content provided by FirstRanker.com ---
S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
--- Content provided by FirstRanker.com ---
4. NOT gate IC 7404 15. EX-OR gate IC 7486 1
6. Connecting wires As required
--- Content provided by FirstRanker.com ---
Theory:The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
0 + 0 = 0
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0 + 1 = 1
1 + 0 = 1
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1 + 1 = 0 (with 1 as carry)The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
significant bit is called the sum.
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Half adder:A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
Full adder:
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A combinational circuit which performs the arithmetic sum of three input bits is called full adder. Thethree input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
From the truth table, the expression for sum and carry bits of the output can be obtained as,
--- Content provided by FirstRanker.com ---
SUM = A?B?C + A?BC? + AB?C? + ABCCARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Half Adder
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Truth table:--- Content provided by FirstRanker.com ---
From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,
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S = A BCarry, C = A . B
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Circuit diagram:--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
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Full adder
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Truth table:Sl.No. Input Output
A B C S C
1. 0 0 0 0 0
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2. 0 0 1 1 03. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
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7. 1 1 0 0 18. 1 1 1 1 1
Sl.No. Input Output
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A B S C1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
4. 1 1 1 1
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17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,Sum:
--- Content provided by FirstRanker.com ---
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:--- Content provided by FirstRanker.com ---
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CARRY = AB + AC + BC
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Logic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
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1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
th
pin is grounded and 14
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thpin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
Result:
--- Content provided by FirstRanker.com ---
The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
At the completion of an experiment student will able to design the half adder circuit and the
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full adder circuit.--- Content provided by FirstRanker.com ---
19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
Aim:
--- Content provided by FirstRanker.com ---
To design and verify the truth table of the half subtractor & full subtractor circuitsApparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
--- Content provided by FirstRanker.com ---
2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
--- Content provided by FirstRanker.com ---
Theory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
subtrahend bit, hence 1 is borrowed.
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Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
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Full subtractor:A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
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From the truth table the expression for difference and borrow bits of the output can be obtainedas,
Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
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Borrow, BORR = A?BC + AB?C + ABC? +ABC--- Content provided by FirstRanker.com ---
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Half subtractor
Truth table:
--- Content provided by FirstRanker.com ---
Sl.No. Input OutputA B Difference Borrow
1. 0 0 0 0
2. 0 1 1 1
3. 1 0 1 0
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4. 1 1 0 0From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A B
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Borrow, BORR = A?. B
Logic diagram:
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
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2. Full subtractorTruth table:
Sl.No.
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Input OutputA B C Difference Borrow
1. 0 0 0 0 0
2. 0 0 1 1 1
3. 0 1 0 1 1
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4. 0 1 1 0 15. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
8. 1 1 1 1 1
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21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Difference
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Difference = A?B?C + A?BC? + AB?C? + ABC
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Borrow
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Borrow = A?B + A?C + BCCircuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.5: 4-BIT ADDER AND SUBTRACTOR
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Aim:
To design and implement 4-bit adder and subtractor using IC 7483
--- Content provided by FirstRanker.com ---
Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. IC IC 7483 1
--- Content provided by FirstRanker.com ---
3. NOT gate IC 7404 14. EX-OR gate IC 7486 1
5. Connecting wires As required
Theory:
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4 BIT Binary adder:
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected to
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the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? aredesignated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
0
and it ripples through
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the full adder to the output carry C4
.
4 BIT Binary subtractor:
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The circuit for subtracting A-B consists of an adder with inverters, placed between each data input?B? and the corresponding input of full adder. The input carry C
0
must be equal to 1 when performing
subtraction.
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4 BIT Binary adder / subtractor:The addition and subtraction operation can be combined into one circuit with one common binary
adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
becomes subtractor.
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23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PIN Diagram for IC 7483:Logic Diagram: 4-Bit Binary Diagram:
Logic diagram: 4-Bit Binary Subtractor:
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4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Truth table:
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Procedure:
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1. Connections are given as per the circuit diagrams.2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
.
Result:
--- Content provided by FirstRanker.com ---
The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table wasverified.
Outcome:
At the completion of an experiment student will able to design 4-bit binary adder and subtractor
--- Content provided by FirstRanker.com ---
Input Data A Input Data B Addition SubtractionA4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
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0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 01 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is expression for difference and borrow?
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2. Write the truth table for half adder.3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
5. Write the truth table for full subtrator.
6. Draw the logic diagram of full subtrator.
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7. What is adder?8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
10. What is combinational circuit?
11. What is different between combinational and sequential circuit?
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12. What are the gates involved for binary adder?13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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Viva ? Voce--- Content provided by FirstRanker.com ---
26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.6: MAGNITUDE COMPARATOR
Aim:
--- Content provided by FirstRanker.com ---
To design, construct and study the performance of 2 bit magnitude comparatorApparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
--- Content provided by FirstRanker.com ---
3. OR gate IC 7432 14. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
--- Content provided by FirstRanker.com ---
Theory:
The comparison of two numbers is an operator that determines one number is greater than, less
than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two
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numbers A and B and determines their relative magnitude. The outcome of the comparator is specified bythree binary variables that indicate whether A>B, A=B (or) A
Truth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:
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Pin Diagram for IC 7485:--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:
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Truth table:
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Procedure:1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
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Result:Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
comparator using logic gates.
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--- Content provided by FirstRanker.com ---
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A B A>B A=B A0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
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0 1 00 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
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1 0 00 0 0 0
0 0 0 0
0 0 0 1
0 0 0 1
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0 0 1Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
1. What is magnitude comparator?
2. What is most significant bit?
3. Explain operation of AND gate.
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4. Explain truth table of a comparator.5. Explain magnitude comparator7485 IC.
6. What is 8-bit input Magnitude Comparator?
7. What is IC?
8. Explain the k-map simplification of A>B.
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9. Explain the k-map simplification of A=B.10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
12. What is the truth table of 1-bit magnitude comparator?
13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Aim:
To design, construct and study the performance of 4-bit different code converters
(i) Binary to gray code converter
--- Content provided by FirstRanker.com ---
(ii) Gray to binary code converter(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
--- Content provided by FirstRanker.com ---
4. NOT gate IC 7404 15. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:The availability of large variety of codes for the same discrete elements of information results in
the use of different codes by different systems. A conversion circuit must be inserted between the two
systems if each uses different codes for same information. Thus, code converter is a circuit that makes the
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two systems compatible even though each uses different binary code. The bit combination assigned tobinary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a
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circuit that makes the two systems compatible even though each uses a different binary code. To convertfrom binary code to Excess-3 code, the input lines must supply the bit combination of elements as
specified by code and the output lines generate the corresponding bit combination of code. Each one of the
four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are
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various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output isC+D has been used to implement partially each of three outputs.
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Logic diagram:32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(i) Binary to gray code converter
Logic Diagram:
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K map for G3:
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G3 = B3K map for G2:
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K map for G1:33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for G0:Truth table:
--- Content provided by FirstRanker.com ---
0
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
11
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
0
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
--- Content provided by FirstRanker.com ---
11
1
0
0
--- Content provided by FirstRanker.com ---
0
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
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11
0
0
1
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10
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(ii) Gray to binary code converter
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34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:K map for B3:
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B3=G3
K map for B2:
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
G3 G2 G1 G0 B3 B2 B1 B0
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0
0
0
0
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00
0
0
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
0
0
0
0
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11
1
1
0
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00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
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11
0
0
1
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10
0
1
1
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00
1
1
--- Content provided by FirstRanker.com ---
01
0
1
0
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10
1
0
1
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01
0
1
0
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1K map for B1:
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K map for B0:
Truth table:
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(iii) BCD to excess-3 code converterLogic Diagram:
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K map for E3:E3 = B3 + B2 (B0 + B1)
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K map for E2:--- Content provided by FirstRanker.com ---
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for E1:--- Content provided by FirstRanker.com ---
K map for E0:--- Content provided by FirstRanker.com ---
Truth table:
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(iv) Excess-3 toB3 B2 B1 B0 G3 G2 G1 G0
0
0
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00
0
0
0
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01
1
1
1
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11
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
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11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
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10
1
0
1
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01
0
1
0
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10
1
0
1
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0
0
0
0
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01
1
1
1
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1x
x
x
x
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xx
0
1
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11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
x
x
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xx
x
x
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10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
xx
x
x
x
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x1
0
1
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01
0
1
0
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10
x
x
x
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xx
x
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38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
BCD code converter
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Logic Diagram:K map for A:
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A = X1 X2 + X3 X4 X1
K map for B:
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--- Content provided by FirstRanker.com ---
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39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
K map for C:--- Content provided by FirstRanker.com ---
K map for D:--- Content provided by FirstRanker.com ---
Truth table:--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
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B3 B2 B1 B0 G3 G2 G1 G0
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00
0
0
0
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11
1
1
1
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0
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
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11
0
0
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11
0
0
1
--- Content provided by FirstRanker.com ---
10
1
0
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10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
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11
1
0
0
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0
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
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00
1
0
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10
1
0
1
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01
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40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Procedure:
1. Connections were given as per circuit diagram.
2. Logical inputs were given as per truth table
3. Observe the logical output and verify with the truth tables.
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Result:
Thus the code converters were designed and verified using the corresponding truth table.
Outcome:
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At the completion of an experiment student will able to design the binary to gray converter.1. What is binary code?
2. What is gray code?
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3. What are the advantages of gray code?4. What is unit distance code?
5. What is sequential code?
6. How to convert binary to gray code?
7. How to convert gray to binary code?
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8. What is reflective code?9. What are the advantages of EX ? 3 code?
10. Which code is used to arithmetic operation in digital circuits?
11. Explain the operation of EX ? OR.
12. What is K ? Map?
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13. Draw the truth table of EX- OR gate.14. What is SOP?
15. What is POS?
16. What is minterm?
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Viva ? Voce--- Content provided by FirstRanker.com ---
41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.8: PARITY GENERATORS AND CHECKERS
Aim:
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To implement the odd and even parity checkers using the logic gates and also to generate the odd parityand even parity numbers using the generators
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl. No Component Type Quantity1 Trainer Kit - 1
2 EX-OR IC7486 1
3 NOT gate IC 7404 1
4 Connecting wires - Required
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Theory:
Parity checking is used for error detection in data transmission.
Odd parity checkers:
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It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
odd.
Even parity checker:
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It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
even.
Odd parity generators:
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It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also
the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bits
which is an odd parity number.
Even parity generator:
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It generates an even parity number. The even parity checker circuit is used with the inverted output and
also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5
bits which is an even parity number.
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42 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Truth table:
Input Checker output Generator output
A B C D D odd even odd even
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0 0 0 1 1 0 00010 000110 0 1 0 1 0 00100 00101
0 0 1 1 0 1 00111 00110
0 1 0 0 1 0 01000 01001
0 1 0 1 0 1 01011 01010
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0 1 1 0 0 1 01101 011000 1 1 1 1 0 01110 01111
1 0 0 0 1 0 10000 10001
1 0 0 1 0 1 10011 10010
1 0 1 0 0 1 10101 10100
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1 0 1 1 1 0 10110 101111 1 0 0 0 1 11001 11000
1 1 0 1 1 0 11010 11011
1 1 1 0 1 0 11100 11101
1 1 1 1 0 1 11111 11110
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Procedure:
1. The circuit is implemented using logic gates.
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2. The inputs are given as per the truth table.
3. The corresponding outputs are noted.
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4. The theoretical and practical values were verified.Result:
The odd and even parity checkers are implemented using the logic gates and the odd parity and
even parity numbers are generated using the corresponding generators.
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Outcome:
At the completion of an experiment student will able to verify the odd and even parity checker
using logic gates.
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43 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
1. What is parity bit?
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2. Why parity bit is added to message?3. What is parity checker?
4. What is odd parity?
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5. What is even parity?6. What are the gates involved for parity generator?
7. List the procedures to convert gray code into binary.
8. Why weighted code is called as reflective codes?
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9. What is a sequential code?10. What is error deducting code?
11. What is ASCII code?
12. What is hamming code?
13. List the binary weighted code.
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14. List the binary non weighted code.15. Write the hamming code equation
16. List the procedures to convert binary code into gray
17. What are the applications of gray code?
18. What are the applications of Excess- 3 code?
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Viva ? Voce--- Content provided by FirstRanker.com ---
44 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.9: MULTIPLEXER AND DEMULTIPLEXER
Aim:
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To design and verify the truth table of a 4X1 multiplexer & 1X4 demultiplexerApparatus required:
Sl. No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. OR gate IC 7432 13. NOT gate IC 7404 1
4. AND gate ( three input ) IC 7411 1
5. Connecting wires As required
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Theory:Multiplexing means transmitting a large number of information units over a smaller number of channels or
lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input
lines and directs it to a single output line. The selection of particular input line is controlled by a set of
selection lines. Normally, there are 2
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ninput lines and n selection lines whose bit combinations determines
which input is selected. A multiplexer is called a data selector, since it selects one of many inputs and
steers the binary information to the output line. A Strobe is also provided to allow the designer to disable all
output data until a specified time. Then, by allowing the STROBE to go low, the proper lead can be
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selected. This feature is very useful where data might be changing the same time DATA SELECT leadschange. It is a very useful Medium Scale Integration (MSI) function and has a multitude of applications. It is
used for connecting two or more sources to a single destination among the computer units and it is useful
for constructing a common bus system. A decoder with an enable input can function as a demultiplexer. A
Demultiplexer is a circuit that receives information on a single line and transmits this information on one of
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2n
possible output lines. The selection of specific output line is controlled by the bit values of n selection
lines. The decoder and demultiplexer operations are obtained from the same circuit; a decoder with an
enable input is referred to as a decoder / de-multiplexer. The Strobe lead can be used to active or de-
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active the entire IC, allowing time for the address lines to change the information is fed to the output.Demultiplexers are useful anytime information from one source must be fed several places.
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45 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
4 X 1 MULTIPLEXER
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CIRCUIT DIAGRAM:--- Content provided by FirstRanker.com ---
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46 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
1X4 DEMULTIPLEXER
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CIRCUIT DIAGRAM:
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47 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Result:The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth tables
were verified.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to design the multiplexer and thedemultiplexer
--- Content provided by FirstRanker.com ---
1. What is multiplexer?
2. What is demultiplexer?
3. What are the advantages of multiplexer?
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4. What are the advantages of demultiplexer?5. What is select signal?
6. How to choose select signal in multiplexer?
7. How to choose select signal in demultiplexer?
8. Write the formula used in select signal.
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9. What is the difference between the multiplexer and demultiplexer?10. What is the application of multiplexer?
11. What is the application of demultiplexer?
12. Draw the truth table of multiplexer.
13. Draw the truth table of demultiplexer.
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14. How many select signals are needed in 8*1 multiplexer?15. How many select signals are needed in 8*1 demultiplexer?
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Viva ? Voce--- Content provided by FirstRanker.com ---
48 Format No.FirstRanker/stud/LM/34/issue:00/revision:00EXP NO: 11 SHIFT REGISTER
Aim:
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To design and implement the various shift register
Apparatus required:
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Sl. No Name of the Apparatus Range Quantity1. D flip flop IC 7474 2
2. OR gate IC 7432 1
3. IC Trainer kit 1
5. Connecting wires As required
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Theory:
A register is capable of shifting its binary information in one or both directions is
known as shift register. The logical configuration of shift register consist of a D-Flip flop
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cascaded with output of one flip flop connected to input of next flip flop. All flip flops receivecommon clock pulses which causes the shift in the output of the flip flop.The simplest possible
shift register is one that uses only flip flop. The output of a given flip flop is connected to the
input of next flip flop of the register. Each clock pulse shifts the content of register one bit position
to right.
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PIN Diagram:Logic Diagram:
SERIAL IN SERIAL OUT
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49 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Truth Table:
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CLK Serial in Serial out1 1 0
2 0 0
3 0 0
4 1 1
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5 X 06 X 0
7 X 1
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Logic Diagram:Serial in parallel out:
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Truth Table:
CLK DATA
OUTPUT
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QA
Q
B
Q
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CQ
D
1 1 1 0 0 0
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2 0 0 1 0 03 0 0 0 1 1
4 1 1 0 0 1
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Parallel in Serial Out:--- Content provided by FirstRanker.com ---
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50 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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CLK Q3 Q2 Q1 Q0 O/P0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1
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Truth Table:
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Parallel in Parallel Out:--- Content provided by FirstRanker.com ---
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PARALLEL IN PARALLEL OUT:--- Content provided by FirstRanker.com ---
Truth Table:
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Procedure:
1. Connections are given as per circuit diagram
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2. Logical inputs are given as per circuit diagram.3. Observe the output and verify the truth table.
Result:
--- Content provided by FirstRanker.com ---
Thus the implementation of shift registers using flip flops was completed successfully.Outcome:
At the completion of an experiment student will able to design the various types of shift register.
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CLK
DATA INPUT OUTPUT
D
A D
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B DC D
D Q
A Q
B Q
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C QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
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51 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.12: SYNCHRONOUS UP/DOWN COUNTER
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Aim:
To design and implement 3 bit synchronous up/down counter
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Apparatus required:S.No Name of the Apparatus Range Quantity
1. JK Flip Flop IC 7474 2
2. OR gate IC 7432 1
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3. NOT gate IC 7404 14. AND gate ( three input ) IC 7411 1
5 XOR gate IC 7486 1
6 IC Trainer Kit 1
7. Connecting wires As required
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Theory:
A counter is a register capable of counting number of clock pulse arriving at its clock input.
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Counter represents the number of clock pulses arrived. An up/down counter is one that is capable ofprogressing in increasing order or decreasing order through a certain sequence. An up/down counter
is also called bidirectional counter. Usually up/down operation of the counter is controlled by up/down
signal. When this signal is high counter goes through up sequence and when up/down signal is low counter
follows reverse sequence.
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K map:
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52 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Q Q
t+1 J K
0 0 0 X
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0 1 1 X1 0 X 1
1 1 X 0
State Diagram:
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Characteristic Table:
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Logic Diagram:
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53 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Input
Up/Down
Present
State
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QA
Q
B
Q
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CNext State
Q
A+1
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QB+1
Q
C+1
A
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JA
K
A
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BJ
B
K
B
--- Content provided by FirstRanker.com ---
C
J
C
K
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C0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
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0 1 0 1 1 0 0 X 0 0 X X 10 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
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1 0 0 0 0 0 1 0 X 0 X 1 X1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
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1 1 0 1 1 1 0 X 0 1 X X 11 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1
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Truth Table:--- Content provided by FirstRanker.com ---
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Procedure:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
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3. Observe the output and verify the truth table.Result:
Thus the 3-bit synchronous up/down counters was implemented successfully.
Outcome:
--- Content provided by FirstRanker.com ---
At the completion of an experiment student will able to design the synchronous up/down counter.--- Content provided by FirstRanker.com ---
54 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.12:
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SIMULATION OF COMBINATIONAL CIRCUITS USING HDL
Aim:
--- Content provided by FirstRanker.com ---
To write a verilog code for half adder, full adder and multiplexerTools Required:
Xilinx 9.2
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Program:
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Simulation wave for half adder--- Content provided by FirstRanker.com ---
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55 Format No.FirstRanker/stud/LM/34/issue:00/revision:00MULTIPLEXER:
--- Content provided by FirstRanker.com ---
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Procedure:
1. Write and draw the Digital logic system.
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2. Write the Verilog code for above system.3. Enter the Verilog code in Xilinx software.
4. Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and verify the
output waveform as obtained.
5. Implement the above code in Spartan III using FPGA kit.
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Result:
Thus the verilog code for half adder, full adder and multiplexer were simulated and verified
successfully.
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Outcome:
At the completion of an experiment student will able to be known the verilog code for half adder,
full adder and multiplexer.
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56 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Expt.No.13:
SIMULATION OF SEQUENTIAL CIRCUITS USING HDL
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Aim:To write a verilog code for RS, D, JK flip flop and up counter
Tools required:
--- Content provided by FirstRanker.com ---
Xilinx 9.2
Program:
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RS Flip Flop:--- Content provided by FirstRanker.com ---
D Flip Flop:
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57 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
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JK Flip Flop:
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Up Counter:
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58 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
Result:
Thus the verilog code for RS,D,JK Filp Flop and up counter were simulated and verified
--- Content provided by FirstRanker.com ---
successfully.Outcome:
At the completion of an experiment student will able to be known the verilog code for RS, D, JK
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Filp Flop and up counter .--- Content provided by FirstRanker.com ---
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59 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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ADDITIONAL EXPERIMENTS
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60 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.8: ENCODER AND DECODER
Aim:
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To study the operation of encoder and decoder circuits using logic gates
Apparatus required:
--- Content provided by FirstRanker.com ---
S. No Name of the Apparatus Range Quantity1. Digital IC trainer 1
2. NOT Gate IC 7404 1
3. OR Gate IC 7432 1
4. AND Gate IC7408 1
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5. Bread Board 16. NOT Gate IC7404 1
8. Connecting wires and probes As required
Theory:
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DecoderIn digital electronics, a decoder can take the form of a multiple-input, multiple-output logic circuit that
converts coded inputs into coded outputs, where the input and output codes are different e.g. n-to-2n ,
binary-coded decimal decoders. Decoding is necessary in applications such as data multiplexing, 7
segment display and memory address decoding.
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The example decoder circuit would be an AND gate because the output of an AND gate is "High" (1) onlywhen all its inputs are "High." Such output is called as "active High output". If instead of AND gate, the
NAND gate is connected the output will be "Low" (0) only when all its inputs are "High". Such output is
called as "active low output".
A slightly more complex decoder would be the n-to-2n type binary decoders. These types of decoders are
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combinational circuits that convert binary information from 'n' coded inputs to a maximum of 2n uniqueoutputs. In case the 'n' bit coded information has unused bit combinations, the decoder may have less than
2n outputs. 2-to-4 decoder, 3-to-8 decoder or 4-to-16 decoder are other examples.
The input to a decoder is parallel binary number and it is used to detect the presence of a particular
binary number at the input. The output indicates presence or absence of specific number at the decoder
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input. An encoder is a device, circuit, transducer, software program, algorithm or person that convertsinformation from one format or code to another. The purpose of encoder is standardization, speed,
secrecy, security, or saving space by shrinking size. Encoders are combinational logic circuits and they are
exactly opposite of decoders. They accept one or more inputs and generate a multibit output code.
Encoders perform exactly reverse operation than decoder. An encoder has M input and N output lines. Out
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61 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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of M input lines only one is activated at a time and produces equivalent code on output N lines. If a deviceoutput code has fewer bits than the input code has, the device is usually called an encoder
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Sl.No. Inputs Outputs
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D7 D6 D5 D4 D3 D2 D1 D0 A B C1. 0 0 0 0 0 0 0 1 0 0 0
2. 0 0 0 0 0 0 1 0 0 0 1
3. 0 0 0 0 0 1 0 0 0 1 0
4. 0 0 0 0 1 0 0 0 0 1 1
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5. 0 0 0 1 0 0 0 0 1 0 06. 0 0 1 0 0 0 0 0 1 0 1
7. 0 1 0 0 0 0 0 0 1 1 0
8. 1 0 0 0 0 0 0 0 1 1 1
Procedure:
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1. Make the circuit connections as shown in the figure.
2. Check the corresponding truth table.
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Result:
The design of the Encoder and Decoder circuit was done and the input and output were obtained
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Outcome:At the completion of an experiment student will able to design the encoder circuit and the decoder circuit
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Sl.No.
Inputs Outputs
A B Y3 Y2 Y1 Y0
1. 0 0 0 0 0 1
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2. 0 1 0 0 1 03. 1 0 0 1 0 0
4. 1 1 1 0 0 0
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62 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
1. What is Encoder?
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2. What is decoder?3. List the application of encoder.
4. List the application of decoder.
5. Draw the truth table of encoder.
6. Draw the truth table of decoder.
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7. What are logic gates used encoder?8. What are logic gates used encoder?
9. What is the difference between decoder with demultiplexer?
10. What is the difference between encoder with multiplexer?
11. How to choose the select signal in encoder?
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12. How to choose the select signal in decoder?13. Draw the logic diagram of encoder.
14. Draw the logic diagram of encoder.
15. What is the difference between encoder with decoder?
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Viva ? Voce--- Content provided by FirstRanker.com ---
63 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.2: IMPLEMENTATION OF BOOLEAN FUNCTIONS
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Aim:
To design the logic circuit and verify the truth table of the given Boolean expression,
F (A, B, C, D) = ? (0, 1, 2, 5, 8, 9, 10)
Apparatus required:
--- Content provided by FirstRanker.com ---
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
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4. NOT gate IC 7404 15. NAND gate IC 7400 1
6. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
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Circuit diagram:
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Design:
Given , F (A,B,C,D) = ? (0,1,2,5,8,9,10)
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Truth table:--- Content provided by FirstRanker.com ---
64 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Sl. No.
INPUT OUTPUT
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A B C D F=D?B?+C?(B?+A?D)1. 0 0 0 0 1
2. 0 0 0 1 1
3. 0 0 1 0 1
4. 0 0 1 1 0
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5. 0 1 0 0 06. 0 1 0 1 1
7. 0 1 1 0 0
8. 0 1 1 1 0
9. 1 0 0 0 1
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10. 1 0 0 1 111. 1 0 1 0 1
12. 1 0 1 1 0
13. 1 1 0 0 0
14. 1 1 0 1 0
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15. 1 1 1 0 016. 1 1 1 1 0
The output function F has four input variables hence a four variable Karnaugh Map is used to obtain a
simplified expression for the output as shown,
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From the K-Map,F = B? C? + D? B? + A? C? D
Since we are using only two input logic gates the above expression can be re-written as,
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F = C? (B? + A? D) + D? B?Now the logic circuit for the above equation can be drawn.
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FirstRanker.com - FirstRanker's Choice
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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
?DEPARTMENT OF
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COMPUTER SCIENCE ENGINEERINGIII SEMESTER - R 2017
CS8382 DIGITAL SYSTEMS LABORATORY
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Name : _______________________________________
Register No : _______________________________________
Section : _______________________________________
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LABORATORY MANUAL
--- Content provided by FirstRanker.com ---
2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
is committed to provide highly disciplined, conscientious andenterprising professionals conforming to global standards through value based quality education and
training.
--- Content provided by FirstRanker.com ---
? To provide competent technical manpower capable of meeting requirements of the industry
? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different
--- Content provided by FirstRanker.com ---
levels? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on
heart and soul
--- Content provided by FirstRanker.com ---
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
--- Content provided by FirstRanker.com ---
To provide candidates with knowledge and skill in the field of Electrical and Electronics
Engineering and thereby produce extremely well trained employable, socially responsible and innovative
--- Content provided by FirstRanker.com ---
Electrical and Electronics Engineers.--- Content provided by FirstRanker.com ---
? To provide the students rigorous learning experience to produce creative solutions to society?sneeds.
? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to
professional ethical code.
? To provide highest quality learning environment for the students emphasizing fundamental
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concepts with strongly supported laboratory and prepare them to meet the global needs of theindustry by continuous assessment and training.
VISION
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MISSION
VISION
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MISSION--- Content provided by FirstRanker.com ---
3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
--- Content provided by FirstRanker.com ---
1. Fundamentals
To provide students with a solid foundation in mathematics, science and fundamentals of
engineering enabling them to solve complex problems in order to develop real time applications.
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2. Core Competence
To train the students to meet the needs of core industry with an attitude of learning new
technologies.
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3. BreadthTo provide relevant training and experience to bridge the gap between theory and practice which
enable them to find solutions to problems in industry and research that contributes to the overall
development of society.
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4. ProfessionalismTo inculcate professional and effective communication skills to the students to make them lead a
team and stand as a good decision maker to manage any constraint environment with good
professional ethics at all strategies.
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5. Lifelong Learning/EthicsTo practice ethical and professional responsibilities in the organization and society with
commitment and lifelong learning needed for successful professional career.
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4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00PROGRAM OUTCOMES (POs)
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a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.
b. Graduates will be able to identify, formulate and solve electrical engineering problems.
c. Graduates will be able to design and conduct experiments, analyze and interpret data.
d. Graduates will be able to design a system, component or process as per needs and specifications.
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e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to
analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduates will be able to communicate effectively by both verbal and written form.
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i. Graduates will show the understanding of impact of engineering solutions on the society and alsowill be aware of contemporary issues.
j. Graduates will develop confidence for self-education and ability for lifelong learning.
k. Graduate who can participate and succeed in competitive examinations.
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CS8381 DIGITAL SYSTEMS LABORATORY
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5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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SYLLABUSObjectives:
The student should be made to:
? Understand the various logic gates.
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? Be familiar with various combinational circuits.? Understand the various components used in the design of digital computers.
? Be exposed to sequential circuits
? Learn to use HDL
List of experiments:
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1. Verification of Boolean Theorems using basic gates.2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
a. 4 ? bit binary adder / subtractor
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b. Parity generator / checkerc. Magnitude Comparator
d. Application using multiplexers
4. Design and implementation of sequential circuits:
a. Shift ?registers
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b. Synchronous and asynchronous counters5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
Course Outcomes:
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? Use Boolean simplification techniques to design a combinational hardware circuit.? Design and Implement combinational and sequential circuits.
? Analyze a given digital circuit ? combinational and sequential.
? Design the different functional units in a digital computer system.
? Design and Implement a simple digital system.
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CS8381 DIGITAL SYSTEMS LABORATORY
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6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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ContentSl.No. Name of the Experiment Page No.
1.
Verification of Boolean Theorems using Digital Logic Gates
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2.Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary
Functions, Code Converters
3.
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Implementation of half adder and full adder4.
Implementation of half subtractor and full subtractor
5.
Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and
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MSI Devices6.
Design and Implementation of Parity Generator / Checker using Basic Gates and MSI
Devices
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7.
Design and Implementation of Magnitude Comparator.
8.
Design and Implementation of Application using Multiplexers / Demultiplexers.
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9.Design and Implementation of Shift Registers.
10.
Design and Implementation of Synchronous and Asynchronous Counters.
11.
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Simulation of Combinational Circuits using Hardware Description Language (VHDL / VerilogHDL Software Required).
12.
Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).
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7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.1: STUDY OF BASIC GATES
Aim:
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To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gatesApparatus required:
Sl.No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
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6. NOR gate IC 7402 17. EX-OR gate IC 7486 1
8. Connecting wires As required
Theory:
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Circuit that takes the logical decision and the process are called logic gates. Each gate has one ormore input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND gate
The AND gate performs a logical multiplication commonly known as AND function. The
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output is high when both the inputs are high. The output is low level when any one of the inputs islow.
OR gate
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
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NOT gateA NOT gate is the physical realization of the complementation operation. The NOT gate is
called an inverter. The output is high when the input is low. The output is low when the input is high.
NAND gate
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
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and any one of the input is low .The output is low level when both inputs are high.NOR gate
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
EX-OR gate
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An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It issimilar to OR gate but excludes the combination of both A and B being equal to one. The exclusive
OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.
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8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
AND Gate Symbol: PIN Diagram:
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OR Gate:
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OR GATE:
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9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NOT Gate symbol: PIN Diagram:
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EXOR Gate symbol: PIN Diagram:
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10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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NAND Gate symbol: PIN Diagram:
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NOR Gate:
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11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Procedure:
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1. Connections are given as per the circuit diagram.2. For all the IC?s 7
th
pin is grounded and 14
th
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pin is given +5 supply.3. Apply the inputs and verify the truth table for all gates.
Result:
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The truth tables of all the basic logic gates were verified.
Outcome:
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At the completion of an experiment student will able to verify the truthtable of all basic gates
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1. List out the basic gate.
2. Mention the universal gate.
3. How many gates presented in IC 7408?
4. What is IC?
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5. What are the applications of gates?6. Write the truth table of AND gate.
7. Write the truth table of OR gate.
8. Write the truth table of NOT gate.
9. Write the truth table of NAND gate.
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10. Write the truth table of NOR gate.11. Write the truth table of EX- OR gate.
12. What are the classifications of IC?
13. What are types of linear integrated circuit?
14. What is meant by etching?
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15. What are the advantages of IC?16. Write the truth table of EX- NOR gate.
Viva ? Voce
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12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.2:
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VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES
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Aim: To verification of Boolean theorems using logic gatesApparatus required:
Sl.No Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
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6. NOR gate IC 7402 37. EX-OR gate IC 7486 1
8. Connecting wires As required
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Theory:BASIC Boolean Laws
1. Commutative Law
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The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A
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2. Associative LawThe binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
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3. Distributive Law
The binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
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2. A.(B+C) = (A.B)+(A.C)4. Absorption Law
1. A+AB = A
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2. A+AB =A+B--- Content provided by FirstRanker.com ---
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13 Format No.FirstRanker/stud/LM/34/issue:00/revision:005. Idempotent Law
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1. A+A = A
2. A.A = A
6. Complementary Law
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1. A+A' = 1
2. A.A' = 0
7. De Morgan ?s Theorem
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1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
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A.B = A+BDesign
1. Absorption Law
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A+AB = A
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2. Involution (or) Double complement Law
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A = A
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3. Idempotent Law1. A+A = A
2. A.A = A
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14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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4. Demorgan ?s Law
A+B = A.B
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5. Distributive Law
A+(B.C) = (A+B).(A+C)
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Procedure:1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to V
cc
.
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3. Apply the inputs to the respective input pins.4. Verify the output with the truth table.
Result:
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Thus the above stated Boolean laws are verified.
Outcome:
At the completion of an experiment student will able to know the basic laws with their truth table.
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1. What is Demorgan?s law?
2. What is associative law?
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3. What is mean by compliment gate?4. Explain the basic laws in digital electronics
5. What is double complement?
Viva ? Voce
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15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.3: HALF ADDER AND FULL ADDER
Aim:
To design and verify the truth table of the Half Adder & Full Adder circuits
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Apparatus required:S. No. Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required
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Theory:
The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
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0 + 0 = 00 + 1 = 1
1 + 0 = 1
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1 + 1 = 0 (with 1 as carry)
The first three operations produce a sum of whose length is one digit, but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry and lower
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significant bit is called the sum.Half adder:
A combinational circuit which performs the addition of two bits is called half adder. The input variables
designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.
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Full adder:A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The
three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented
with two half adders and one OR gate.
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From the truth table, the expression for sum and carry bits of the output can be obtained as,SUM = A?B?C + A?BC? + AB?C? + ABC
CARRY = A?BC + AB?C + ABC? +ABC
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16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Half AdderTruth table:
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,S = A B
Carry, C = A . B
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Circuit diagram:
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Full adderTruth table:
Sl.No. Input Output
A B C S C
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1. 0 0 0 0 02. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
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6. 1 0 1 0 17. 1 1 0 0 1
8. 1 1 1 1 1
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Sl.No. Input OutputA B S C
1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
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4. 1 1 1 117 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,
Sum:
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SUM = A?B?C + A?BC? + AB?C? + ABC = A B C
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Carry:
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CARRY = AB + AC + BCLogic Diagram:
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18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Procedure:1. Connections are given as per the circuit diagrams.
2. For all the IC?s 7
th
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pin is grounded and 14th
pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
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Result:The design of the half adder and full adder circuits was done and their truth tables were verified.
Outcome:
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At the completion of an experiment student will able to design the half adder circuit and thefull adder circuit.
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19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR
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Aim:To design and verify the truth table of the half subtractor & full subtractor circuits
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
--- Content provided by FirstRanker.com ---
1. Digital IC trainer kit 12. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
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6. Connecting wires As requiredTheory:
The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit
is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the
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subtrahend bit, hence 1 is borrowed.Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
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difference and borrow bits.Full subtractor:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
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From the truth table the expression for difference and borrow bits of the output can be obtained
as,
Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC
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Borrow, BORR = A?BC + AB?C + ABC? +ABC
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20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Half subtractor
Truth table:
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Sl.No. Input Output
A B Difference Borrow
1. 0 0 0 0
2. 0 1 1 1
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3. 1 0 1 04. 1 1 0 0
From the truth table the expression for difference and borrow bits of the output can be obtained as,
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Difference, DIFF = A BBorrow, BORR = A?. B
Logic diagram:
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2. Full subtractor
Truth table:
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Sl.No.Input Output
A B C Difference Borrow
1. 0 0 0 0 0
2. 0 0 1 1 1
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3. 0 1 0 1 14. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
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8. 1 1 1 1 1--- Content provided by FirstRanker.com ---
21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
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Difference--- Content provided by FirstRanker.com ---
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Difference = A?B?C + A?BC? + AB?C? + ABCBorrow
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Borrow = A?B + A?C + BC
Circuit diagram:
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22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.5: 4-BIT ADDER AND SUBTRACTORAim:
To design and implement 4-bit adder and subtractor using IC 7483
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Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. IC IC 7483 13. NOT gate IC 7404 1
4. EX-OR gate IC 7486 1
5. Connecting wires As required
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Theory:4 BIT Binary adder:
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
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constructed with full adders connected in cascade, with the output carry from each full adder connected tothe input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through full adder. The input carry to the adder is C
0
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and it ripples throughthe full adder to the output carry C
4
.
4 BIT Binary subtractor:
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The circuit for subtracting A-B consists of an adder with inverters, placed between each data input
?B? and the corresponding input of full adder. The input carry C
0
must be equal to 1 when performing
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subtraction.4 BIT Binary adder / subtractor:
The addition and subtraction operation can be combined into one circuit with one common binary
adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it
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becomes subtractor.23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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PIN Diagram for IC 7483:
Logic Diagram: 4-Bit Binary Diagram:
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Logic diagram: 4-Bit Binary Subtractor:4-Bit Binary Adder /Subtractor:
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24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Truth table:--- Content provided by FirstRanker.com ---
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Procedure:1. Connections are given as per the circuit diagrams.
2. Logical inputs were given as per circuit diagram.
3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.
.
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Result:The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was
verified.
Outcome:
At the completion of an experiment student will able to design 4-bit binary adder and subtractor
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Input Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
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0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 00 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
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1. What is expression for difference and borrow?2. Write the truth table for half adder.
3. Write the truth table for full adder.
4. Write the truth table for half subtrator.
5. Write the truth table for full subtrator.
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6. Draw the logic diagram of full subtrator.7. What is adder?
8. List out the application of adders.
9. Draw the full adder using two half adder circuits.
10. What is combinational circuit?
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11. What is different between combinational and sequential circuit?12. What are the gates involved for binary adder?
13. List the properties of Ex-Nor gate?
14. What is expression for sum and carry?
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Viva ? Voce
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26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.6: MAGNITUDE COMPARATOR
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Aim:To design, construct and study the performance of 2 bit magnitude comparator
Apparatus required:
Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
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2. AND gate IC 7408 13. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
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7. Connecting wires As requiredTheory:
The comparison of two numbers is an operator that determines one number is greater than, less
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than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares twonumbers A and B and determines their relative magnitude. The outcome of the comparator is specified by
three binary variables that indicate whether A>B, A=B (or) A
Truth table:
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27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K-map
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28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Logic Diagram:
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Pin Diagram for IC 7485:
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Logic Diagram:
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29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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8 Bit Magnitude Comparator:
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Truth table:
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Procedure:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
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Result:
Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.
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Outcome:At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude
comparator using logic gates.
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A B A>B A=B A0 0 0 0
0 0 0 0
0 0 0 0
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0 0 0 00 1 0
0 0 0 1
0 0 0 1
0 0 0 0
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0 0 0 01 0 0
0 0 0 0
0 0 0 0
0 0 0 1
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0 0 0 10 0 1
Viva ? Voce
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30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is magnitude comparator?
2. What is most significant bit?
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3. Explain operation of AND gate.4. Explain truth table of a comparator.
5. Explain magnitude comparator7485 IC.
6. What is 8-bit input Magnitude Comparator?
7. What is IC?
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8. Explain the k-map simplification of A>B.9. Explain the k-map simplification of A=B.
10. Explain the k-map simplification of A11. Draw the logic diagram of 1-bit magnitude comparator.
12. What is the truth table of 1-bit magnitude comparator?
13. What is the use of magnitude comparator?
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Expt.No.7: CODE CONVERSION
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31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Aim:
To design, construct and study the performance of 4-bit different code converters
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(i) Binary to gray code converter(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. Magnitude comparator IC 7485 2
6. EX-OR gate IC 7486 1
7. Connecting wires As required
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Theory:
The availability of large variety of codes for the same discrete elements of information results in
the use of different codes by different systems. A conversion circuit must be inserted between the two
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systems if each uses different codes for same information. Thus, code converter is a circuit that makes thetwo systems compatible even though each uses different binary code. The bit combination assigned to
binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs
and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0
and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
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designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is acircuit that makes the two systems compatible even though each uses a different binary code. To convert
from binary code to Excess-3 code, the input lines must supply the bit combination of elements as
specified by code and the output lines generate the corresponding bit combination of code. Each one of the
four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-
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level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These arevarious other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is
C+D has been used to implement partially each of three outputs.
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Logic diagram:
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32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00(i) Binary to gray code converter
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Logic Diagram:K map for G3:
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G3 = B3
K map for G2:
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K map for G1:
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33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
K map for G0:
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Truth table:0
0
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00
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
--- Content provided by FirstRanker.com ---
00
0
0
1
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11
1
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
0
0
0
0
--- Content provided by FirstRanker.com ---
00
0
0
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
11
1
1
1
--- Content provided by FirstRanker.com ---
00
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
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11
0
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(ii) Gray to binary code converter
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34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Logic Diagram:
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K map for B3:B3=G3
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K map for B2:--- Content provided by FirstRanker.com ---
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35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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G3 G2 G1 G0 B3 B2 B1 B00
0
0
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00
0
0
0
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11
1
1
1
--- Content provided by FirstRanker.com ---
11
1
0
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00
0
1
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
10
0
0
0
--- Content provided by FirstRanker.com ---
0
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
1
1
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
0
--- Content provided by FirstRanker.com ---
01
1
0
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00
0
0
0
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00
0
1
1
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11
1
1
1
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10
0
0
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01
1
1
1
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00
0
0
1
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11
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
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11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
0
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
K map for B1:
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K map for B0:
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Truth table:--- Content provided by FirstRanker.com ---
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36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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(iii) BCD to excess-3 code converter
Logic Diagram:
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K map for E3:
E3 = B3 + B2 (B0 + B1)
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K map for E2:
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37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for E1:
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K map for E0:
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Truth table:
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(iv) Excess-3 to
B3 B2 B1 B0 G3 G2 G1 G0
0
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00
0
0
0
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00
1
1
1
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11
1
1
1
--- Content provided by FirstRanker.com ---
0
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
11
0
0
--- Content provided by FirstRanker.com ---
11
0
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
1
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
0
0
--- Content provided by FirstRanker.com ---
00
1
1
1
--- Content provided by FirstRanker.com ---
11
x
x
x
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xx
x
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
x
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xx
x
x
x
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1
0
0
1
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10
0
1
1
--- Content provided by FirstRanker.com ---
0x
x
x
x
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xx
1
0
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10
1
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1
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01
0
x
x
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xx
x
x
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38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
BCD code converter
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Logic Diagram:
K map for A:
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A = X1 X2 + X3 X4 X1
K map for B:
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39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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K map for C:
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K map for D:
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Truth table:
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B3 B2 B1 B0 G3 G2 G1 G0
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0
0
0
0
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01
1
1
1
--- Content provided by FirstRanker.com ---
10
1
1
--- Content provided by FirstRanker.com ---
11
0
0
0
--- Content provided by FirstRanker.com ---
01
1
0
--- Content provided by FirstRanker.com ---
01
1
0
0
--- Content provided by FirstRanker.com ---
11
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
0
--- Content provided by FirstRanker.com ---
00
0
0
0
--- Content provided by FirstRanker.com ---
00
0
1
1
--- Content provided by FirstRanker.com ---
0
0
0
0
--- Content provided by FirstRanker.com ---
11
1
1
0
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
10
0
1
1
--- Content provided by FirstRanker.com ---
00
0
1
--- Content provided by FirstRanker.com ---
01
0
1
0
--- Content provided by FirstRanker.com ---
10
1
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40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
--- Content provided by FirstRanker.com ---
Procedure:
1. Connections were given as per circuit diagram.
2. Logical inputs were given as per truth table
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3. Observe the logical output and verify with the truth tables.Result:
Thus the code converters were designed and verified using the corresponding truth table.
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Outcome:At the completion of an experiment student will able to design the binary to gray converter.
1. What is binary code?
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2. What is gray code?3. What are the advantages of gray code?
4. What is unit distance code?
5. What is sequential code?
6. How to convert binary to gray code?
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7. How to convert gray to binary code?8. What is reflective code?
9. What are the advantages of EX ? 3 code?
10. Which code is used to arithmetic operation in digital circuits?
11. Explain the operation of EX ? OR.
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12. What is K ? Map?13. Draw the truth table of EX- OR gate.
14. What is SOP?
15. What is POS?
16. What is minterm?
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Viva ? Voce
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41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.8: PARITY GENERATORS AND CHECKERS
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Aim:To implement the odd and even parity checkers using the logic gates and also to generate the odd parity
and even parity numbers using the generators
Apparatus required:
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Sl. No Component Type Quantity
1 Trainer Kit - 1
2 EX-OR IC7486 1
3 NOT gate IC 7404 1
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4 Connecting wires - RequiredTheory:
Parity checking is used for error detection in data transmission.
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Odd parity checkers:It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
odd.
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Even parity checker:It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is
even.
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Odd parity generators:It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also
the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bits
which is an odd parity number.
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Even parity generator:It generates an even parity number. The even parity checker circuit is used with the inverted output and
also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5
bits which is an even parity number.
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42 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Truth table:
Input Checker output Generator output
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A B C D D odd even odd even0 0 0 1 1 0 00010 00011
0 0 1 0 1 0 00100 00101
0 0 1 1 0 1 00111 00110
0 1 0 0 1 0 01000 01001
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0 1 0 1 0 1 01011 010100 1 1 0 0 1 01101 01100
0 1 1 1 1 0 01110 01111
1 0 0 0 1 0 10000 10001
1 0 0 1 0 1 10011 10010
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1 0 1 0 0 1 10101 101001 0 1 1 1 0 10110 10111
1 1 0 0 0 1 11001 11000
1 1 0 1 1 0 11010 11011
1 1 1 0 1 0 11100 11101
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1 1 1 1 0 1 11111 11110Procedure:
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1. The circuit is implemented using logic gates.2. The inputs are given as per the truth table.
3. The corresponding outputs are noted.
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4. The theoretical and practical values were verified.
Result:
The odd and even parity checkers are implemented using the logic gates and the odd parity and
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even parity numbers are generated using the corresponding generators.Outcome:
At the completion of an experiment student will able to verify the odd and even parity checker
using logic gates.
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43 Format No.FirstRanker/stud/LM/34/issue:00/revision:001. What is parity bit?
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2. Why parity bit is added to message?
3. What is parity checker?
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4. What is odd parity?5. What is even parity?
6. What are the gates involved for parity generator?
7. List the procedures to convert gray code into binary.
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8. Why weighted code is called as reflective codes?9. What is a sequential code?
10. What is error deducting code?
11. What is ASCII code?
12. What is hamming code?
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13. List the binary weighted code.14. List the binary non weighted code.
15. Write the hamming code equation
16. List the procedures to convert binary code into gray
17. What are the applications of gray code?
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18. What are the applications of Excess- 3 code?Viva ? Voce
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44 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Expt.No.9: MULTIPLEXER AND DEMULTIPLEXER
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Aim:To design and verify the truth table of a 4X1 multiplexer & 1X4 demultiplexer
Apparatus required:
Sl. No Name of the Apparatus Range Quantity
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1. Digital IC trainer kit 12. OR gate IC 7432 1
3. NOT gate IC 7404 1
4. AND gate ( three input ) IC 7411 1
5. Connecting wires As required
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Theory:
Multiplexing means transmitting a large number of information units over a smaller number of channels or
lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input
lines and directs it to a single output line. The selection of particular input line is controlled by a set of
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selection lines. Normally, there are 2n
input lines and n selection lines whose bit combinations determines
which input is selected. A multiplexer is called a data selector, since it selects one of many inputs and
steers the binary information to the output line. A Strobe is also provided to allow the designer to disable all
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output data until a specified time. Then, by allowing the STROBE to go low, the proper lead can beselected. This feature is very useful where data might be changing the same time DATA SELECT leads
change. It is a very useful Medium Scale Integration (MSI) function and has a multitude of applications. It is
used for connecting two or more sources to a single destination among the computer units and it is useful
for constructing a common bus system. A decoder with an enable input can function as a demultiplexer. A
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Demultiplexer is a circuit that receives information on a single line and transmits this information on one of2
n
possible output lines. The selection of specific output line is controlled by the bit values of n selection
lines. The decoder and demultiplexer operations are obtained from the same circuit; a decoder with an
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enable input is referred to as a decoder / de-multiplexer. The Strobe lead can be used to active or de-active the entire IC, allowing time for the address lines to change the information is fed to the output.
Demultiplexers are useful anytime information from one source must be fed several places.
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45 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
4 X 1 MULTIPLEXER
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CIRCUIT DIAGRAM:
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46 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1X4 DEMULTIPLEXER--- Content provided by FirstRanker.com ---
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47 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Result:
The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth tables
were verified.
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Outcome:At the completion of an experiment student will able to design the multiplexer and the
demultiplexer
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1. What is multiplexer?
2. What is demultiplexer?
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3. What are the advantages of multiplexer?4. What are the advantages of demultiplexer?
5. What is select signal?
6. How to choose select signal in multiplexer?
7. How to choose select signal in demultiplexer?
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8. Write the formula used in select signal.9. What is the difference between the multiplexer and demultiplexer?
10. What is the application of multiplexer?
11. What is the application of demultiplexer?
12. Draw the truth table of multiplexer.
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13. Draw the truth table of demultiplexer.14. How many select signals are needed in 8*1 multiplexer?
15. How many select signals are needed in 8*1 demultiplexer?
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Viva ? Voce
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48 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
EXP NO: 11 SHIFT REGISTER
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Aim:To design and implement the various shift register
Apparatus required:
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Sl. No Name of the Apparatus Range Quantity
1. D flip flop IC 7474 2
2. OR gate IC 7432 1
3. IC Trainer kit 1
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5. Connecting wires As requiredTheory:
A register is capable of shifting its binary information in one or both directions is
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known as shift register. The logical configuration of shift register consist of a D-Flip flopcascaded with output of one flip flop connected to input of next flip flop. All flip flops receive
common clock pulses which causes the shift in the output of the flip flop.The simplest possible
shift register is one that uses only flip flop. The output of a given flip flop is connected to the
input of next flip flop of the register. Each clock pulse shifts the content of register one bit position
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to right.PIN Diagram:
Logic Diagram:
SERIAL IN SERIAL OUT
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49 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Truth Table:
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CLK Serial in Serial out
1 1 0
2 0 0
3 0 0
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4 1 15 X 0
6 X 0
7 X 1
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Logic Diagram:
Serial in parallel out:
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Truth Table:
CLK DATA
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OUTPUTQ
A
Q
B
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QC
Q
D
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1 1 1 0 0 02 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1
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Parallel in Serial Out:
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50 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
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3 0 0 0 0 1Truth Table:
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Parallel in Parallel Out:
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PARALLEL IN PARALLEL OUT:
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Truth Table:
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Procedure:
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1. Connections are given as per circuit diagram2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
Result:
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Thus the implementation of shift registers using flip flops was completed successfully.
Outcome:
At the completion of an experiment student will able to design the various types of shift register.
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CLK
DATA INPUT OUTPUT
D
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A DB D
C D
D Q
A Q
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B QC Q
D
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
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51 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.12: SYNCHRONOUS UP/DOWN COUNTERAim:
To design and implement 3 bit synchronous up/down counter
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Apparatus required:
S.No Name of the Apparatus Range Quantity
1. JK Flip Flop IC 7474 2
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2. OR gate IC 7432 13. NOT gate IC 7404 1
4. AND gate ( three input ) IC 7411 1
5 XOR gate IC 7486 1
6 IC Trainer Kit 1
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7. Connecting wires As requiredTheory:
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A counter is a register capable of counting number of clock pulse arriving at its clock input.Counter represents the number of clock pulses arrived. An up/down counter is one that is capable of
progressing in increasing order or decreasing order through a certain sequence. An up/down counter
is also called bidirectional counter. Usually up/down operation of the counter is controlled by up/down
signal. When this signal is high counter goes through up sequence and when up/down signal is low counter
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follows reverse sequence.K map:
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52 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
Q Q
t+1 J K
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0 0 0 X0 1 1 X
1 0 X 1
1 1 X 0
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State Diagram:--- Content provided by FirstRanker.com ---
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Characteristic Table:
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Logic Diagram:
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53 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Input
Up/Down
Present
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StateQ
A
Q
B
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QC
Next State
Q
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A+1Q
B+1
Q
C+1
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AJ
A
K
A
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B
J
B
K
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BC
J
C
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KC
0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
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0 1 1 0 1 0 1 X 0 X 1 1 X0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
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0 0 0 1 0 0 0 0 X 0 X X 11 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
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1 1 0 0 1 0 1 X 0 0 X 1 X1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1
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Truth Table:
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Procedure:
1. Connections are given as per circuit diagram.
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2. Logical inputs are given as per circuit diagram.3. Observe the output and verify the truth table.
Result:
Thus the 3-bit synchronous up/down counters was implemented successfully.
Outcome:
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At the completion of an experiment student will able to design the synchronous up/down counter.
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54 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.12:SIMULATION OF COMBINATIONAL CIRCUITS USING HDL
Aim:
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To write a verilog code for half adder, full adder and multiplexer
Tools Required:
Xilinx 9.2
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Program:
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Simulation wave for half adder
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55 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
MULTIPLEXER:
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Procedure:
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1. Write and draw the Digital logic system.2. Write the Verilog code for above system.
3. Enter the Verilog code in Xilinx software.
4. Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and verify the
output waveform as obtained.
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5. Implement the above code in Spartan III using FPGA kit.Result:
Thus the verilog code for half adder, full adder and multiplexer were simulated and verified
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successfully.Outcome:
At the completion of an experiment student will able to be known the verilog code for half adder,
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full adder and multiplexer.--- Content provided by FirstRanker.com ---
56 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.13:
SIMULATION OF SEQUENTIAL CIRCUITS USING HDL
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Aim:
To write a verilog code for RS, D, JK flip flop and up counter
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Tools required:Xilinx 9.2
Program:
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RS Flip Flop:
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D Flip Flop:
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57 Format No.FirstRanker/stud/LM/34/issue:00/revision:00--- Content provided by FirstRanker.com ---
JK Flip Flop:
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Up Counter:
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58 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Result:
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Thus the verilog code for RS,D,JK Filp Flop and up counter were simulated and verifiedsuccessfully.
Outcome:
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At the completion of an experiment student will able to be known the verilog code for RS, D, JKFilp Flop and up counter .
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59 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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ADDITIONAL EXPERIMENTS
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60 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Expt.No.8: ENCODER AND DECODER
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Aim:To study the operation of encoder and decoder circuits using logic gates
Apparatus required:
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S. No Name of the Apparatus Range Quantity
1. Digital IC trainer 1
2. NOT Gate IC 7404 1
3. OR Gate IC 7432 1
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4. AND Gate IC7408 15. Bread Board 1
6. NOT Gate IC7404 1
8. Connecting wires and probes As required
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Theory:Decoder
In digital electronics, a decoder can take the form of a multiple-input, multiple-output logic circuit that
converts coded inputs into coded outputs, where the input and output codes are different e.g. n-to-2n ,
binary-coded decimal decoders. Decoding is necessary in applications such as data multiplexing, 7
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segment display and memory address decoding.The example decoder circuit would be an AND gate because the output of an AND gate is "High" (1) only
when all its inputs are "High." Such output is called as "active High output". If instead of AND gate, the
NAND gate is connected the output will be "Low" (0) only when all its inputs are "High". Such output is
called as "active low output".
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A slightly more complex decoder would be the n-to-2n type binary decoders. These types of decoders arecombinational circuits that convert binary information from 'n' coded inputs to a maximum of 2n unique
outputs. In case the 'n' bit coded information has unused bit combinations, the decoder may have less than
2n outputs. 2-to-4 decoder, 3-to-8 decoder or 4-to-16 decoder are other examples.
The input to a decoder is parallel binary number and it is used to detect the presence of a particular
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binary number at the input. The output indicates presence or absence of specific number at the decoderinput. An encoder is a device, circuit, transducer, software program, algorithm or person that converts
information from one format or code to another. The purpose of encoder is standardization, speed,
secrecy, security, or saving space by shrinking size. Encoders are combinational logic circuits and they are
exactly opposite of decoders. They accept one or more inputs and generate a multibit output code.
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Encoders perform exactly reverse operation than decoder. An encoder has M input and N output lines. Out61 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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of M input lines only one is activated at a time and produces equivalent code on output N lines. If a device
output code has fewer bits than the input code has, the device is usually called an encoder
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Sl.No. Inputs OutputsD7 D6 D5 D4 D3 D2 D1 D0 A B C
1. 0 0 0 0 0 0 0 1 0 0 0
2. 0 0 0 0 0 0 1 0 0 0 1
3. 0 0 0 0 0 1 0 0 0 1 0
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4. 0 0 0 0 1 0 0 0 0 1 15. 0 0 0 1 0 0 0 0 1 0 0
6. 0 0 1 0 0 0 0 0 1 0 1
7. 0 1 0 0 0 0 0 0 1 1 0
8. 1 0 0 0 0 0 0 0 1 1 1
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Procedure:1. Make the circuit connections as shown in the figure.
2. Check the corresponding truth table.
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Result:
The design of the Encoder and Decoder circuit was done and the input and output were obtained
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Outcome:
At the completion of an experiment student will able to design the encoder circuit and the decoder circuit
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Sl.No.
Inputs Outputs
A B Y3 Y2 Y1 Y0
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1. 0 0 0 0 0 12. 0 1 0 0 1 0
3. 1 0 0 1 0 0
4. 1 1 1 0 0 0
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62 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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1. What is Encoder?2. What is decoder?
3. List the application of encoder.
4. List the application of decoder.
5. Draw the truth table of encoder.
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6. Draw the truth table of decoder.7. What are logic gates used encoder?
8. What are logic gates used encoder?
9. What is the difference between decoder with demultiplexer?
10. What is the difference between encoder with multiplexer?
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11. How to choose the select signal in encoder?12. How to choose the select signal in decoder?
13. Draw the logic diagram of encoder.
14. Draw the logic diagram of encoder.
15. What is the difference between encoder with decoder?
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Viva ? Voce
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63 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Expt.No.2: IMPLEMENTATION OF BOOLEAN FUNCTIONSAim:
To design the logic circuit and verify the truth table of the given Boolean expression,
F (A, B, C, D) = ? (0, 1, 2, 5, 8, 9, 10)
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Apparatus required:Sl.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
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3. OR gate IC 7432 14. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
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8. Connecting wires As requiredCircuit diagram:
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Design:
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Given , F (A,B,C,D) = ? (0,1,2,5,8,9,10)Truth table:
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64 Format No.FirstRanker/stud/LM/34/issue:00/revision:00
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Sl. No.
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INPUT OUTPUTA B C D F=D?B?+C?(B?+A?D)
1. 0 0 0 0 1
2. 0 0 0 1 1
3. 0 0 1 0 1
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4. 0 0 1 1 05. 0 1 0 0 0
6. 0 1 0 1 1
7. 0 1 1 0 0
8. 0 1 1 1 0
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9. 1 0 0 0 110. 1 0 0 1 1
11. 1 0 1 0 1
12. 1 0 1 1 0
13. 1 1 0 0 0
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14. 1 1 0 1 015. 1 1 1 0 0
16. 1 1 1 1 0
The output function F has four input variables hence a four variable Karnaugh Map is used to obtain a
simplified expression for the output as shown,
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From the K-Map,
F = B? C? + D? B? + A? C? D
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Since we are using only two input logic gates the above expression can be re-written as,F = C? (B? + A? D) + D? B?
Now the logic circuit for the above equation can be drawn.
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65 Format No.FirstRanker/stud/LM/34/issue:00/revision:00Procedure:
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1. Connections are given as per the circuit diagram.2. For all the IC?s 7
th
pin is grounded and 14
th
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pin is given +5 V supply.3. Apply the inputs and verify the truth table for the given Boolean expression.
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Result:The truth table of the given Boolean expression was verified.
Outcome:
At the completion of an experiment student will able to design the Boolean expression.
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