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Download GTU BE/B.Tech 2019 Winter 4th Sem New 2140910 Digital Electronics Question Paper

Download GTU (Gujarat Technological University) BE/BTech (Bachelor of Engineering / Bachelor of Technology) 2019 Winter 4th Sem New 2140910 Digital Electronics Previous Question Paper

This post was last modified on 20 February 2020

GTU BE/B.Tech 2019 Winter Question Papers || Gujarat Technological University


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GUJARAT TECHNOLOGICAL UNIVERSITY
BE - SEMESTER- IV (New) EXAMINATION - WINTER 2019

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Subject Code: 2140910 Date: 10/12/2019
Subject Name: Digital Electronics
Time: 10:30 AM TO 01:00 PM Total Marks: 70

Instructions:

  1. Attempt all questions.
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  3. Make suitable assumptions wherever necessary.
  4. Figures to the right indicate full marks.

MARKS

Q.1 Do as instructed (Each question carry two marks) 14

  1. How to convert Binary to Gray Code? Explain with necessary diagrams.
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  3. Convert: (ABC)16 = ( )10 = ( )8
  4. Add (-258)10 to (-48)10 using 2's compliments method.
  5. Subtract (108)10 from (93)10 using 2's compliments method.
  6. Add (-7)10 to (-8)10 using 1's compliments method.
  7. Convert (4500)10 =( )16 = ( )8
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  9. Define Excess - 3 code with suitable example.

Q.2

  1. Explain TTL logic family with necessary sketches and truth table. 03
  2. Define universal gates. Design different types of gate using each universal gates. 04
  3. Design & explain full subtractor with truth table and circuit diagrams. 07
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OR

  1. Design & explain how two half adders can make one full adder with truth table and circuit diagrams. 07

Q.3

  1. Explain following with examples 03
    1. Minterm
    2. Maxterm
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    4. Don't care
  2. Reduce the following function using K-map. 04
    Y = Sm (0,2,4,6,9,13,21,23,25,29,31)
  3. Reduce the following function using tabulation method 07

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    Y = Sm(0,2,3,6,7,8,9,10,13)

OR

  1. Explain following with examples 03
    1. POS
    2. SOP
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  3. Demonstrate the validity of the De Morgan’s theorems by truth tables. 04
  4. Reduce following function with help of Boolean expression. Also realize the expression with NAND gate. 07
    Y = (A+B) (A+(B+C')) +A' (B+C)

Q.4

  1. Derive Excitation tables for J-K flip flop. 03
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  3. Explain SIPO shift register with necessary circuit diagram. 04
  4. Explain J - K master slave flip flop with necessary sketches and truth table. 07

OR

  1. Derive Excitation tables for S-R flip flop. 03
  2. Explain PIPO shift register with necessary circuit diagram. 04
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  4. Design modulo - 10 counter with timing diagrams. 07

Q.5

  1. Define following terms: 03
    1. Resolution
    2. Linearity
    3. Accuracy
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  2. Explain R -2R ladder method for D/A converter with necessary circuit diagrams. 07

OR

  1. Explain Sample and Hold circuit. 03
  2. Write a short note on memory organization. 04
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  4. Explain successive approximation method for A/D converter with circuit diagram. 07

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