GUJARAT TECHNOLOGICAL UNIVERSITY
BE - SEMESTER- VI (New) EXAMINATION - WINTER 2019
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Subject Code: 2161101 Date: 11/12/2019
Subject Name: VLSI Technology & Design
Time: 02:30 PM TO 05:00 PM Total Marks: 70
Instructions:
- Attempt all questions.
- Make suitable assumptions wherever necessary.
- Figures to the right indicate full marks.
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MARKS
Q.1 (a) Draw VLSI design flow with block diagram. 03
(b) Differentiate between FPGA and CPLD 04
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(c) Discuss various packaging technology used for VLSI chips. 07
Q.2 (a) Explain the concept of MOSFET as a switch. 03
(b) Justify that size of PMOS transistor chosen to be 2.5 times of an 04 NMOS transistor.
(c) Design a resistive load inverter with RL=1KQ, such that VOL = 07 0.6V. The enhancement type driver transistor has the following parameters: Vad =5V, V1o =1V, y=0.2 V1/2, L =0, pnCox = 22 nA/VZ Determine
- Require aspect ratio. W/L
- VL and Vi and
- noise margin NMr and NMy
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OR
(c) Draw the inverter circuit with depletion type nMOS load. Mention 07 the operating regions of driver and load transistors for different input voltages. Derive the expression of critical voltages Vir,Vor, Vs, Von.
Q.3 (a) Define following Terms: 03
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- Threshold Voltage
- Noise Margin
- Propagation Delay
(b) Explain: Substrate bias effect. 04
(c) Explain the energy band diagram of MOS structure at surface 07 inversion and derive the expression for the maximum possible depth of the depletion region.
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OR
Q.3 (a) Draw CMOS Inverter circuit and voltage transfer characteristics. 03 Mention different operating region of NMOS and PMOS on VTC.
(b) Derive expression for frequency of oscillation for three stage ring 04 oscillator circuit. Draw necessary circuit and waveforms.
(c) Derive the expression of tpuL of a CMOS inverter using differential 07 equation method.
Q.4 (a) Discuss the effect of Full scaling(constant-Field scaling) on: (1) Cox 03 (i) Ip
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(b) Derive Req of all regions in CMOS Transmission gates 04
(c) Implement and Describe CMOS clocked RS flip-flop. 07
Q.4 (a) Draw two-input CMOS NOR and NAND gate circuits. 03
(b) Which are the four general criteria to measure design quality of a 04 fabricated integrated circuit (chip)? Briefly explain each of them.
(c) Realize the following Boolean function using CMOS Transmission 07 Gates. F=AB+A’C’+AB’C
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Q.5 (a) Draw the circuit diagram of domino CMOS logic gate. 03
(b) Explain Voltage bootstrapping. 04
(c) Implement and Describe CMOS clocked JK flip-flop. 07
OR
Q.5 (a) Draw general layout of an H-tree clock distribution network. 03
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(b) Describe in brief : Built in Self Test (BIST) 04
(c) What is Latch up? Explain the prevention techniques. 07
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