Download GTU BE/B.Tech 2019 Summer 4th Sem New 2140910 Digital Electronics Question Paper

Download GTU (Gujarat Technological University) BE/BTech (Bachelor of Engineering / Bachelor of Technology) 2019 Summer 4th Sem New 2140910 Digital Electronics Previous Question Paper

1
Seat No.: ________ Enrolment No.___________
GUJARAT TECHNOLOGICAL UNIVERSITY
BE - SEMESTER ?IV(NEW) ? EXAMINATION ? SUMMER 2019
Subject Code:2140910 Date:13/05/2019
Subject Name: Digital Electronics
Time: 02:30 PM TO 05:00 PM Total Marks: 70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
1. Figures to the right indicate full marks.

MARKS

Q.1 (a) Find the XS-3 code of following decimal numbers
(i) 26 (ii) 42 (iii) 63

03
(b) Differentiate between combinational logic circuit and sequential
logic circuit.

04
(c) Explain why NAND and NOR are known as universal gates and
construct AND, OR and NOT using the universal gates.

07
Q.2 (a) Convert the following Binary to Gray Code
(i)1001 (ii)1010 (iii) 1011

03
(b)
Convert the following
(i) (4CD)16 = ( )2
(ii) (26.24)8 = ( )10

04
(c) Simplify Y=A?BCD? + BCD? + BC?D? + BC?D and implement using
NAND gate only.

07
OR
(c) State and explain De Morgan?s theorems with truth tables.

07
Q.3 (a) Explain minterm and maxterm.

03
(b) Add 27.125 to -79.625 using 12-bit 2?s complement arithmetic.

04
(c) Minimize using K-map f(A,B,C,D) = ?(1,3,4,6,8,11,15)
+d(0,5,7) also draw MSI circuit for the output.

07
OR
Q.3 (a) Explain parity checking method of error detection.

03
(b) Perform the decimal subtraction 206.7-147.8 in 8421 BCD code.

04
(c) Discuss 4 ? bit magnitude comparator in detail. 07
Q.4 (a) Explain full adder.

03
(b) Explain R-2R ladder DAC with necessary diagram.

04
(c) Draw 4 bit down counter, explain its working with timing diagram and
truth table.
07
OR
Q.4 (a) Discuss multiplexer with suitable diagram.

03
(b) Explain terms Accuracy and settling time for DAC.

04
(c) Describe 3 to 8 line decoder with logic diagram and truth table. 07
Q.5 (a) Compare SRAM with DRAM.

03
(b) Draw the two input TTL NAND gate circuit with totem pole output.

04
(c) Describe operation of D/A converter with binary ? weighted resistors. 07
OR

Q.5 (a) Compare SOP and POS.

03
(b) Give comparison between EPROM and FLASH memory.

04
(c) Describe the working of look-ahead-carry adder.

07
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