Seat No.:
Enrolment No.
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GUJARAT TECHNOLOGICAL UNIVERSITY
BE - SEMESTER-VIII(OLD) EXAMINATION - WINTER 2017
Subject Code: 180802 Date: 02-11-2017
Subject Name: VLSI Technologies
Time: 02:30 pm TO 5:00 pm Total Marks: 70
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Instructions:
- Attempt all questions.
- Make suitable assumptions wherever necessary.
- Figures to the right indicate full marks.
Q-1 (a) Explain the VLSI design flow by Y-chart and its simplified view
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(b) Discuss basic steps of fabrication.
Q2 (a) Explain Channel Length Modulation
(b) Explain energy band diagram of MOS structure at surface inversion and derive the equation of threshold voltage.
OR
Derive the expression for drain current as a function of VGS, VDS and VSB for all three region of operation of MOSFET using Gradual Channel Approximation.
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Q2 (b) Explain the functioning of depletion load nMOS inverter and derive critical voltage points VOH, VOL, VIL and VIH.
Q3 (a) Give the delay time definitions and calculation of delay times.
OR
(b) Draw two types of enhancement — load n-MOS inverter circuits and compare both.
Q3 (a) Write a short note on MOSFET Capacitance.
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(b) Concept of regularity, modularity and locality.
Q4 (a) Explain Device Isolation Technique and Locos.
OR
(b) Write a short note on FPGA.
Q4 (a) Explain CMOS Transmission gates (or Pass Gates).
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(b) Ad HOC testable design techniques
(b) Explain the basic principle of pass transistor circuit. Explain logic “1” transfer and logic “0” transfer.
OR
(b) Explain the criteria to measure the design quality to improve the chip design and explain any two in brief.
(b) Write a short note on Built In Self Test (BIST).
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