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Download PTU B.Tech 2020 March CSE-IT 3rd Sem CS 205 Digital Circuits & Logic Design Question Paper

Download PTU (I.K. Gujral Punjab Technical University Jalandhar (IKGPTU) ) BE/BTech CSE/IT (Computer Science And Engineering/ Information Technology) 2020 March 3rd Sem CS 205 Digital Circuits & Logic Design Previous Question Paper

This post was last modified on 21 March 2020

This download link is referred from the post: PTU B.Tech Question Papers 2020 March (All Branches)


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Roll No.

Total No. of Pages : 02

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Total No. of Questions : 18

B.Tech (CSE) (Sem.-3)

DIGITAL CIRCUITS & LOGIC DESIGN

Subject Code : CS-205

M.Code : 56503

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Time : 3 Hrs. Max. Marks : 60

INSTRUCTIONS TO CANDIDATES :

  1. SECTION-A is COMPULSORY consisting of TEN questions carrying TWO marks each.
  2. SECTION-B contains FIVE questions carrying FIVE marks each and students have to attempt any FOUR questions.
  3. SECTION-C contains THREE questions carrying TEN marks each and students have to attempt any TWO questions.
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SECTION-A

Write briefly :

  1. Explain the working of OR, AND and NOT gates.
  2. Distinguish between SOP and POS forms!
  3. What are minimization techniques?
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  5. What do you mean by toggle?
  6. What are Min and Max terms?
  7. What is the use of A/D and D/A conversions?
  8. What are shift registers?
  9. Draw the circuit diagram of a 8-input multiplexer.
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  11. What is the race condition in S-R flip-flop? How is it resolved in D-flip-flop?
  12. Define a Flip-Flop with a suitable sketch?

SECTION-B

  1. What is PLA? Design BCD to Excess-3 code convertor using PLA.
  2. What is a ROM? What are its types? Give characteristics of each.
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  4. Convert D flip-flop to JK flip flop.
  5. Draw a circuit for the 4-input successive operation A/D convertor. Discuss its limitations.
  6. Reduce the following function using Karnaugh map technique : F(A,B,C,D) = Σ m(5,6,7,12,13) + Σ d(4,9,14,15)

SECTION-C

  1. Explain the step-wise process for the sequential circuit design using state tables.
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  3. What is a Programmable logic devices? What are their advantages? Explain in detail the architecture of a programmable logic device.
  4. a) Implement the function F= A’BC+ ABC’+A’BC’+AC" using PAL.
    b) With the help of a diagram explain the working of R-2R ladder type DAC.

NOTE : Disclosure of identity by writing mobile number or making passing request on any page of Answer sheet will lead to UMC case against the Student.


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This download link is referred from the post: PTU B.Tech Question Papers 2020 March (All Branches)