Download PTU B.Tech 2020 March ECE 6th Sem BTEC 904 Digital System Design Question Paper

Download PTU (I.K. Gujral Punjab Technical University Jalandhar (IKGPTU) ) BE/BTech ECE (Electronics And Communications Engineering) 2020 March 6th Sem BTEC 904 Digital System Design Previous Question Paper

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Roll No. Total No. of Pages : 02
Total No. of Questions : 09
B.Tech.(ECE) (E-I 2012 to 2017) (Sem.?6)
DIGITAL SYSTEM DESIGN
Subject Code : BTEC-904
M.Code : 71233
Time : 3 Hrs. Max. Marks : 60
INSTRUCTIONS TO CANDIDATES :
1. SECTION-A is COMPULSORY consisting of TEN questions carrying TWO marks
each.
2. SECTION-B contains FIVE questions carrying FIVE marks each and students
have to attempt any FOUR questions.
3. SECTION-C contains THREE questions carrying TEN marks each and students
have to attempt any TWO questions.

SECTION-A
1. Answer briefly :
(a) What is combinational logic circuit?
(b) What is difference between PLA and PAL?
(c) Explain the JK flip flop excitation table.
(d) Define synchronous sequential circuit.
(e) Write two limitations of finite state machine.
(f) What is mealy machine?
(g) What are the rules for the conversion of state diagram to an ASM chart?
(h) What is Hazards?
(i) State the purpose of programmable logic devices.
(j) Explain AND PLD notation.
SECTION-B
2. Design and explain 4 to 1 channel multiplexer.
3. Explain the differences among a truth table, a state table, a characteristic table, and an
excitation table. Also, explain the difference among a Boolean equation, a state equation,
a characteristic equation, and a flip-flop input equation.
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1 | M - 7 1 2 3 3 ( S 2 ) - 2 1 1 4
Roll No. Total No. of Pages : 02
Total No. of Questions : 09
B.Tech.(ECE) (E-I 2012 to 2017) (Sem.?6)
DIGITAL SYSTEM DESIGN
Subject Code : BTEC-904
M.Code : 71233
Time : 3 Hrs. Max. Marks : 60
INSTRUCTIONS TO CANDIDATES :
1. SECTION-A is COMPULSORY consisting of TEN questions carrying TWO marks
each.
2. SECTION-B contains FIVE questions carrying FIVE marks each and students
have to attempt any FOUR questions.
3. SECTION-C contains THREE questions carrying TEN marks each and students
have to attempt any TWO questions.

SECTION-A
1. Answer briefly :
(a) What is combinational logic circuit?
(b) What is difference between PLA and PAL?
(c) Explain the JK flip flop excitation table.
(d) Define synchronous sequential circuit.
(e) Write two limitations of finite state machine.
(f) What is mealy machine?
(g) What are the rules for the conversion of state diagram to an ASM chart?
(h) What is Hazards?
(i) State the purpose of programmable logic devices.
(j) Explain AND PLD notation.
SECTION-B
2. Design and explain 4 to 1 channel multiplexer.
3. Explain the differences among a truth table, a state table, a characteristic table, and an
excitation table. Also, explain the difference among a Boolean equation, a state equation,
a characteristic equation, and a flip-flop input equation.
2 | M - 7 1 2 3 3 ( S 2 ) - 2 1 1 4
4. Differentiate Moore and Mealy machines.
5. Draw the block diagram of Asynchronous Sequential circuits and explain it.
6. Explain how to remove hazards? For a circuit shown below draw a hazards free circuit.


SECTION-C
7. A sequential circuit has two JK flip-flops A and B and one input x. The circuit is
described by the following flip-flop input equations :
J
A
= x K
A
= B
J
B
= x K
B
= A'
(a) Derive the state equations A (t + 1) and B (t + 1) by substituting the input equations
for the J and K variables. (7)
(b) Draw the state diagram of the circuit. (3)
8. Draw and explain the general structure of PLDs. Draw a simple four-input, three-output
PAL derive. (7+3)
9. Convert the state diagram of Fig. below to ASM chart. (10)

NOTE : Disclosure of Identity by writing Mobile No. or Making of passing request on any
page of Answer Sheet will lead to UMC against the Student.
x
1
=1
x
2
x
3
=1
1 0 ?
0 1 ?
0 1 ?
1 0 ?
1
2
3
1
?Y
(a) AND-OR circuit
1/1
1/1
S
0
S
1
S
2
0/0
0/0 1/0
0/1
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