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Download PTU B.Tech 2020 March ME 7th Sem Vlsi Design Question Paper

Download PTU (I.K. Gujral Punjab Technical University Jalandhar (IKGPTU) ) BE/BTech ME (Marine Engineering) 2020 March 7th Sem Vlsi Design Previous Question Paper

This post was last modified on 21 March 2020

PTU B.Tech Question Papers 2020 March (All Branches)


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Roll No. Total No. of Pages : 02

Total No. of Questions : 09

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B.Tech. (ECSE) (Sem.-7)

VLSI DESIGN

Subject Code : BTEC-604

M.Code : 72170

Time : 3 Hrs. Max. Marks : 60

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INSTRUCTIONS TO CANDIDATES :

  1. SECTION-A is COMPULSORY consisting of TEN questions carrying TWO marks each.
  2. SECTION-B contains FIVE questions carrying FIVE marks each and students have to attempt any FOUR questions.
  3. SECTION-C contains THREE questions carrying TEN marks each and students have to attempt any TWO questions.

SECTION-A

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  1. Write briefly :
    1. State the advantages of VHDL.
    2. What is transport delay? How does it differ from inertial delay?
    3. What is the range of natural and real data types in VHDL?
    4. How is a generic statement useful in VHDL code?
    5. Differentiate between synthesis and simulation.
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    7. Explain type declaration and its usage.
    8. Why is NMOS technology preferred more than PMOS technology?
    9. Differentiate enhancement mode and depletion mode transistors.
    10. Describe the if-else statement.
    11. What are the various sources of power dissipation in CMOS circuits?
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SECTION-B

  1. What are the different types of VHDL modeling? Explain with examples.
  2. Write the VHDL code for a 3-bit Binary to Gray converter.
  3. What is an NMOS inverter? Discuss its transfer characteristics.
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  5. Explain pre-defined and user-defined attributes with the help of suitable examples.
  6. What is scaling? What is the effect of scaling on the circuit performance?

SECTION-C

  1. Design and implement a 16:1 Multiplexer using two 8:1 MUXes and a logic gate in Verilog HDL.
  2. Draw a CMOS inverter and discuss its DC characteristics. Write the conditions for the different regions of operation.
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  4. Write the VHDL code for a 4-bit synchronous up counter using sequential statements.

NOTE : Disclosure of Identity by writing Mobile No. or Making of passing request on any page of Answer Sheet will lead to UMC against the Student.



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