Download AKTU B-Tech 4th Sem 2016-17 NEC402 Electronic Circuits Question Paper

Download AKTU (Dr. A.P.J. Abdul Kalam Technical University (AKTU), formerly Uttar Pradesh Technical University (UPTU) B-Tech 4th Semester (Fourth Semester) 2016-17 NEC402 Electronic Circuits Question Paper

PrintedPages :2 Roll No.| l l l l I l l l l l NEC402
B. TECH.
THEORY EXAMINATION (SEM?IV) 2016-17
ELECTRONIC CIRCUITS
Time : 3 Hours Max. Marks : 100
Note : Be precise in your answer. In case Ofnumerical problem assume data wherever not provided.
SECTION ? A
1. Attempt all of the following questions: 10 x 2 = 20
(a) The input signal Vi to an op?amp is Vi = 0.03 sin 1.5x 105 t. What can be the maximum
gain of an op?amp with slew rate of 0.4 volts/ps.
(b) Draw the circuit diagram of an integrator and find its output.
(c) What do you mean by slew rate and CMRR of an op?amp.
((1) Draw Hybrid ?TE model and T?model equivalent of NPN transistor.
(e) Explain Bakhausen criterion.
(f) What are the conditions for operation in triode and saturation region of NMOS and
PMOS transistors?
(g) An amplifier has a mid?band gain of 125 and bandwidth of 250 KHZ. If 4% negative
feedback is introduced, find the new bandwidth and gain, also find the feedback ratio
when the bandwidth is restricted to lMHz.
(h) Draw the circuit of colpitts oscillator and also write its frequency and condition of
maintaining oscillations.
(i) What is the principle of crystal oscillator?
(i) What are the internal capacitances of BJT?
SECTION ? B
2. Attempt any five of the following questions: 5 x 10 = 50
(3) Explain inverting amplifier and also derive an expression for the closed loop gain under
the assumption that the open loop gain is finite.
(b) Do the analysis of series-series feedback amplifier to derive gain, input resistance and
output resistance.
(c) Draw the circuit of an RC phase shift oscillator using op?amp and derive frequency and
condition of oscillation for RC phase shift oscillator.
(d) (i) Explain Hartley oscillator.
(ii) Differentiate between DMOSFET and EMOSFET.
(e) Do the analysis bias dc biasing circuit of the NPN transistor to derive Q point and of
self stability factor.
(f) DO the small signal analysis of MOS differential pair to determine differential and
common mode gain.
(g) (i) An enhancement type NMOS transistor with Vt =0.7 V has its source terminal
grounded and a 1.5 V applied to the gate. In what region does the device operate
for a) VD=0.5 V b) VD=0.9 V c) VD: 3 V.
(ii) Explain the construction and working of N type enhancement MOSFET.
(h) (i) Draw input and output characteristics of common emitter amplifier.
(ii) State the properties of an ideal op-amp.

SECTION ? C
Attempt any two parts of the following questions: 2 x 15 = 30
3
Do the small signal analysis of common emitter amplifier with emitter resistance d0
derive input resistance, voltage gain (from base to collector), overall voltage gain
(source to load), open circuit voltage gain and output resistance.
Explain the effect of finite loop gain and bandwidth on circuit performance. Also define
input offset voltage and input Offset current.
(1) Explain all four feedback topologies with their block diagram.
(ii) Explain the operation of LC tank circuit.