VASAVI COLLEGE OF ENGINEERING (Autonomous), HYDERABAD

B.E. (ECE) VI Semester Main Examinations, May-June 2016

VLSI DESIGN

Max. Marks: 70

Time: 3 hours

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Note: Answer ALL questions in Part-A and any FIVE questions from Part-B

Part-A (10x2=20 Marks)

1. Define Fan-in and Fan-out.
2. What are the different operating regions of MOS transistor?
3. What is body effect? How does it affect the performance of MOSFET?
4. What are the advantages of dynamic logic circuits over static logic circuits?

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5. List the advantages and disadvantages of CMOS transmission gate.
6. Define scaling. What are the different types of scaling?
7. What are the sources of power dissipation in CMOS circuits?
8. Explain the concept of Logical Effort.
9. List different types of programmable ASICs.

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10. Write short notes on Built-In Self-Test (BIST).

Part-B (5x10=50 Marks)

1. a) Explain the fabrication process of NMOS transistor with neat diagrams. (5)
   b) Derive an expression for drain current in saturation region. (5)
2. a) Explain CMOS inverter transfer characteristics with neat diagrams. (5)
   b) Implement a full adder circuit using transmission gate. (5)

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3. a) Design a 4-input CMOS NAND gate. Calculate worst case rise time and fall time. (5)
   b) Explain Domino logic with suitable examples. (5)
4. a) Explain different short channel effects in MOSFET. (5)
   b) What is latch-up? Explain latch-up triggering mechanism. (5)
5. a) Explain the terms clock skew and clock jitter. How these problems can be addressed? (5)
   

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   b) Design a 4x4 array multiplier using carry save adder. (5)
6. a) Explain about different Antifuse technologies. (5)
   b) What is Boundary Scan? Explain the architecture of Boundary Scan. (5)
7. a) Explain the steps involved in ASIC design flow. (5)
   b) Write short notes on: (5)
   

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   i) Fault models
   ii) Scan path technique

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