FirstRanker's choice
Code: 17D06101
--- Content provided by FirstRanker.com ---
M.Tech I Semester Regular & Supplementary Examinations January/February 2019
STRUCTURAL DIGITAL SYSTEM DESIGN
(Common to DECS, ECE, DSCE, ES, VLSI&ES, ES&VLSI, VLSI&ESD, VLSI, VLSIS and VLSISD)
(For students admitted in 2017 & 2018 only)
Time: 3 hours
--- Content provided by FirstRanker.com ---
Max. Marks: 60
Answer all the questions
*****
- (a) Implement the following Boolean function using 8:1 multiplexer. F(A, B, C, D) = ?m(1, 2, 4, 6, 7, 11, 13, 15)
(b) What is the need of ALU and explain about it?--- Content provided by FirstRanker.com ---
OR - Construct a 5 to 32 line decoder with four 3 to 8 line decoders with enable and a 2 to 4 line decoder.
- (a) Explain top-down design methodology with example.
(b) Discuss about the separation of controller and architecture.
OR - What are the basic elements of ASM chart explain clearly with an example?
- Briefly explain about multiplexer controller method and one shot method.
OR - Briefly discuss about fault diagnosis and testing with flow diagram.
- Discuss about the 2910 micro program sequencer.
--- Content provided by FirstRanker.com ---
OR - Explain about design of micro minicomputer.
- Write short notes on simulators and schematic entry.
OR - Design a system for serial to parallel data conversion.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
*****
--- Content provided by FirstRanker.com ---
This download link is referred from the post: JNTUA M.Tech 1st Sem last 10 year 2010-2020 Previous Question Papers (JNTU Anantapur)