This download link is referred from the post: JNTUA M.Tech 1st Sem last 10 year 2010-2020 Previous Question Papers (JNTU Anantapur)
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Code: 17D06202
M.Tech I Semester Regular & Supplementary Examinations January/February 2019
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CPLD & FPGA ARCHITECTURES & APPLICATIONS
(Common to ES, VLSI&ES, ES&VLSI, VLSI&ESD, VLSI, VLSI and VLSISD)
(For students admitted in 2017 & 2018 only)
Time: 3 hours
Max. Marks: 60
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Answer all the questions
- (a) With neat block diagram, explain the architecture of Xilinx Cool Runner XCR3064XL CPLD.
(b) When is CPLD better suited than SPLD? List out the comparisons between those two.
OR - (a) Draw the basic block diagram of PLA device and explain each block. List out its applications.
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(b) Implement the following combinational circuit Boolean function:
F1(A,B,C)=Σ(0,1,2,4)
F2(A,B,C)=Σ(0,5,6,7) using PLA. - (a) How does the architecture of a typical FPGA device differ from that of a CPLD? In what way does the architecture affect the timing performance in the two cases?
(b) Describe the technology mapping for FPGA.--- Content provided by FirstRanker.com ---
OR - (a) Explain the concept of meta stability and when does meta stability cause design failures.
(b) Discuss following FPGA classification on user programmable switch technologies:
(i) SRAM. (ii) Anti-fuse. (iii) EEPROM.
And discuss the trade off. - Draw the logic diagram of Xilinx 4000 CLB and I/O blocks and explain their function.
OR - (a) Implemented simple and Fast-Ripple-Carry Counter Built with One Bit per CLB in the XC3000.
(b) Discuss the design Trade-Offs in SRAM-programmable FPGA Architecture. - (a) Compare the performance parameters of ACTEL based FPGAs ACT-1, 2 and 3.
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(b) Explain about different programmable elements in FPGA architectures.
OR - (a) How the ACT-3 architecture is different from ACT-2 architecture? Explain the ACT-3 architecture in detail.
(b) Explain the ACT-2 architecture for high fan-in example. - (a) Explain state machine design for a 4-channel DMA controller.
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(b) List criteria that influence performance of logic in FPGA designs.
OR - (a) Discuss chip level design considerations for ACT-1 and ACT-2 FPGA design.
(b) Explain high-performance loadable six-bit counter using pre-scaled counter design.
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This download link is referred from the post: JNTUA M.Tech 1st Sem last 10 year 2010-2020 Previous Question Papers (JNTU Anantapur)
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