Download JNTUA M.Tech 1st Sem 2019 Feb Regular and Supply 17D06202 CPLD And FPGA Architectures And Applications Question Paper

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Code: 17D06202

M.Tech I Semester Regular & Supplementary Examinations January/February 2019

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CPLD & FPGA ARCHITECTURES & APPLICATIONS

(Common to ES, VLSI&ES, ES&VLSI, VLSI&ESD, VLSI, VLSI and VLSISD)

(For students admitted in 2017 & 2018 only)

Time: 3 hours

Max. Marks: 60

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Answer all the questions

1. (a) With neat block diagram, explain the architecture of Xilinx Cool Runner XCR3064XL CPLD.
   (b) When is CPLD better suited than SPLD? List out the comparisons between those two.
   OR
2. (a) Draw the basic block diagram of PLA device and explain each block. List out its applications.
   

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   (b) Implement the following combinational circuit Boolean function:
   F1(A,B,C)=S(0,1,2,4)
   F2(A,B,C)=S(0,5,6,7) using PLA.
3. (a) How does the architecture of a typical FPGA device differ from that of a CPLD? In what way does the architecture affect the timing performance in the two cases?
   (b) Describe the technology mapping for FPGA.
   

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   OR
4. (a) Explain the concept of meta stability and when does meta stability cause design failures.
   (b) Discuss following FPGA classification on user programmable switch technologies:
   (i) SRAM. (ii) Anti-fuse. (iii) EEPROM.
   And discuss the trade off.

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5. Draw the logic diagram of Xilinx 4000 CLB and I/O blocks and explain their function.
   OR
6. (a) Implemented simple and Fast-Ripple-Carry Counter Built with One Bit per CLB in the XC3000.
   (b) Discuss the design Trade-Offs in SRAM-programmable FPGA Architecture.
7. (a) Compare the performance parameters of ACTEL based FPGAs ACT-1, 2 and 3.
   

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   (b) Explain about different programmable elements in FPGA architectures.
   OR
8. (a) How the ACT-3 architecture is different from ACT-2 architecture? Explain the ACT-3 architecture in detail.
   (b) Explain the ACT-2 architecture for high fan-in example.
9. (a) Explain state machine design for a 4-channel DMA controller.
   

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   (b) List criteria that influence performance of logic in FPGA designs.
   OR
10. (a) Discuss chip level design considerations for ACT-1 and ACT-2 FPGA design.
    (b) Explain high-performance loadable six-bit counter using pre-scaled counter design.

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