FirstRanker Logo

FirstRanker.com - FirstRanker's Choice is a hub of Question Papers & Study Materials for B-Tech, B.E, M-Tech, MCA, M.Sc, MBBS, BDS, MBA, B.Sc, Degree, B.Sc Nursing, B-Pharmacy, D-Pharmacy, MD, Medical, Dental, Engineering students. All services of FirstRanker.com are FREE

📱

Get the MBBS Question Bank Android App

Access previous years' papers, solved question papers, notes, and more on the go!

Install From Play Store

Download JNTUA M.Tech 1st Sem 2018 Aug-Sept 9D06101 Digital System Design Question Paper

Download JNTUA (JNTU Anantapur) M.Tech ( Master of Technology) 1st Semester 2018 Aug-Sept 9D06101 Digital System Design Previous Question Paper

This post was last modified on 30 July 2020

This download link is referred from the post: JNTUA M.Tech 1st Sem last 10 year 2010-2020 Previous Question Papers (JNTU Anantapur)


FirstRanker's choice

Code: 9D06101

FirstRanker.com

--- Content provided by FirstRanker.com ---

M.Tech I Semester Supplementary Examinations August/September 2018

DIGITAL SYSTEM DESIGN

(Common to DSCE, DECS, ECE, VLSIES, ESVLSI, VLSIESD & MNE)

(For students admitted in 2013, 2014, 2015 & 2016 only)

Time: 3 hours

--- Content provided by FirstRanker.com ---

Max. Marks: 60

Answer any FIVE questions

All questions carry equal marks


  1. Develop an ASM chart to design control logic of a binary divider and realize the same.
  2. (a) Design an iterative comparator circuit to compare two n bit numbers.

    --- Content provided by FirstRanker.com ---

    (b) How a sequential circuit can be designed using FPGA?
  3. Explain about the following types of faults:
    (a) Stuck at faults.
    (b) Bridge faults.
    (c) Temporary faults.
  4. --- Content provided by FirstRanker.com ---

  5. (a) Discuss in detail Boolean difference method in combinational circuits.
    (b) What is the significance of Kohavi algorithm? Explain how it detects multiple faults in two-level-networks with a simple example.
  6. Classify the fault detection experiments for the sequential circuits and explain.
  7. Design a 3-bit BCD to grey code converter and design the circuit using PLA and then show that how folding will reduce the number of cross points given on the PLA.
  8. Explain in detail testable PLA design with an example.
  9. --- Content provided by FirstRanker.com ---

  10. The output Z of a fundamental-mode, two input sequential circuit is to change from 0 to 1 only when X2 changes from 0 to 1 while X1 = 1. The output is to change from 1 to 0 only when X1 changes from 1 to 0 while X2 = 1. (i) Find a minimum-row reduced flow table, the output should be fast and flicker-free. (ii) Show a valid assignment and write a set of (static) hazard- free excitation and output equations.

FirstRanker.com



--- Content provided by FirstRanker.com ---

This download link is referred from the post: JNTUA M.Tech 1st Sem last 10 year 2010-2020 Previous Question Papers (JNTU Anantapur)