This download link is referred from the post: JNTUA M.Tech 1st Sem last 10 year 2010-2020 Previous Question Papers (JNTU Anantapur)
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Code: 9D06106c
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M.Tech I Semester Supplementary Examinations August/September 2018
LOW POWER VLSI DESIGN
(Common to DSCE and DECS)
(For students admitted in 2013, 2014, 2015 & 2016 only)
Max. Marks: 60 | Time: 3 hours |
Answer any FIVE questions
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All questions carry equal marks
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- (a) Compare low-power VLSI design techniques with conventional design methods.
(b) Explain about the design limitations imposed on low-power, low-voltage circuits pertaining to the following parameters: (i) Power supply voltage. (ii) Scaling.
(c) What are the advantages and limitations of silicon-on-insulator technology? - (a) Give the complete process flow for 0.2 µm in SOI Bi-CMOS process.
(b) Describe the process for integrated analog-digital CMOS I.C. - (a) Explain about narrow channel effects of SOI CMOS devices due to cross section and threshold voltage.
(b) What are the future trends in Bi CMOS process? Explain. - (a) Describe the advanced MOSFET models. What are the limitations of this model?
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(b) Describe the temperature dependent hybrid model device threshold model of MOSFET. - (a) Discuss the characterization and power consumption of Bi-CMOS gates.
(b) With the help of a schematic diagram, explain about the working of an FS-M Bi CMOS logic gate. - (a) In what way relay logic circuits differ from pass transistor logic circuits. Why the output of a pass transistor circuit is not used as a control signal for the next stage?
(b) Explain with an example how pipelining and parallelism can be combined to realize low power circuits.--- Content provided by FirstRanker.com ---
(c) Realize and implement NAND / AND logic and XOR / XNOR logic using CPL logic. - (a) What are the quality measures for latches and flip-flops? Explain.
(b) Give the design perspective for edge triggered D-flip-flop. - (a) Explain the clock skew problem of dynamic CMOS circuits.
(b) Floating body effects may also cause the parasitic bipolar leakage current in CMOS-SOI pass gate transistor- Explain?--- Content provided by FirstRanker.com ---
(c) Explain different pre-charge techniques employed by SRAM's.
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This download link is referred from the post: JNTUA M.Tech 1st Sem last 10 year 2010-2020 Previous Question Papers (JNTU Anantapur)