Download DU (University of Delhi) B-Tech 1st Semester 7797 Computer System Architecture Question Paper

Download DU (University of Delhi) B-Tech (Bachelor of Technology) 1st Semester 7797 Computer System Architecture Question Paper

This post was last modified on 31 January 2020

Tags: DU B-Tech Delhi University B-Tech Previous Year Papers Question Papers 2010-2020 Computer System Architecture 1st Semester 7797 PDF Download frdA310120A144911

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A Firstranker's choice

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This question paper contains 4+1 printed pages]

Roll No.

S. No. of Question Paper : 7797

Unique Paper Code : 2341102 F-1

Name of the Paper : Computer System Architecture (CSDC1-102)

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Name of the Course : B.Tech. (Computer Science) [DC-1.2]

Semester : 2l

Duration : 3 Hours Maximum Marks : 75

(Write your Roll No. on the top immediately on receipt of this question paper.)

Question No. 1 is compulsory.

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Attempt any four questions from question numbers 2 to 7.

Section A

(a) Convert (a x b) + (c % d) from infix to Reverse Polish Notation (RPN) showing different steps of stack.
(b) Design and explain the address sequencer for the microprogrammed control unit having control memory of 128 words. There are 4 status bits in the system. Length of microinstruction is 20 bits out of which 9 bits are used for microoperations. 5
(c) Formulate a mapping procedure that provides sixteen consecutive microinstructions of each routine of a typical computer. The operation code has five bits and the control memory has 4096 words. 6

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(d) The memory unit of computer has 256 K words of 32 bits each. The computer has an instruction format with four fields : an operation code field, a mode field to specify one of the addressing modes, a register address field to specify one of 60 processor registers, and a memory address. Specify the instruction format and the number of bits in each field if the instructions in one memory field. 5
(e) Explain the following : 4
1. Cycle stealing
2. Cache mapping
3. Microoperation
4. Processor register.
(f) Give the differences between isolated I/O and memory-mapped I/O. 3
(g) Draw a logic circuit for the following : 2
Y = XYZ + XYZ.
(h) Describe how AND gate can be implemented using NAND gates. 2

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Section B

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(a) Draw and explain the flow chart of interrupt cycle. Also explain how multiple VO interrupt is handled in the computer system. 5
(b) The control memory has 2048 words of 32 bits each. Each microinstruction has three fields. Three field’s microoperations are specified by 15 bits.
1. How many bits are there in the control address register ? 3
2. How many bits are there in the branch address field and the select field ? 2
(a) Explain (BSA), ISZ and SPA instructions with their respective microopreation. 6

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(b) A digital computer has a memory unit with a capacity of 16, 384 words of 40 bits each. The instruction code format consists of six bits for the operation part and 14 bits for the address part (no mode bit present). Two instructions are packed in one memory word and a 40 bit Instruction Register (IR) is available in the fetching and executing an instruction for this computer. 4
(a) Explain the organization of a microprogrammed control unit with the help of a block diagram. 5
(b) What are the purposes of different kind of addressing modes ? Consider a 16-bit processor in which the following appears in main memory, starting at location 200.:
```
200 Load to AC Mode
201 500
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202 Next Instruction 
```
The first part of the first word indicates that this instruction loads a value into an accumulator. The Mode field specifies an addressing. mode and, if appropriate, indicates a source register; assume that when used, the source register is R1, which has a value of 400. There is also a base register that contains the value 100. The value of 500 in location 201 may be part of the address calculation. Assume that the location 399 contains the value 999; location 400 contains the value 1000, and so on. Determine the effective address and the operand to be loaded for the following address modes :
1. PC relative
2. Register.
(a) Differentiate between an encoder and a decoder. Construct a 3 x 8 decoder with 2 x 4 decoders. 5

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(b) Give the truth table of full adders. Derive the Boolean function of a full adder using Karnaugh Map. Hence draw its circuit diagram. 5
(a) Differentiate among Main memory, Control memory and Cache memory. 3
(b) Give the differences between hardwired control and microprogrammed control processors architectures. 3
(c) Give I/O channel architecture with the help of diagram. 4
(d) Give block diagram of DMA controller. How does CPU initialize the DMA transfer ? 6

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(e) A two-way set associative Cache memory uses blocks of four words. The Cache can accommodate a total of 2048 words from main memory. The main memory size is 128 K*32. What are the sizes of the : 4
1. TAG
2. INDEX ?

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This post was last modified on 31 January 2020