Download DU (University of Delhi) B-Tech 1st Semester 7797 Computer System Architecture Question Paper

Download DU (University of Delhi) B-Tech (Bachelor of Technology) 1st Semester 7797 Computer System Architecture Question Paper

This question paper contains 4+1 printed pages]
Roll No.
S. No. of Question Paper : 7797
Unique Paper Code : 2341102 , ? 17.1 1
Name of the Paper : Computer System Architecture (CSDCl-102)
Name of the Course : B.Tech. (Computer Science) [DC-l.2]
Semester : l
Duration :3 Hours ? - Maximum Marks : 75
(Write your Roll No. on (he top immediately on receipt of this question paper.)
Question No. l is compulsory.
Attempt any fbur questions from question numbers 2 to 7.
Section A
l. (a) Convert (a x b) + (c X J) from in?x to Reverse Polish Notation (RPN) showing different
steps of stack. h 4
(1)) Design and explain the address sequencer for the microprogrammed control unit having
(C)
control memory of 128 words. Them ane?4 status bits in the system Length of microinsumtion
is 20 bits out of which 9 bits are used for micmopcmtions. ? 5
F onnulale a mapping pmwdure that provides sixteen conmcutive miminstmctions of each
routine of a typical computer. The operation code has ?ve hits and the control memory-
has 4096 words. I I 6
P.T.O.

( 2 ) ? 7797~
(d) The memory unit of computer has 256 K words ofr32 bits each. The computer has
an instruction format {with four ?elds : an operation code ?eld, a mode ?eld to specify
one of the addressing modes, a register address ?eld to specify one of 60 processor
registers, and a memory address. Specify the instruction format and the number of bits
~ in each ?eld if the instructions in one memory ?eld. 5
(e) Explain the following: 4
(i) Cycle stealing
(ii) Cachemapping
(iii) Microoperation
giv) Processor register. .
(f) Give the differences between isolated I/O and memory-mapped I/O. 3
(g) Draw a logic cihcuit for the following : ' 2
Y = m + XYZ.
(h) Describe how AND gate can be implemented using NAND gates. 2
(i) Explain in detail about associative mapping with the help of example. 4

3.
( 3 ) 7797
Section B
((1) Draw and explain the ?ow Chan of interrupt cycle. Also explain how multiple I/O interrupt
(b)
(a)
(b)
(u)
is handled in the computer system. 5
The control memory has 2048 words of 32 bits each. Each microinstruction has three
?elds. Three ?eld?s microoperations are speci?ed by 15 bits.
(I) How many bits are there in the control address register ? 3
(ii) How many hits are there in the branch address ?eld and the select ?eld ? - 2
Explain (BSA), 182 and SPA instructions with their respective microopreation. 6
A digital computer has a memory unit with a capacity of 16, 384 words of 40 bits
each. The instruction code fomat consists of six bits for the operation pan and 14 bits
for the address part (no mode bit present). Two instructions are packed in one memory
word and a 40 bit Instruction Register (IR) is available in the fetching and executing
an instruction for this computer. 4
Explain the organization of a microprogrammed control unit with the help of a block
diagram. . 5
P.T.O.

( 4 ) 7797
What are the purpogcs of different kind of addressing modes ? Consider a 16-bit
processor in which the following appeais in maixi memory. starting at location 200,:
200 Load to AC Mode
201 500
? 202' Next Instruction
The ?rst part of the ?rst word indicates that this instruction loads a value into an
accumulator. The Mode ?eld speci?es an addressing. mode and, if appropriate,
indicates a source register; assume that when used, the source register is R1, which
has a value of 400. There is also a base register that contains the value 100.
The value of 500 in location 201 may be part of the address calculation. Assume
that the location 399 contains the value 999; location 400 contains the value 1000,
and so on. Determine the effective address and the operand to be loaded for the
following address modes : i
(1') Dim
(ii) Immediate
(m) Indirect
(iv) PC relative
(V) Regim-

L. (U)
(b)
5. (u)
' (b)
'. (u)
v (1))
t 5 ) ? 7797
Differentiate between an encoder and a decoder. Construct a 3 X 8 decoder
with 2 X 4 decoders. 5
Give the truth table of full adders. Derive the Boolean function of a full adder using
Kamaugh Map. Hence draw its circuit diagram. 5
Differentiate among Main memory, Control memory and Cache memory. 3
Give the differences between hardwired control and microprogrammed control processors
architectures. 3
Give l/O channel architecture with the help of diagram. - 4
Give block diagram of DMA controller. HOW does CPU initialize the DMA
6
transfer ?
A two-way set associative Cache memory uses blocks of four words. The Cache
can accommodate a total of 2048 words from main memory. The main memory size
is 128 K*32. What are the sizes of the : - ~ 4
(i) TAG
(ii) INDEX ?
5 - 2,000~
mt
ach
pry
\ a
to.