Download JNTUA M.Tech 2nd Sem Supply 2018 Feb 9D06106c Low Power VLSI Design Question Paper

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Code: 9D06106c

Time: 3 hours

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M.Tech II Semester Supplementary Examinations February 2018

LOW POWER VLSI DESIGN

(Electronics & Communication Engineering)

(For students admitted in 2012, 2013, 2014, 2015 & 2016 only)

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Max. Marks: 60

Answer any FIVE questions

All questions carry equal marks

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1. (a) What do you mean by low power design? Explain why it is so important.
   

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   (b) Justify the statement ‘SOI is one of the leading technology'.
2. Describe the following MOS transistor isolation techniques:
   (a) LOCOS.
   (b) Shallow trench isolation
   (c) Deep trench isolation.

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3. With the help of cross-sectional diagram, illustrate the features of modern CMOS technology.
4. Explain in detail the EKV MOSFET and advanced MOSFET model.
5. Implement a 3-input NAND gate using the following logics:
   (a) CC-BICMOS.
   (b) FS-BICMOS.
   

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   (c) FS-CMBL.
6. (a) Perform comparative analysis of all e BiCMOS circuit in terms of power, delay and voltage swing.
   (b) Draw and explain a charge-pump integrated HB-BICMOS circuit.
7. Implement the clocked SR flip flop in the following styles:
   (a) A fully static.
   

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   (b) A RAM style.
   (c) A CVSL style.
8. Describe the following with respect to power reduction in clock networks:
   (a) Clock gating.
   (b) Reduced swing clock.
   

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   (c) Oscillator circuit for clock generation.

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