This download link is referred from the post: JNTUA M.Tech 2nd Sem last 10 year 2010-2020 Previous Question Papers (JNTU Anantapur)
Code: D06206cM
I M.Tech I Semester Supplementary Examinations February 2018
FPGA ARCHITECTURE & APPLICATIONS (Digital Systems and Computer Electronics)
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(For students admitted in 2012, 2013, 2014, 2015 & 2016 only)
Time: 3 hours Max. Marks: 60
Answer any FIVE questions
All questions carry equal marks
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(a) Implement the following Boolean function using PAL:
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(b) Distinguish between FPGA and CPLD.
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(a) Explain a Govt. state assignments for FPGA.
(b) Realize switching functions (2, 3, 4, 6, 7) using 2 input LUTs. Give the truth table implementation in each LUT & show wires in FPGA.
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(a) Write about FPGA and compare speed performance of ACT1, ACT2, ACT3 FPGA.
(b) What is LE? Draw and explain the working of LE of altera FLEX 8000.
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(a) What is state transition table?
(b) Explain how state transaction assignment can be carried at for FPGA.
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(a) Explain the procedure for design of a state machine using one-hot encoding.
(b) Explain the symbolic representation of FSM architectures.
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Write notes on:
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(a) Architecture centred around non registered PLDs.
(b) State machine design centered around shift registers.
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(a) Design a parallel adder sequential circuit.
(b) Explain multiplexers.
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Write notes on:
(a) Counters and parallel controllers.
(b) Combinational logic circuits.
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This download link is referred from the post: JNTUA M.Tech 2nd Sem last 10 year 2010-2020 Previous Question Papers (JNTU Anantapur)
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