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Download JNTUA M.Tech 2nd Sem 2016 February 9D06101 Digital System Design Question Paper

Download JNTUA (JNTU Anantapur) M.Tech ( Master of Technology) 2nd Semester 2016 February 9D06101 Digital System Design Previous Question Paper || Download M.Tech 2nd Sem 9D06101 Digital System Design Question Paper || JNTU Anantapur M.Tech Previous Question Paper

This post was last modified on 31 July 2020

This download link is referred from the post: JNTUA M.Tech 2nd Sem last 10 year 2010-2020 Previous Question Papers (JNTU Anantapur)


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Code: 9D06101

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M.Tech I Semester Regular & Supplementary Examinations February 2016

DIGITAL SYSTEM DESIGN

(Common to DSCE, DECS, ECE, VLSIES, ESVLSI, VLSIESD & MNE)

(For students admitted in 2011, 2012, 2013, 2014 & 2015 only)

Time: 3 hours

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Max Marks: 60

Answer any FIVE questions

All questions carry equal marks

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  1. (a) Discuss the primary constructs that are used in VHDL.

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    (b) Design a 4 X 3 ROM to perform:
    F1 = ∑(0, 1, 2, 3, 7)
    F2 = ∑(1, 2, 3, 5, 7)
    F3 = ∑(0, 2, 4, 6)
  2. (a) Draw the symbols used in ASM chart and explain.

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    (b) Describe important features of FPGA.
  3. Construct the test set of output function of the circuit F(X1, X2, X3) = X1X3 + (X2 + X3). Using path sensitizing method.
  4. (a) With a neat circuit diagram, describe the working of a signature analyzer.
    (b) Write short notes on testing for bridging faults.
  5. (a) Explain about fault detection and location in sequential circuits.

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    (b) Discuss about synchronizing experiments of fault diagnosis in sequential circuits.
  6. (a) Explain the various types of cross point fault that occur in PLA's.
    (b) Explain PLA folding.
  7. (a) Explain how test generation can be achieved in testing a PLA.
    (b) Discuss briefly about testable PLA design.
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  9. Explain the fundamental mode model for asynchronous sequential machine design.

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This download link is referred from the post: JNTUA M.Tech 2nd Sem last 10 year 2010-2020 Previous Question Papers (JNTU Anantapur)