This download link is referred from the post: JNTUA M.Tech 2nd Sem last 10 year 2010-2020 Previous Question Papers (JNTU Anantapur)
Firstranker's choice
Code: 9D06206c
--- Content provided by FirstRanker.com ---
Time: 3 hours
M.Tech II Semester Supplementary Examinations January/February 2017
FPGA ARCHITECTURE & APPLICATIONS
(Digital Systems & Computer Electronics)
Answer any FIVE questions
--- Content provided by FirstRanker.com ---
All questions carry equal marks
- (a) Explain about FLEX logic with the aid of suitable sketch.
(b) Explain in detail about mask programmable ROM. - (a) Write notes on technology mapping for FPGAs with suitable example.
(b) Explain routing architecture of FPGA. - (a) Explain the design considerations of Xilinx XC4000 series FPGAs with relevant example.
(b) Draw and explain the operation of Xilinx based XC 4000 CLB. - (a) With suitable example, explain the top down design approach for FPGAs using finite state machines.
(b) Elaborate the derivations of state machine charts relevant to FSM with suitable example. - (a) Discuss about meta stability and synchronization of finite state machines.
--- Content provided by FirstRanker.com ---
(b) Write an example and explain about one-hot design using ASM. - Draw and explain the model used for architecture centered around nonregistered programmable logic devices.
- (a) Explain the concepts of controller, path and functional partition with respect to system level design.
(b) Give the design flow of FPGA as a case study of counter. - Give the design flow of FPGA as a case study of parallel adder and parallel controller.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Max. Marks: 60
--- Content provided by FirstRanker.com ---
This download link is referred from the post: JNTUA M.Tech 2nd Sem last 10 year 2010-2020 Previous Question Papers (JNTU Anantapur)