This download link is referred from the post: JNTUA M.Tech 2nd Sem last 10 year 2010-2020 Previous Question Papers (JNTU Anantapur)
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Code: 17D06109
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M.Tech II Semester Supplementary Examinations January/February 2019
TEST & TESTABILITY
(Common to VLSI, VLSIS & VLSISD)
(For students admitted in 2017 only)
Time: 3 hours
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Max. Marks: 60
Answer all the questions
- (a) Classify types of testing and explain in brief about them.
(b) Explain in brief about bridging faults.OR
- (a) Explain about the types of testing of VLSI chips.
(b) Explain in detail about temporary faults. - (a) Illustrate serial fault simulation for large number of faults.
(b) Illustrate detective fault simulation using combinational circuit.OR
- (a) Explain about event driven simulation using combinational circuit.
(b) Illustrate two valued deductive simulation with example. - (a) Explain concept of controllability and observability with the help of block diagram.
(b) Compute the combinational SCOAP testability measures for the circuit that realizes an expression J = ((A+B)⊕E)+BC+D. - (a) Illustrate partial-scan design with s-graph.
OR
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(b) Explain about the properties of Ad-Hoc DFT methods and its difficulties too. - (a) Illustrate economic case for BIST.
(b) Explain about the process of random pattern generation.OR
- (a) Illustrate circular self-test path BIST architecture with example.
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(b) Illustrate LFSR as signature analyzer. - (a) Explain boundary scan architecture with neat schematic.
(b) Explain BYPASS and INTEST instructions in boundary scan description language.OR
- (a) Explain about BDSL description components.
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(b) Explain about ring configuration of TAP controller.
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This download link is referred from the post: JNTUA M.Tech 2nd Sem last 10 year 2010-2020 Previous Question Papers (JNTU Anantapur)