This download link is referred from the post: JNTUA M.Tech 2nd Sem last 10 year 2010-2020 Previous Question Papers (JNTU Anantapur)
Code: 17D06202 FirstRanker.com
M.Tech II Semester Supplementary Examinations January/February 2019
CPLD & FPGA ARCHITECTURES & APPLICATIONS
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(Digital Systems & Computer Electronics)
(For students admitted in 2017 only)
Time: 3 hours Max. Marks: 60
Answer all the questions
- (a) Explain the various architectures of Xilinx Cool Runner CPLDs.
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(b) Distinguish between programmable logic devices.
OR - (a) Write short notes on CPLD implementation of a parallel adder with accumulation.
(b) Realize 3 X 8 decoder with single enable input using PAL & PLA. - (a) With neat diagrams, explain logic block architectures of FPGAs.
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(b) Write a short note on applications of FPGAs.
OR - (a) Explain the concept of programmable I/O blocks in FPGAs.
(b) Explain different programming technologies in FPGAs. - (a) Write about SRAM programming technology of programmable FPGAs with neat sketches.
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(b) List out the salient features of Xilinx based XC 3000 CLB.
OR - Draw the schematic diagram of Xilinx based XC 4000 CLB and describe its functional operation.
- (a) Discuss the architectural differences of ACT1 and ACT2 family FPGAs.
(b) Explain how anti-fuse programming technology is used in Actel FPGAs.--- Content provided by FirstRanker.com ---
OR - (a) How would you implement a binary counter using the CLBs of FPGA?
(b) Describe the applications of Actel FPGAs. - (a) Explain about position tracker of a Robot manipulator with help of FPGAs.
(b) Realize full adder using Actel FPGAs.--- Content provided by FirstRanker.com ---
OR - Explain about a fast video controller.
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This download link is referred from the post: JNTUA M.Tech 2nd Sem last 10 year 2010-2020 Previous Question Papers (JNTU Anantapur)