This download link is referred from the post: JNTUA M.Tech 2nd Sem last 10 year 2010-2020 Previous Question Papers (JNTU Anantapur)
Code: 17D06207
M.Tech II Semester Supplementary Examinations January/February 2019
SYSTEM ON CHIP DESIGN
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(Digital Systems and Computer Electronics)
(For students admitted in 2017 only)
Answer all the questions
Max. Marks: 60
Time: 3 hours
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- Mention the instruction execution sequence of processor.
- List out the SOC memory considerations.
OR
- Comprehend the pipelined processor model.
- Draw and explain the block diagram of processors in SOC model.
OR
- List out the instruction set mnemonic operations.
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- Write about the WRITE policies of memory design.
- Write about basic DRAM types.
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OR
- Write about simple DRAM and their memory array.
- Draw the simplified block diagram of an SOC module and explain.
OR
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- Compare the bus interconnect architectures.
- Write about commercial logic block of Xilinx CLB.
- Draw and explain the block diagram of JPEG compression.
- Write about performance and Area trade-off on Xilinx vertex XCV-1000.
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This download link is referred from the post: JNTUA M.Tech 2nd Sem last 10 year 2010-2020 Previous Question Papers (JNTU Anantapur)
--- Content provided by FirstRanker.com ---