Download JNTUA M.Tech 2nd Sem 2019 Feb 17D06207 System on Chip Design Question Paper

Code: 17D06207

M.Tech II Semester Supplementary Examinations January/February 2019

SYSTEM ON CHIP DESIGN

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(Digital Systems and Computer Electronics)

(For students admitted in 2017 only)

Answer all the questions

Max. Marks: 60

Time: 3 hours

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1. 1. Mention the instruction execution sequence of processor.
   2. List out the SOC memory considerations.

   OR

2. Comprehend the pipelined processor model.

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3. Draw and explain the block diagram of processors in SOC model.

   OR

4. List out the instruction set mnemonic operations.
5. 1. Write about the WRITE policies of memory design.
   2. Write about basic DRAM types.

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   OR

6. Write about simple DRAM and their memory array.
7. Draw the simplified block diagram of an SOC module and explain.

   OR

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8. 1. Compare the bus interconnect architectures.
   2. Write about commercial logic block of Xilinx CLB.
9. Draw and explain the block diagram of JPEG compression.
10. Write about performance and Area trade-off on Xilinx vertex XCV-1000.

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