This download link is referred from the post: JNTUA M.Tech 2nd Sem last 10 year 2010-2020 Previous Question Papers (JNTU Anantapur)
Code: 17
D06210
M.Tech
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II Semester Supplementary Examinations January/February 2019
LOW POWER VLSI DESIGN
(Digital Systems & Computer Electronics)
(For students admitted in 2017 only)
Time: 3 hours Max. Marks: 60
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Answer all the questions
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Explain the need for low power VLSI design.
OR
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What are the sources of power dissipation in digital IC’s? Explain.
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Discuss about pipelining and parallel processing approaches.
OR
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What is the difference between MTCMOS and VTCMOS? How it will effect in the reduction of power in designing multiplexer and flip-flops?
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Describe about CMOS adder’s architecture.
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Explain about low voltage low-power design techniques.
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Draw the basic building blocks of the Baugh-Wooley multiplier architecture and explain its operation.
OR
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Explain about Booth multiplier.
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Discuss sources of power dissipation in SRAM and DRAM.
OR
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With neat diagrams, explain about SRAM technologies and DRAM architecture.
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*****
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This download link is referred from the post: JNTUA M.Tech 2nd Sem last 10 year 2010-2020 Previous Question Papers (JNTU Anantapur)