Download JNTUA M.Tech 2nd Sem Reg-Supply 2018 Aug-Sept 9D06106c Low Power VLSI Design Question Paper

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Code: 9D06106c

M.Tech II Semester Supplementary Examinations August/September 2018

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LOW POWER VLSI DESIGN

(Electronics & Communication Engineering)

(For students admitted in 2013, 2014, 2015 & 2016 only)

Time: 3 hours Max. Marks: 60

Answer any FIVE questions

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All questions carry equal marks

1. Explain the limitations of low-voltage, low-power design w.r.t the following:
   1. Power supply voltage.
   2. Threshold voltage.
   3. Scaling.
   4. Interconnect wires.

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2. 1. What are the considerations to be taken care while integrating BICMOS process? Explain.
   2. Discuss briefly the p-well CMOS process and Twin-well Bi-CMOS process.
3. Illustrate a 0.2 um SOI BiCMOS process flow and then explain each step of it.

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4. Explain in detail the current model of advanced MOSFET model.
5. Discuss the following basic driver configurations of BICMOS logic circuit:
   1. The common-emitter.
   2. The gated diode.
   3. The emitter follower.

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6. 1. Design ESD-free BICMOS inverter and then explain the same.
   2. Compare performance of ESD-free. BICMOS digital circuit with an optimized two-stage CMOS and the TS-FS-BiCMOS circuits.
7. 1. Explain the pipelining theme by taking a negative edge-triggered CMOS flip-flop.
   2. Develop a dynamic negative-edge triggered flip-flop based on pass transistor logic and then explain the same.

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8. Describe the following low power techniques for SRAM:
   1. Memory bank partitioning.
   2. Pulsed word line and reduce bitline swing.

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