This download link is referred from the post: JNTUA M.Tech 2nd Sem last 10 year 2010-2020 Previous Question Papers (JNTU Anantapur)
FirstRanker.com
Firstranker's choice
Code: 9D06203
--- Content provided by FirstRanker.com ---
FirstRanker.com M.Tech II Semester Supplementary Examinations August/September 2018
DESIGN OF FAULT TOLERANT SYSTEMS
(Digital Systems & Computer Electronics)
(For students admitted in 2013, 2014, 2015 & 2016 only)
--- Content provided by FirstRanker.com ---
Time: 3 hours Max. Marks: 60- (a) Write a short note on following:
Reliability.
(b) Meantime.
(c) Maintainability.--- Content provided by FirstRanker.com ---
(d) Availability. - (a) Discuss about triple modular redundancy with necessary diagrams.
(b) Explain time redundancy and sift out redundancy. - (a) What is self-checking circuits? Explain the principle of operation of a self-checking circuit with a suitable diagram.
(b) Design a totally self-checking checker using low cost residue code. - (a) Explain fail safe design of sequential circuits using Berger code.
(b) Explain the fail-safe design of synchronous sequential circuits using partition theory. - (a) Design the circuit for the Reed-Muller expansion implementation.
(b) Explain use of control and syndrome testable design for combinational circuits. - Discuss about theory and operation of linear feedback shift register with a suitable diagram.
- (a) Explain controllability and observability with scan register with a suitable diagram.
(b) Explain classic scan design. - Discuss test pattern generation for BIST with examples.
- Explain constant weight patterns.
--- Content provided by FirstRanker.com ---
--- Content provided by FirstRanker.com ---
Answer any FIVE questions
--- Content provided by FirstRanker.com ---
All questions carry equal marks--- Content provided by FirstRanker.com ---
This download link is referred from the post: JNTUA M.Tech 2nd Sem last 10 year 2010-2020 Previous Question Papers (JNTU Anantapur)