Download VTU BE 2020 Jan CSE Question Paper 15 Scheme 7th Sem 15CS72 Advanced Computer Architecture

--- Content provided by​ FirstRanker.com ---

? ? ? ;
I
?
\ C
a

--- Content provided by​ FirstRanker.com ---

: D I ; -c:' ; 15CS72
Seventh Semester B.E. Degree Examination, DecilitIaaii.2020
Advanced Computer Architecture
Time: 3 hrs. Max. Marks: 80
USN

--- Content provided by FirstRanker.com ---

U
0.;
I)
1)

--- Content provided by⁠ FirstRanker.com ---

F. E.:
.
? c:
7

--- Content provided by⁠ FirstRanker.com ---

.5
3
4
c.
y

--- Content provided by‍ FirstRanker.com ---

I
)

7J y
?r

--- Content provided by‍ FirstRanker.com ---

.

o
,(.
5

--- Content provided by‌ FirstRanker.com ---

'
CA z
O CO .) CO
CCS C
1

--- Content provided by​ FirstRanker.com ---

5
C
c75
? L
,

--- Content provided by​ FirstRanker.com ---

c::
o
E
? U
2

--- Content provided by⁠ FirstRanker.com ---

c
. c 5
?
4,
-

--- Content provided by​ FirstRanker.com ---

a. c.4
E
o 2
>,
8

--- Content provided by‌ FirstRanker.com ---

rsi
0
z
C

--- Content provided by⁠ FirstRanker.com ---

t
V
0
C-
Note: Answer any FIVE full questions, choosing ONE full question from each module.

--- Content provided by​ FirstRanker.com ---

Module-1
a. With a neat diagram explain the elements of modern computer system. (08 Marks)
b. Explain Flynn's classification of computer architecture. (08 Marks)
OR
2 a. Define data dependency. Explain different functions of data dependency with the help of

--- Content provided by⁠ FirstRanker.com ---

dependency graph. (08 Marks)
b. A 4 MHz processor was used to execute a benchmark program with the following
instruction mix and clock cycle counts.
Instruction type Instruction count Cycles/instruction
Integer arithmetic 45000 1

--- Content provided by​ FirstRanker.com ---

Data transfer 32000 2
Floating point 15000 2
Control transfer 8000 2
Determine the effective CPI, MIPS rate and execution time for this program. (08 Marks)
Module-2

--- Content provided by‌ FirstRanker.com ---

3 a. Explain the architecture of VLIW processor and its pipeline operations. (08 Marks)
b. Explain the inclusion property and locality of reference along with its types in multilevel
memory hierarchy. (08 Marks)
OR
4 a. Explain page replacement policies with the help of an example. (08 Marks)

--- Content provided by‌ FirstRanker.com ---

b. Give the characteristics of symbolic processors. (08 Marks)
Module-3
5 a. Explain bus arbitration and its types in multiprocessor systems. (08 Marks)
b. Explain any two mapping techniques. (08 Marks)
OR

--- Content provided by FirstRanker.com ---

6 a. Explain the following terms associated with cache and memory architecture:
(i) Low order memory interleaving
(ii) Atomic v/s non-atomic memory
(iii) Physical address cache vs virtual address cache
(iv) Memory bandwidth and fault tolerance. (08 Marks)

--- Content provided by‍ FirstRanker.com ---

1 of 2
FirstRanker.com - FirstRanker's Choice
? 4 NIMP
13
.$,

--- Content provided by​ FirstRanker.com ---

I
1E7?
? ? ? ;
I
?

--- Content provided by FirstRanker.com ---

\ C
a
: D I ; -c:' ; 15CS72
Seventh Semester B.E. Degree Examination, DecilitIaaii.2020
Advanced Computer Architecture

--- Content provided by‌ FirstRanker.com ---

Time: 3 hrs. Max. Marks: 80
USN
U
0.;
I)

--- Content provided by FirstRanker.com ---

1)

F. E.:
.
? c:

--- Content provided by⁠ FirstRanker.com ---

7

.5
3
4

--- Content provided by‌ FirstRanker.com ---

c.
y
I
)

--- Content provided by‍ FirstRanker.com ---

7J y
?r
.

o

--- Content provided by​ FirstRanker.com ---

,(.
5
'
CA z
O CO .) CO

--- Content provided by FirstRanker.com ---

CCS C
1
5
C
c75

--- Content provided by​ FirstRanker.com ---

? L
,
c::
o
E

--- Content provided by⁠ FirstRanker.com ---

? U
2
c
. c 5
?

--- Content provided by FirstRanker.com ---

4,
-
a. c.4
E
o 2

--- Content provided by​ FirstRanker.com ---

>,
8

rsi
0

--- Content provided by​ FirstRanker.com ---

z
C
t
V
0

--- Content provided by​ FirstRanker.com ---

C-
Note: Answer any FIVE full questions, choosing ONE full question from each module.
Module-1
a. With a neat diagram explain the elements of modern computer system. (08 Marks)
b. Explain Flynn's classification of computer architecture. (08 Marks)

--- Content provided by‌ FirstRanker.com ---

OR
2 a. Define data dependency. Explain different functions of data dependency with the help of
dependency graph. (08 Marks)
b. A 4 MHz processor was used to execute a benchmark program with the following
instruction mix and clock cycle counts.

--- Content provided by​ FirstRanker.com ---

Instruction type Instruction count Cycles/instruction
Integer arithmetic 45000 1
Data transfer 32000 2
Floating point 15000 2
Control transfer 8000 2

--- Content provided by​ FirstRanker.com ---

Determine the effective CPI, MIPS rate and execution time for this program. (08 Marks)
Module-2
3 a. Explain the architecture of VLIW processor and its pipeline operations. (08 Marks)
b. Explain the inclusion property and locality of reference along with its types in multilevel
memory hierarchy. (08 Marks)

--- Content provided by​ FirstRanker.com ---

OR
4 a. Explain page replacement policies with the help of an example. (08 Marks)
b. Give the characteristics of symbolic processors. (08 Marks)
Module-3
5 a. Explain bus arbitration and its types in multiprocessor systems. (08 Marks)

--- Content provided by‍ FirstRanker.com ---

b. Explain any two mapping techniques. (08 Marks)
OR
6 a. Explain the following terms associated with cache and memory architecture:
(i) Low order memory interleaving
(ii) Atomic v/s non-atomic memory

--- Content provided by‌ FirstRanker.com ---

(iii) Physical address cache vs virtual address cache
(iv) Memory bandwidth and fault tolerance. (08 Marks)
1 of 2
b. Consider the following pipelined processor within 3 stages this pipeline has total evaluation
time of 8 clock cycles. All successor st ges must be used after each clock cycle.

--- Content provided by​ FirstRanker.com ---

0 1 2 3 4 5 6 7 8
S
I
X
S2 X X X

--- Content provided by FirstRanker.com ---

S3 X
S4
X X
SS X X
(i) List the set of forbidden latencies between task initiations

--- Content provided by​ FirstRanker.com ---

(ii) Draw the state diagram which shows all possible latency cycles
(iii) List all greedy cycles
(iv) Value of MAL.
Module-4
7 a. Explain hierarchical bus system with neat diagram.

--- Content provided by⁠ FirstRanker.com ---

b. Explain crossbar networks along with its advantages and limitations.
OR
8 a. Explain snoopy protocols with its approaches.
b Briefly explain message routing schemes.
Module-5

--- Content provided by​ FirstRanker.com ---

9 a. Define parallel programming model. Explain any two models.
b. Mention branch prediction methods and explain.
OR
10 a.
With the help of a neat diagram explain compilation phases in code generator.

--- Content provided by‌ FirstRanker.com ---

b. Explain different language features for parallelism.
(08 Marks)
(08 Marks)
(08 Marks)
(08 Marks)

--- Content provided by‍ FirstRanker.com ---

(08 Marks)
(08 Marks)
(08 Marks)
(08 Marks)
(08 Marks)

--- Content provided by‌ FirstRanker.com ---

2 of 2
FirstRanker.com - FirstRanker's Choice