PTU B.Tech CSE 3rd Semester May 2019 56591 COMPUTER ARCHITECTURE Question Papers

Roll No.

Total No. of Questions : 18

Total No. of Pages : 02

--- Content provided by‌ FirstRanker.com ---

B.Tech.(CSE)/(IT) (2011 Onwards)
B.Tech.(3D Animation & Graphics) (2012 Onwards)
(Sem.-3)
COMPUTER ARCHITECTURE
Subject Code : BTCS-301

--- Content provided by​ FirstRanker.com ---

Time: 3 Hrs. Max. Marks : 60

INSTRUCTION TO CANDIDATES :

1. SECTION-A is COMPULSORY consisting of TEN questions carrying TWO marks each.
2. SECTION-B contains FIVE questions carrying FIVE marks each and students have to attempt any FOUR questions.

--- Content provided by FirstRanker.com ---

3. SECTION-C contains THREE questions carrying TEN marks each and students have to attempt any TWO questions.

SECTION-A

1. Differentiate between Computer Architecture and Organization.
2. What do you understand by Fetch Cycle?
3. Differentiate between Arithmetic Shift Left and Arithmetic Shift Right.

--- Content provided by FirstRanker.com ---

4. What is a microprogram sequencer?
5. What is instruction-level parallelism?
6. Why does increasing the capacity of cache tend to increase its hit rate?
7. What do you mean by memory hierarchy?
8. Draw a neat diagram for handshaking mode of data transfer.

--- Content provided by FirstRanker.com ---

9. How many 128×8 ROM memory chips are needed to provide a memory capacity of 4096×16?
10. What do you mean by Inter-processor Communication?

SECTION -B

11. Give the comparison between hardwired control unit and micro programmed control unit.
12. Compare RISC and CISC architecture.

--- Content provided by‍ FirstRanker.com ---

13. Explain all the phases of instruction cycle.
14. What are the various types of interrupts? Explain.
15. Formulate a six-segment instruction pipeline for a computer. Specify the operations to be performed in each pipeline.

SECTION -C

16. Explain with an example, how effective address is calculated in different types of addressing modes?

--- Content provided by‌ FirstRanker.com ---

17. Explain in detail the different mappings used for cache memory. Compare them.
18. With neat block diagram, explain how DMA controller is initialized for DMA data transfer?

NOTE : Disclosure of Identity by writing Mobile No. or Making of passing request on any page of Answer Sheet will lead to UMC against the Student.

For more visit: FirstRanker.com

--- Content provided by‍ FirstRanker.com ---