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Download PTU M.Tech. ECE 2nd Semester 74282 VLSI DESIGN Question Paper

Download PTU. I.K. Gujral Punjab Technical University (IKGPTU) M.Tech. ECE 2nd Semester 74282 VLSI DESIGN Question Paper.

This post was last modified on 13 December 2019

PTU M.Tech 2nd Semester Last 10 Years 2010-2020 Previous Question Papers|| Punjab Technical University


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Roll No.

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Total No. of Questions : 08

M.Tech.(ECE) (2016 Batch) EL-I

VLSI DESIGN

Subject Code : MTEC-204B

M.Code: 74282

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(Sem.-2)

Time: 3 Hrs.

Max. Marks : 100

Total No. of Pages : 02

INSTRUCTIONS TO CANDIDATES :

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  1. Attempt any FIVE questions out of EIGHT questions.
  2. Each question carries TWENTY marks.
  1. (a) Design a Mod-6 counter using SR flip-flop and also convert it into counter using JK flip-flop. (14)
  2. (b) What are the various types of ROM's? Discuss their relative advantages and disadvantages. (6)
  1. (a) Explain memory structure of SRAM with read and write circuitry with the help of read and write timing diagrams. (10)
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  3. (b) Give a brief note on the looping statements available in Verilog HDL. (10)

3. A sequential network has one input(X) and two outputs (Z1 and Z2). An output Z1 =1 occurs every time the input sequence 010 is completed provided that the sequence 100 has never occurred. An output Z2 = 1 occurs every time the input sequence 100 is completed. Note that once a Z2 = 1 output has occurred, Z1 = 1 can never occur, but not vice-versa. Derive a Mealy state graph and table with a minimum number of states. Also realize the network using JK flip-flops and NAND gates. (20)

  1. (a) Write a Verilog code for 4-bit binary to gray code converter using if-else statement. (10)
  2. (b) Design a full-adder using : (10)
    1. i) Only NAND gates
    2. ii) Only NOR gates
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  1. (a) What is meta-stability in digital circuits? Discuss methods to eliminate it. (10)
  2. (b) Explain leakage currents and refresh operation in DRAM cells. (10)

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  1. (a) List the various scalar data types and explain them with the help of examples. (10)
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  3. (b) Write a VHDL code for 4-bit Binary to Gray code converter using behavioral style of modeling. (10)
  1. (a) Explain the structural difference between a ROM and a PLA and implement the following function using ROM and PLA design : F (A, B, C, D) = S (0, 1, 3, 6, 8, 9, 10, 12, 15). (14)
  2. (b) Discuss the role of CLBs in FPGAs. (6)
  1. (a) Differentiate between sequential and concurrent circuits by giving an appropriate example. (10)
  2. (b) Write a short note on : (10)
    1. i) CPLD
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    3. ii) PLA

NOTE : Disclosure of Identity by writing Mobile No. or Making of passing request on any page of Answer Sheet will lead to UMC against the Student.


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