Download GTU BE/B.Tech 2019 Winter 3rd Sem New 3130704 Digital Fundamentals Question Paper

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Enrolment No.

Subject Code: 3130704

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GUJARAT TECHNOLOGICAL UNIVERSITY

BE - SEMESTER- III (New) EXAMINATION — WINTER 2019

Subject Name: Digital Fundamentals

Time: 02:30 PM TO 05:00 PM

Instructions:

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1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.

Q.1 Do as Directed

1. Given that (16)₁₀ = (100)_x. Find the value of x. (03 Marks)

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2. Add (6E)₁₆ and (C5)₁₆. (04 Marks)
3. (1011011101101110)₂ = ( )₈ = ( )₁₆ (07 Marks)

Q.2 (a) State and explain De Morgan’s theorems with truth tables. (03 Marks)

(b) Implement AND, OR, & EX-OR gates using NAND & NOR gates. (04 Marks)

(c) Express the Boolean function F = A + B’C in a sum of minterms. (07 Marks)

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OR

(a) Reduce the expression F=A[ B+ C’ (AB + AC’)’] (03 Marks)

(b) Simplify the following Boolean function by using the tabulation method. (04 Marks)

F(A,B,C,D)=Sm (0, 1, 2,8, 10, 11, 14, 15) (07 Marks)

Q.3 (a) Using D & E as the MEV, Reduce (03 Marks)

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F=A’B’C’ + A’B’CD + A’BCE’ + A’BC’E + AB’C + ABC + ABC’D". (04 Marks)

(b) Simplify the Boolean function (07 Marks)

F(w,x,y,z)=Sm(0,1,2,4,5,6,8,9, 12,13, 14)

OR

(a) Design 1 - bit Magnitude Comparator. (03 Marks)

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(b) Design a full adder and realize full adder using 3X8 Decoder and 2 OR gates. (04 Marks)

(c) Simplify the Boolean function F=A’B’C’+B’CD’+ A’BCD’ + AB’C’ (07 Marks)

Q.4 (a) Explain 4 — bit parallel adder: (03 Marks)

(b) Implement the following function using 8X1 MUX (04 Marks)

F(A,B,C,D)=Sm (0,1,3,4, 8,9, 15) (07 Marks)

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OR

(a) Explain SR flip-flop using characteristic table & characteristic equation. (03 Marks)

(b) Explain the working of SISO shift register. (04 Marks)

(c) Design a counter with the following binary sequence: 0, 1, 3, 7, 6, 4 and repeat. Use T flip-flops. (07 Marks)

Q.5 (a) What is the race around condition in JK flip-flop? (03 Marks)

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(b) Design 4-bit Ring counter using D flip-flip. (04 Marks)

(c) Design JK flip-flip using D flip-flip. (07 Marks)

OR

(a) Explain the specification of D/A converter. (03 Marks)

(b) Explain R-2R ladder type D/A converter. (04 Marks)

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(c) Explain Successive Approximation type A/D converter. (07 Marks)

Q.6 (a) Explain classification of Memories. (03 Marks)

(b) Explain the types of ROM. (04 Marks)

(c) A combinational circuit is defined by the function (07 Marks)

F₁(A,B,C)=Sm(4,5,7) F₂(A,B,C)=Sm(3,5,7)

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Implement the circuit with a PLA having 3 inputs, 3 product term & 2 outputs.

Date: 3/12/2019

Total Marks: 70

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