Download GTU BE/B.Tech 2019 Winter 6th Sem New 2160909 Advance Microcontrollers Question Paper

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GUJARAT TECHNOLOGICAL UNIVERSITY
BE - SEMESTER- VI (New) EXAMINATION - WINTER 2019

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Instructions:

1. Attempt all questions.

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2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.

MARKS

Q.1

1. List advantage and disadvantages of Harvard Architecture over Von Neumann architecture (03)

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2. Give the significance of C compiler, Debugger, Assembler and Flash programmer (04)
3. Why Watch-dog timer is necessary for embedded systems? Explain the watchdog timer of P89V51RD2 in detail (07)

Q.2

1. Draw PCA interrupt system of P89V51RD2 (03)
2. List out steps required to enable interrupts safely in an IRQ handler (04)

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3. Draw and explain block diagram of MPC 3304(ADC). (07)

OR

1. Explain what is PWM? Write an embedded C program to generate PWM in xx51 microcontroller. Assume necessary data and clearly mention your assumptions. (07)

Q.3

1. Differentiate ISP (In System Programming) and IAP (In Application Programming). (03)

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2. Explain the CMOD, CCON registers of P89V51RD2. (04)
3. Discuss I2C & SPI communication protocol for microcontrollers. (07)

OR

1. Explain the SPI control & SPI status registers in P89V51RD2 (03)
2. Explain PWM mode of P89V51RD2 PCA timer in detail. (04)

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3. Discuss the pulse- width modulator mode of 89V51RD2 microcontroller with C programming code (07)

Q.4

1. Explain Round Robin with Interrupt Architecture. (03)
2. Explain multi-AHB bus matrix in STM32F4XX. (04)
3. Explain the NVIC operation exception entry and exit of STM32F4XX (07)

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OR

1. Explain pointer to structure with example (03)
2. Draw and explain reset circuit of STM32F4xx. (04)
3. Explain the feature of GPIO in detail. (07)

Q.5

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1. Explain the concept of memory segmentation in Cortex processor. (03)
2. Explain the main feature of TIM6 & TIM7 in STM32F4XX (04)
3. Explain the bit banding technique in cortex M processors (07)

OR

1. What is Enumerator? (03)

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2. Explain tail chaining in cortex M processors. (04)
3. Explain the 3-stage pipelining in cortex CPU (07)

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