Download GTU BE/B.Tech 2019 Winter 7th Sem New 2172409 Digital Signal Processing For Power Electronics Question Paper

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GUJARAT TECHNOLOGICAL UNIVERSITY
BE - SEMESTER- VII (New) EXAMINATION — WINTER 2019

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Subject Code: 2172409 Date: 03/12/2019
Subject Name: Digital Signal Processing for Power Electronics
Time: 10:30 AM TO 01:00 PM Total Marks: 70

Instructions:

1. Attempt all questions.

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2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.

Q.1 (a) Differentiate Energy signal and Power signal. 03
(b) Enlist applications of DSP. 04
(c) Classify and explain types of systems with examples. 07

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Q.2 (a) Check the system described by equation y(t) = sinx(t) for time variant. 03
(b) Enlist standard Discrete time signal with neat sketches. 04
(c) What is MAC? Explain it and state its importance with reference to DSP. 07

OR

(c) Draw and explain the block diagram of architecture for modified Harvard digital signal processor. 07

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Q.3 (a) State relation between Fourier Transform & Z-Transform. 03
(b) Find the N point DFT for x(n) = aⁿ for 0<a<1 04
(c) What do you understand by twiddle factor? Derive the relationship between DFT and Z Transform. 07

OR

Q.3 (a) Explain any three property of DFT. 03

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(b) Determine the periodicity of the following signal. 04
(1) x1(t) = sin(5t) (2) x2(t) = sin(20pt)
(3) x3(t) = x1(t) + x2(t)
(c) Find x(n) if X(z) = (1+0.5z^-1)/(1-0.5z^-1) 07

Q.4 (a) Define sampling and aliasing. 03

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(b) Draw the structure of cascade realization of
H(z) = 1-z^-1 / (1-0.5z^-1)(1-0.125z^-1) 04
(c) Explain following. (1) Radix-2 FFT algorithm (2) DIT algorithm. 07

OR

Q.4 (a) Discuss the need of interlocking in brief. 03

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(b) Draw the structure of parallel realization of
H(z) = 1-z^-1 / (1-0.5z^-1)(1-0.125z^-1) 04
(c) Find the inverse DFT of X(k) = {1,2,3,4}. 07

Q.5 (a) Explain the concept of pipelining in DSP. 03
(b) How reduction in product round off errors is achieved? 04

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(c) Explain the structures for realization of FIR systems. 07

OR

Q.5 (a) Explain in brief the fixed point representation of binary numbers. 03
(b) What are the different formats of fixed point representation? 04
(c) Explain the structures for realization of IIR systems. 07

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