GUJARAT TECHNOLOGICAL UNIVERSITY
BE - SEMESTER- III (New) EXAMINATION — WINTER 2019
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Subject Code: 2131704 Date: 3/12/2019
Subject Name: Digital Logic Circuits
Time: 02:30 PM TO 05:00 PM Total Marks: 70
Instructions:
- Attempt all questions.
- Make suitable assumptions wherever necessary.
- Figures to the right indicate full marks.
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Q.1 (a) What is Race condition? 03
(b) Define: 1) Fan-in 2) Fan-out 04
3) Propagation Delay 4) Noise margin
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(c) State and Prove De Morgan’s theorem. 07
Q.2 (a) Write a short note on PLA. 03
(b) Convert the following 04
- Decimal number 256 to Hexadecimal equivalent.
- Decimal number 648 to octal equivalent.
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(c) Draw logic diagram, symbol and characteristic table for JK flip-flop. 07
OR
(c) Explain positive edge-triggered D flip-flop. 07
Q.3 (a) Explain state table, state diagram with example. 03
(b) Design full subtractor using half subtractors. 04
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(c) With the help of a neat diagram, explain the working of a two-input TTL 07
NAND gate.
OR
Q.3 (a) Realize Ex-OR gate and NOT gate using NOR gate. 03
(b) Reduce the expression: 04
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- A[B+ C(AB + AC)]
- (A + BC) (AB +ABC)
(c) Explain BCD-to-Seven segment decoder. 07
Q.4 (a) Draw neat diagram of 3x8 decoder circuit. 03
(b) Simplify the Boolean function using K-map: 04
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F(wxyz) = S m(0,1,2,4,5,6,8,9,12,13,14)
(c) Explain with logic diagram of 4-bit serial-in serial-out shift register. 07
OR
Q.4 (a) Write a short note on shift register. 03
(b) Write a short note on Arithmetic micro operation in detail. 04
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(c) Explain 4-bit ring counter with circuit diagram and waveforms. 07
Q.5 (a) Convert SR flip-flop into T flip-flop. 03
(b) Draw neat diagram of 2-bit magnitude comparator circuit. 04
(c) Write the state table and state equation with the state diagram of clocked D 07
flip-flop.
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OR
Q.5 (a) Explain 2 bit binary UP counter using JK flip-flops. 03
(b) Distinguish between combinational and sequential switching circuits. 04
(c) Explain Successive Approximation ADC. 07
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