Download GTU BE/B.Tech 2019 Summer 6th Sem New 2161101 Vlsi Technology And Design Question Paper

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5 B “VI(NEW) — EXAMINATION - SUMMER 2019

Subject Name:VLSI Technology & Design

Time:10:30 AM TO 01:00 PM

Total Marks: 70

Instructions:

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1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks

Q.1

1. Explain various VLSI design concepts - regularity, modularity, and locality. 03

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2. Explain LOCOS technique used for device isolation and state its advantages over the Etched Field Oxidation technique. 04
3. Explain the behaviour of MOS device under external bias with the help of energy band diagrams and derive the relationship for maximum depletion width at oxide-semiconductor surface. 07

Q.2

1. Compare ion implantation and diffusion methods used for impurity doping. 03
2. Explain the substrate bias effect in nMOS and pMOS devices. 04

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3. Explain the experimental methods of measuring following parameters of nMOS: Threshold voltage (V_T), channel length modulation coefficient (?), substrate-bias coefficient (?), transconductance parameter (k) 07

OR

1. Consider a MOS system with the following parameters:
   • t_ox=20nm
   • F_Pgc= -0.85V
   • N_i=2x10¹⁵cm^-3

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   • Q_ox= 3x2x10¹¹ C/cm²
   1. Determine the threshold voltage, V_T0-under zero bias at room temperature (T = 300 °K). Consider e_ox = 3.97e₀ and e_si = 11.7e₀
   2. Determine the type (p-type or n-type) and amount of channel implant (N_I /cm²) required to change the threshold voltage to 0.8 V.

Q.3

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1. Explain the effect of noise on the performance of a digital system and define noise margins (NM_L and NM_H). 03
2. Explain resistive load inverter in brief and derive V_IL and V_IH critical voltage equations for this inverter. 04
3. Explain the MOSFET capacitances in detail. 07

OR

1. Draw the nMOS depletion load and CMOS implementations of the following Boolean function: Y = A(D +E)+ BC 03

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2. Explain the latch-up problem observed in CMOS circuits and mention various techniques to prevent it. 04
3. Consider a CMOS inverter with the following parameters:
   • V_DD =3.3V
   • V_T0,n= 0.6V
   • V_T0,p= -0.7V
   • k_n= 200uA/V²

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   • k_p = 80uA/V²
   Calculate the noise margins of the circuit. Consider k_n = 2.5V and V_GS ? |V_T0,p| as it is not a symmetric CMOS inverter. 07

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Q.4

1. Sketch and explain the CMOS edge-triggered master-slave D-flip flop. 03

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2. Differentiate the ratioed and ratio-less logic circuits with examples. 04
3. Explain the Elmore delay calculation method used for complex RC network. Derive a formula for Elmore delay T_PD. 07

OR

1. Compare Static and Dynamic CMOS logic circuits. 03
2. Write a note on CMOS Ring Oscillator circuit. 04

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3. Explain high performance Domino CMOS logic circuits. 07

Q.5

1. Implement 2-to-1 MUX and XOR functions using CMOS Transmission Gates (TGs). 03
2. What is clock-skew? Explain on-chip clock generation and distribution. 04
3. Explain the basic principle of dynamic logic using nMOS pass transistor and discuss the logic ‘1’ and logic ‘0’ transfer. 07

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OR

1. Explain various types of faults observed during the chip testing. 03
2. Compare FPGA and CPLD. 04
3. Explain the Built-in-Self-Test (BIST) technique for circuit testing. 07

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